diff --git a/.cargo/config.toml b/.cargo/config.toml new file mode 100644 index 0000000..5dcef74 --- /dev/null +++ b/.cargo/config.toml @@ -0,0 +1,11 @@ +# default runner starts a GDB sesssion, which requires OpenOCD to be +# running, e.g., +## openocd -s C:\OpenOCD\openocd\scripts -f board/ti_ek-tm4c123gxl.cfg +# depending on your local GDB, pick one of the following +[target.thumbv7em-none-eabihf] +runner = "arm-none-eabi-gdb -q -x openocd.gdb" +rustflags = [ + "-C", "link-arg=-Tlink.x", +] +[build] +target = "thumbv7em-none-eabihf" diff --git a/Cargo.lock b/Cargo.lock new file mode 100644 index 0000000..34f26b8 --- /dev/null +++ b/Cargo.lock @@ -0,0 +1,183 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 3 + +[[package]] +name = "bare-metal" +version = "0.2.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5deb64efa5bd81e31fcd1938615a6d98c82eafcbcd787162b6f63b91d6bac5b3" +dependencies = [ + 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"a210d160f08b701c8721ba1c726c11662f877ea6b7094007e1ca9a1041945034" + +[[package]] +name = "vcell" +version = "0.1.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002" + +[[package]] +name = "void" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d" + +[[package]] +name = "volatile-register" +version = "0.2.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc" +dependencies = [ + "vcell", +] diff --git a/Cargo.toml b/Cargo.toml new file mode 100644 index 0000000..c42a2e1 --- /dev/null +++ b/Cargo.toml @@ -0,0 +1,14 @@ +[package] +name = "tivatest" +version = "0.1.0" +edition = "2021" +build="build.rs" + +[dependencies] +cortex-m = "0.7" +cortex-m-rt = {version="0.7",features=["device"]} +tm4c123x = {version="0.9.2", features=["rt"]} +embedded-hal = "0.2" + +[dependencies.panic-halt] +version = "0.2" diff --git a/aes.o b/aes.o new file mode 100644 index 0000000..a2ca2f0 Binary files /dev/null and b/aes.o differ diff --git a/build.rs b/build.rs new file mode 100644 index 0000000..fea20e8 --- /dev/null +++ b/build.rs @@ -0,0 +1,34 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; + +fn main() { + // Put the linker script somewhere the linker can find it + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("memory.x")) + .unwrap() + .write_all(include_bytes!("memory.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + + println!("cargo:rerun-if-changed=build.rs"); + println!("cargo:rerun-if-changed=memory.x"); + // tell rustc to link with some driverlib library + println!("cargo:rustc-link=gpio"); + println!("cargo:rustc-link=uart"); + println!("cargo:rustc-link=sysctl"); + println!("cargo:rustc-link=systick"); + println!("cargo:rustc-link=timer"); + println!("cargo:rustc-link=i2c"); + println!("cargo:rustc-link=interrupt"); + println!("cargo:rustc-link=adc"); + println!("cargo:rustc-link=ssi"); + + + + // and it should search the Cargo.toml directory for that library + println!("cargo:rustc-link-search={}", std::env::var("CARGO_MANIFEST_DIR").unwrap()); +} + + diff --git a/can.o b/can.o new file mode 100644 index 0000000..10f8288 Binary files /dev/null and b/can.o differ diff --git a/comp.o b/comp.o new file mode 100644 index 0000000..fea237f Binary files /dev/null and b/comp.o differ diff --git a/cpu.o b/cpu.o new file mode 100644 index 0000000..e5e57e5 Binary files /dev/null and b/cpu.o differ diff --git a/crc.o b/crc.o new file mode 100644 index 0000000..4542bf1 Binary files /dev/null and b/crc.o differ diff --git a/des.o b/des.o new file mode 100644 index 0000000..af57f75 Binary files /dev/null and b/des.o differ diff --git a/device.x b/device.x new file mode 100644 index 0000000..98c3a97 --- /dev/null +++ b/device.x @@ -0,0 +1,79 @@ +PROVIDE(GPIOA = DefaultHandler); +PROVIDE(GPIOB = DefaultHandler); +PROVIDE(GPIOC = DefaultHandler); +PROVIDE(GPIOD = DefaultHandler); +PROVIDE(GPIOE = DefaultHandler); +PROVIDE(UART0 = DefaultHandler); +PROVIDE(UART1 = DefaultHandler); +PROVIDE(SSI0 = DefaultHandler); +PROVIDE(I2C0 = DefaultHandler); +PROVIDE(PWM0_FAULT = DefaultHandler); +PROVIDE(PWM0_0 = DefaultHandler); +PROVIDE(PWM0_1 = DefaultHandler); +PROVIDE(PWM0_2 = DefaultHandler); +PROVIDE(QEI0 = DefaultHandler); +PROVIDE(ADC0SS0 = DefaultHandler); +PROVIDE(ADC0SS1 = DefaultHandler); +PROVIDE(ADC0SS2 = DefaultHandler); +PROVIDE(ADC0SS3 = DefaultHandler); +PROVIDE(WATCHDOG = DefaultHandler); +PROVIDE(TIMER0A = DefaultHandler); +PROVIDE(TIMER0B = DefaultHandler); +PROVIDE(TIMER1A = DefaultHandler); +PROVIDE(TIMER1B = DefaultHandler); +PROVIDE(TIMER2A = DefaultHandler); +PROVIDE(TIMER2B = DefaultHandler); +PROVIDE(COMP0 = DefaultHandler); +PROVIDE(COMP1 = DefaultHandler); +PROVIDE(SYSCTL = DefaultHandler); +PROVIDE(FLASH = DefaultHandler); +PROVIDE(GPIOF = DefaultHandler); +PROVIDE(UART2 = DefaultHandler); +PROVIDE(SSI1 = DefaultHandler); +PROVIDE(TIMER3A = DefaultHandler); +PROVIDE(TIMER3B = DefaultHandler); +PROVIDE(I2C1 = DefaultHandler); +PROVIDE(QEI1 = DefaultHandler); +PROVIDE(CAN0 = DefaultHandler); +PROVIDE(CAN1 = DefaultHandler); +PROVIDE(HIBERNATE = DefaultHandler); +PROVIDE(USB0 = DefaultHandler); +PROVIDE(PWM0_3 = DefaultHandler); +PROVIDE(UDMA = DefaultHandler); +PROVIDE(UDMAERR = DefaultHandler); +PROVIDE(ADC1SS0 = DefaultHandler); +PROVIDE(ADC1SS1 = DefaultHandler); +PROVIDE(ADC1SS2 = DefaultHandler); +PROVIDE(ADC1SS3 = DefaultHandler); +PROVIDE(SSI2 = DefaultHandler); +PROVIDE(SSI3 = DefaultHandler); +PROVIDE(UART3 = DefaultHandler); +PROVIDE(UART4 = DefaultHandler); +PROVIDE(UART5 = DefaultHandler); +PROVIDE(UART6 = DefaultHandler); +PROVIDE(UART7 = DefaultHandler); +PROVIDE(I2C2 = DefaultHandler); +PROVIDE(I2C3 = DefaultHandler); +PROVIDE(TIMER4A = DefaultHandler); +PROVIDE(TIMER4B = DefaultHandler); +PROVIDE(TIMER5A = DefaultHandler); +PROVIDE(TIMER5B = DefaultHandler); +PROVIDE(WTIMER0A = DefaultHandler); +PROVIDE(WTIMER0B = DefaultHandler); +PROVIDE(WTIMER1A = DefaultHandler); +PROVIDE(WTIMER1B = DefaultHandler); +PROVIDE(WTIMER2A = DefaultHandler); +PROVIDE(WTIMER2B = DefaultHandler); +PROVIDE(WTIMER3A = DefaultHandler); +PROVIDE(WTIMER3B = DefaultHandler); +PROVIDE(WTIMER4A = DefaultHandler); +PROVIDE(WTIMER4B = DefaultHandler); +PROVIDE(WTIMER5A = DefaultHandler); +PROVIDE(WTIMER5B = DefaultHandler); +PROVIDE(SYSEXC = DefaultHandler); +PROVIDE(PWM1_0 = DefaultHandler); +PROVIDE(PWM1_1 = DefaultHandler); +PROVIDE(PWM1_2 = DefaultHandler); +PROVIDE(PWM1_3 = DefaultHandler); +PROVIDE(PWM1_FAULT = DefaultHandler); + diff --git a/eeprom.o b/eeprom.o new file mode 100644 index 0000000..c1a73ee Binary files /dev/null and b/eeprom.o differ diff --git a/emac.o b/emac.o new file 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file mode 100644 index 0000000..c259b4a Binary files /dev/null and b/libsystick.a differ diff --git a/libtimer.a b/libtimer.a new file mode 100644 index 0000000..7fdaf72 Binary files /dev/null and b/libtimer.a differ diff --git a/libuart.a b/libuart.a new file mode 100644 index 0000000..40f08e5 Binary files /dev/null and b/libuart.a differ diff --git a/libudma.a b/libudma.a new file mode 100644 index 0000000..c590ea2 Binary files /dev/null and b/libudma.a differ diff --git a/libusb.a b/libusb.a new file mode 100644 index 0000000..d774074 Binary files /dev/null and b/libusb.a differ diff --git a/libwatchdog.a b/libwatchdog.a new file mode 100644 index 0000000..31bc5b5 Binary files /dev/null and b/libwatchdog.a differ diff --git a/memory.x b/memory.x new file mode 100644 index 0000000..6f1910a --- /dev/null +++ b/memory.x @@ -0,0 +1,16 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* Sections */ +SECTIONS +{ + /* Stack section (placed at the top of RAM) */ + .stack : ALIGN(4){ + _stack_top = ORIGIN(RAM) + LENGTH(RAM); /* Top of the stack */ + . = _stack_top - 0x400; /* Allocate 1 KB for stack */ + _stack_bottom = .; /* Bottom of the stack */ + } > RAM +} diff --git a/mpu.o b/mpu.o new file mode 100644 index 0000000..24eae19 Binary files /dev/null and b/mpu.o differ diff --git a/onewire.o b/onewire.o new file mode 100644 index 0000000..1511e34 Binary files /dev/null and b/onewire.o differ diff --git a/openocd.gdb b/openocd.gdb new file mode 100644 index 0000000..72f99ae --- /dev/null +++ b/openocd.gdb @@ -0,0 +1,35 @@ +target extended-remote :3333 + +# print demangled symbols +set print asm-demangle on + +# Reset and halt the target +monitor reset halt + +# detect unhandled exceptions, hard faults and panics +break DefaultHandler +break UserHardFault +break rust_begin_unwind + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +#monitor arm semihosting enable + +# # send captured ITM to the file itm.fifo +# # (the microcontroller SWO pin must be connected to the programmer SWO pin) +# # 8000000 must match the core clock frequency +# monitor tpiu config internal itm.txt uart off 8000000 + +# # OR: make the microcontroller SWO pin output compatible with UART (8N1) +# # 8000000 must match the core clock frequency +# # 2000000 is the frequency of the SWO pin +# monitor tpiu config external uart off 8000000 2000000 + +# # enable ITM port 0 +# monitor itm port 0 on + +load + +# start the process but immediately halt the processor +#stepi diff --git a/pwm.o b/pwm.o new file mode 100644 index 0000000..3287899 Binary files /dev/null and b/pwm.o differ diff --git a/qei.o b/qei.o new file mode 100644 index 0000000..67947a1 Binary files /dev/null and b/qei.o differ diff --git a/readme.md b/readme.md new file mode 100644 index 0000000..b7b9b19 --- /dev/null +++ b/readme.md @@ -0,0 +1,67 @@ +# TivaCCriticalRegion + +This repository demonstrates how to use `cortex_m::interrupt::free` to safely access shared data in a critical section on the TI TM4C123GXL LaunchPad using Rust. It is a minimal embedded example that toggles an onboard LED based on a shared flag, set inside a timer interrupt and cleared in the main loop. + +Unlike platforms with native atomic support, this example uses `Mutex>` instead of `AtomicBool` to maintain compatibility with microcontrollers that do not fully support atomic operations in `no_std` environments. + +## Features + +- Runs on TI TM4C123GXL LaunchPad (Cortex-M4F) +- Written in safe `no_std` Rust +- Demonstrates safe shared-state access using `cortex_m::interrupt::free` +- Uses a `Mutex>` flag shared between main and interrupt context +- Blinks onboard LED when a timer-based flag is set + +## Requirements + +- Rust nightly toolchain with support for `thumbv7em-none-eabihf` +- `cortex-m` and `cortex-m-rt` crates +- Flashing tools like OpenOCD, probe-rs, or LM Flash Programmer +- TivaWare and [TivaCRustWare](https://github.itap.purdue.edu/wang32/TivaCRustWare) HAL + +## Setup + +1. Add the target: + ```bash + rustup target add thumbv7em-none-eabihf + ``` + +2. Clone the repository: + ```bash + git clone https://github.itap.purdue.edu/wang32/TivaCCriticalRegion.git + cd TivaCCriticalRegion + ``` + +3. Build the project: + ```bash + cargo build --release + ``` + +4. Flash to the TM4C123GXL board using your preferred method. + +## Code Structure + +- `SECONDS_FLAG` is a `Mutex>` shared between main and an interrupt handler. +- The interrupt handler sets `SECONDS_FLAG` to true. +- The main loop checks and clears `SECONDS_FLAG`; if set, it toggles the LED. + +## Example Logic Snippet + +```rust +interrupt::free(|cs| { + let flag = SECONDS_FLAG.borrow(cs); + if flag.get() { + flag.set(false); + GREEN_LED.toggle(); + } +}); +``` + +## License + +This project is intended for educational and instructional use. + +## Acknowledgments + +Inspired by the Rust embedded community and based on the `cortex-m` crate's safe interrupt handling patterns. + diff --git a/shamd5.o b/shamd5.o new file mode 100644 index 0000000..706fd2e Binary files /dev/null and b/shamd5.o differ diff --git a/src/adc.rs b/src/adc.rs new file mode 100644 index 0000000..23b399c --- /dev/null +++ b/src/adc.rs @@ -0,0 +1,191 @@ + +pub fn ADCIntUnregisterWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCIntUnregister(ui32Base, ui32SequenceNum); } +} + +pub fn ADCIntDisableWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCIntDisable(ui32Base, ui32SequenceNum); } +} + +pub fn ADCIntEnableWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCIntEnable(ui32Base, ui32SequenceNum); } +} + +pub fn ADCIntStatusWrap(ui32Base: u32, ui32SequenceNum: u32, bMasked: bool) -> u32 { + unsafe { ADCIntStatus(ui32Base, ui32SequenceNum, bMasked) } +} + +pub fn ADCIntClearWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCIntClear(ui32Base, ui32SequenceNum); } +} + +pub fn ADCSequenceEnableWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCSequenceEnable(ui32Base, ui32SequenceNum); } +} + +pub fn ADCSequenceDisableWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCSequenceDisable(ui32Base, ui32SequenceNum); } +} + +pub fn ADCSequenceConfigureWrap(ui32Base: u32, ui32SequenceNum: u32, ui32Trigger: u32, ui32Priority: u32) { + unsafe { ADCSequenceConfigure(ui32Base, ui32SequenceNum, ui32Trigger, ui32Priority); } +} + +pub fn ADCSequenceOverflowWrap(ui32Base: u32, ui32SequenceNum: u32) -> i32 { + unsafe { ADCSequenceOverflow(ui32Base, ui32SequenceNum) } +} + +pub fn ADCSequenceOverflowClearWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCSequenceOverflowClear(ui32Base, ui32SequenceNum); } +} + +pub fn ADCSequenceUnderflowWrap(ui32Base: u32, ui32SequenceNum: u32) -> i32 { + unsafe { ADCSequenceUnderflow(ui32Base, ui32SequenceNum) } +} + +pub fn ADCSequenceUnderflowClearWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCSequenceUnderflowClear(ui32Base, ui32SequenceNum); } +} + +pub fn ADCSequenceDataGetWrap(ui32Base: u32, ui32SequenceNum: u32, pui32Buffer: *const u32) -> i32 { + unsafe { ADCSequenceDataGet(ui32Base, ui32SequenceNum, pui32Buffer) } +} + +pub fn ADCProcessorTriggerWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCProcessorTrigger(ui32Base, ui32SequenceNum); } +} + +pub fn ADCHardwareOversampleConfigureWrap(ui32Base: u32, ui32Factor: u32) { + unsafe { ADCHardwareOversampleConfigure(ui32Base, ui32Factor); } +} + +pub fn ADCClockConfigSetWrap(ui32Base: u32, ui32Config: u32, ui32ClockDiv: u32) { + unsafe { ADCClockConfigSet(ui32Base, ui32Config, ui32ClockDiv); } +} + +pub fn ADCClockConfigGetWrap(ui32Base: u32, pui32ClockDiv: *const u32) -> u32 { + unsafe { ADCClockConfigGet(ui32Base, pui32ClockDiv) } +} + +pub fn ADCComparatorConfigureWrap(ui32Base: u32, ui32Comp: u32, ui32Config: u32) { + unsafe { ADCComparatorConfigure(ui32Base, ui32Comp, ui32Config); } +} + +pub fn ADCComparatorRegionSetWrap(ui32Base: u32, ui32Comp: u32, ui32LowRef: u32, ui32HighRef: u32) { + unsafe { ADCComparatorRegionSet(ui32Base, ui32Comp, ui32LowRef, ui32HighRef); } +} + +pub fn ADCComparatorResetWrap(ui32Base: u32, ui32Comp: u32, bTrigger: bool, bInterrupt: bool) { + unsafe { ADCComparatorReset(ui32Base, ui32Comp, bTrigger, bInterrupt); } +} + +pub fn ADCComparatorIntDisableWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCComparatorIntDisable(ui32Base, ui32SequenceNum); } +} + +pub fn ADCComparatorIntEnableWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCComparatorIntEnable(ui32Base, ui32SequenceNum); } +} + +pub fn ADCComparatorIntStatusWrap(ui32Base: u32) -> u32 { + unsafe { ADCComparatorIntStatus(ui32Base) } +} + +pub fn ADCComparatorIntClearWrap(ui32Base: u32, ui32Status: u32) { + unsafe { ADCComparatorIntClear(ui32Base, ui32Status); } +} + +pub fn ADCIntDisableExWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { ADCIntDisableEx(ui32Base, ui32IntFlags); } +} + +pub fn ADCIntEnableExWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { ADCIntEnableEx(ui32Base, ui32IntFlags); } +} + +pub fn ADCIntStatusExWrap(ui32Base: u32, bMasked: bool) -> u32 { + unsafe { ADCIntStatusEx(ui32Base, bMasked) } +} + +pub fn ADCIntClearExWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { ADCIntClearEx(ui32Base, ui32IntFlags); } +} + +pub fn ADCSequenceDMAEnableWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCSequenceDMAEnable(ui32Base, ui32SequenceNum); } +} + +pub fn ADCSequenceDMADisableWrap(ui32Base: u32, ui32SequenceNum: u32) { + unsafe { ADCSequenceDMADisable(ui32Base, ui32SequenceNum); } +} + +pub fn ADCBusyWrap(ui32Base: u32) -> bool { + unsafe { ADCBusy(ui32Base) } +} + +pub fn ADCReferenceSetWrap(ui32Base: u32, ui32Ref: u32) { + unsafe { ADCReferenceSet(ui32Base, ui32Ref); } +} + +pub fn ADCReferenceGetWrap(ui32Base: u32) -> u32 { + unsafe { ADCReferenceGet(ui32Base) } +} + +pub fn ADCPhaseDelaySetWrap(ui32Base: u32, ui32Phase: u32) { + unsafe { ADCPhaseDelaySet(ui32Base, ui32Phase); } +} + +pub fn ADCPhaseDelayGetWrap(ui32Base: u32) -> u32 { + unsafe { ADCPhaseDelayGet(ui32Base) } +} + +pub fn ADCSampleRateSetWrap(ui32Base: u32, ui32ADCClock: u32, ui32Rate: u32) { + unsafe { ADCSampleRateSet(ui32Base, ui32ADCClock, ui32Rate); } +} + +pub fn ADCSampleRateGetWrap(ui32Base: u32) -> u32 { + unsafe { ADCSampleRateGet(ui32Base) } +} + + +#[link(name="adc", kind="static")] +extern "C" { + pub fn ADCIntRegister(ui32Base: u32, ui32SequenceNum: u32, pfnHandler: Option ); + pub fn ADCIntUnregister(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCIntDisable(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCIntEnable(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCIntStatus(ui32Base: u32, ui32SequenceNum: u32, bMasked: bool) -> u32; + pub fn ADCIntClear(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCSequenceEnable(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCSequenceDisable(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCSequenceConfigure(ui32Base: u32, ui32SequenceNum: u32, ui32Trigger: u32, ui32Priority: u32); + pub fn ADCSequenceOverflow(ui32Base: u32, ui32SequenceNum: u32) -> i32; + pub fn ADCSequenceOverflowClear(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCSequenceUnderflow(ui32Base: u32, ui32SequenceNum: u32) -> i32; + pub fn ADCSequenceUnderflowClear(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCSequenceDataGet(ui32Base: u32, ui32SequenceNum: u32, pui32Buffer: *const u32) -> i32; + pub fn ADCProcessorTrigger(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCHardwareOversampleConfigure(ui32Base: u32, ui32Factor: u32); + pub fn ADCClockConfigSet(ui32Base: u32, ui32Config: u32, ui32ClockDiv: u32); + pub fn ADCClockConfigGet(ui32Base: u32, pui32ClockDiv: *const u32) -> u32; + pub fn ADCComparatorConfigure(ui32Base: u32, ui32Comp: u32, ui32Config: u32); + pub fn ADCComparatorRegionSet(ui32Base: u32, ui32Comp: u32, ui32LowRef: u32, ui32HighRef: u32); + pub fn ADCComparatorReset(ui32Base: u32, ui32Comp: u32, bTrigger: bool, bInterrupt: bool); + pub fn ADCComparatorIntDisable(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCComparatorIntEnable(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCComparatorIntStatus(ui32Base: u32) -> u32; + pub fn ADCComparatorIntClear(ui32Base: u32, ui32Status: u32); + pub fn ADCIntDisableEx(ui32Base: u32, ui32IntFlags: u32); + pub fn ADCIntEnableEx(ui32Base: u32, ui32IntFlags: u32); + pub fn ADCIntStatusEx(ui32Base: u32, bMasked: bool) -> u32; + pub fn ADCIntClearEx(ui32Base: u32, ui32IntFlags: u32); + pub fn ADCSequenceDMAEnable(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCSequenceDMADisable(ui32Base: u32, ui32SequenceNum: u32); + pub fn ADCBusy(ui32Base: u32) -> bool; + pub fn ADCReferenceSet(ui32Base: u32, ui32Ref: u32); + pub fn ADCReferenceGet(ui32Base: u32) -> u32; + pub fn ADCPhaseDelaySet(ui32Base: u32, ui32Phase: u32); + pub fn ADCPhaseDelayGet(ui32Base: u32) -> u32; + pub fn ADCSampleRateSet(ui32Base: u32, ui32ADCClock: u32, ui32Rate: u32); + pub fn ADCSampleRateGet(ui32Base: u32) -> u32; +} \ No newline at end of file diff --git a/src/can.rs b/src/can.rs new file mode 100644 index 0000000..b6d31f6 --- /dev/null +++ b/src/can.rs @@ -0,0 +1,217 @@ +//! Definitions for CAN controller FFI interface. +//! This module defines C-compatible structs and enums for use with external CAN libraries. + +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct tCANMsgObject { + /// The CAN message identifier used for 11 or 29 bit identifiers. + pub ui32MsgID: u32, + + /// The message identifier mask used when identifier filtering is enabled. + pub ui32MsgIDMask: u32, + + /// Status flags and settings specified by `tCANObjFlags`. + pub ui32Flags: u32, + + /// Number of bytes of data in the message object. + pub ui32MsgLen: u32, + + /// Pointer to the message object's data. + pub pui8MsgData: *const u8, +} + +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct tCANBitClkParms { + /// Synchronization, Propagation, and Phase Buffer 1 segments (2-16 time quanta). + pub ui32SyncPropPhase1Seg: u32, + + /// Phase Buffer 2 segment (1-8 time quanta). + pub ui32Phase2Seg: u32, + + /// Resynchronization Jump Width (1-4 time quanta). + pub ui32SJW: u32, + + /// CAN_CLK divider to determine time quanta (1-1023). + pub ui32QuantumPrescaler: u32, +} + +#[repr(C)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum tCANIntStsReg { + /// Read the CAN interrupt status information. + CAN_INT_STS_CAUSE = 0, + + /// Read a message object's interrupt status. + CAN_INT_STS_OBJECT = 1, +} + +#[repr(C)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum tCANStsReg { + /// Read the full CAN controller status. + CAN_STS_CONTROL = 0, + + /// Mask of message objects with a transmit request set. + CAN_STS_TXREQUEST = 1, + + /// Mask of message objects with new data available. + CAN_STS_NEWDAT = 2, + + /// Mask of message objects that are enabled. + CAN_STS_MSGVAL = 3, +} + +#[repr(C)] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum tMsgObjType { + /// Transmit message object. + MSG_OBJ_TYPE_TX = 0, + + /// Transmit remote request message object. + MSG_OBJ_TYPE_TX_REMOTE = 1, + + /// Receive message object. + MSG_OBJ_TYPE_RX = 2, + + /// Receive remote request message object. + MSG_OBJ_TYPE_RX_REMOTE = 3, + + /// Remote frame receive with auto-transmit message object. + MSG_OBJ_TYPE_RXTX_REMOTE = 4, +} + +pub fn CANBitRateSetWrap(ui32Base: u32, ui32SourceClock: u32, ui32BitRate: u32) -> u32 { + return unsafe { CANBitRateSet(ui32Base, ui32SourceClock, ui32BitRate) }; +} + +pub fn CANDisableWrap(ui32Base: u32) { + unsafe { CANDisable(ui32Base) }; +} + +pub fn CANEnableWrap(ui32Base: u32) { + unsafe { CANEnable(ui32Base) }; +} + +pub fn CANErrCntrGetWrap(ui32Base: u32, pui32RxCount: *const u32, pui32TxCount: *const u32) -> bool { + return unsafe { CANErrCntrGet(ui32Base, pui32RxCount, pui32TxCount) }; +} + +pub fn CANInitWrap(ui32Base: u32) { + unsafe { CANInit(ui32Base) }; +} + +pub fn CANIntClearWrap(ui32Base: u32, ui32IntClr: u32) { + unsafe { CANIntClear(ui32Base, ui32IntClr) }; +} + +pub fn CANIntDisableWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { CANIntDisable(ui32Base, ui32IntFlags) }; +} + +pub fn CANIntEnableWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { CANIntEnable(ui32Base, ui32IntFlags) }; +} + +pub fn CANIntRegisterWrap(ui32Base:u32, pfnHandler: Option) { + unsafe { CANIntRegister(ui32Base, pfnHandler) }; +} + +pub fn CANIntUnregisterWrap(ui32Base: u32) { + unsafe { CANIntUnregister(ui32Base) }; +} + +pub fn CANMessageClearWrap(ui32Base: u32, ui32ObjID: u32) { + unsafe { CANMessageClear(ui32Base, ui32ObjID) }; +} + +pub fn CANRetryGetWrap(ui32Base: u32) -> bool { + return unsafe { CANRetryGet(ui32Base) }; +} + +pub fn CANRetrySetWrap(ui32Base: u32, bAutoRetry: bool) { + unsafe { CANRetrySet(ui32Base, bAutoRetry) }; +} + +pub fn CANBitTimingGetWrap(ui32Base: u32, psClkParms: *const tCANBitClkParms) { + unsafe { CANBitTimingGet(ui32Base, psClkParms) }; +} + +pub fn CANBitTimingSetWrap(ui32Base: u32, psClkParms: *const tCANBitClkParms) { + unsafe { CANBitTimingSet(ui32Base, psClkParms) }; +} + +pub fn CANIntStatusWrap(ui32Base: u32, eIntStsReg: tCANIntStsReg) -> u32 { + return unsafe { CANIntStatus(ui32Base, eIntStsReg) }; +} + +pub fn CANStatusGetWrap(ui32Base: u32, eStatusReg: tCANStsReg) -> u32 { + return unsafe { CANStatusGet(ui32Base, eStatusReg) }; +} + +pub fn CANMessageSetWrap( + base: u32, + obj_id: u32, + msg_object: &tCANMsgObject, + msg_type: tMsgObjType, +) { + unsafe { + CANMessageSet(base, obj_id, msg_object as *const _, msg_type) + } +} + +pub fn CANMessageGetWrap( + base: u32, + obj_id: u32, + msg_object: &tCANMsgObject, + clear_pending_int: bool, +) { + unsafe { + CANMessageGet(base, obj_id, msg_object as *const _, clear_pending_int) + } +} + +pub fn create_msg_object(ui32MsgID: u32, ui32MsgIDMask:u32,ui32Flags:u32,ui32MsgLen:u32, data: &[u8]) -> tCANMsgObject { + assert!(data.len() <= 8); + tCANMsgObject { + ui32MsgID: ui32MsgID, + ui32MsgIDMask: ui32MsgIDMask, + ui32Flags: ui32Flags, + ui32MsgLen: data.len() as u32, + pui8MsgData: data.as_ptr(), + } +} + +#[link(name = "can", kind = "static")] +extern "C" { + pub fn CANBitRateSet(ui32Base: u32, ui32SourceClock: u32, ui32BitRate: u32) -> u32; + pub fn CANDisable(ui32Base: u32); + pub fn CANEnable(ui32Base: u32); + pub fn CANErrCntrGet(ui32Base: u32, pui32RxCount: *const u32, pui32TxCount: *const u32) -> bool; + pub fn CANInit(ui32Base: u32); + pub fn CANIntClear(ui32Base: u32, ui32IntClr: u32); + pub fn CANIntDisable(ui32Base: u32, ui32IntFlags: u32); + pub fn CANIntEnable(ui32Base: u32, ui32IntFlags: u32); + pub fn CANIntRegister(ui32Base:u32, pfnHandler: Option); + pub fn CANIntUnregister(ui32Base: u32); + pub fn CANMessageClear(ui32Base: u32, ui32ObjID: u32); + pub fn CANRetryGet(ui32Base: u32) -> bool; + pub fn CANRetrySet(ui32Base: u32, bAutoRetry: bool); + pub fn CANBitTimingGet(ui32Base: u32, psClkParms: *const tCANBitClkParms); + pub fn CANBitTimingSet(ui32Base: u32, psClkParms: *const tCANBitClkParms); + pub fn CANIntStatus(ui32Base: u32, eIntStsReg: tCANIntStsReg) -> u32; + pub fn CANStatusGet(ui32Base:u32, eStatusReg:tCANStsReg)->u32; + + pub fn CANMessageGet( + ui32Base: u32, + ui32ObjID: u32, + psMsgObject: *const tCANMsgObject, + bClrPendingInt: bool, + ); + pub fn CANMessageSet( + ui32Base: u32, + ui32ObjID: u32, + psMsgObject: *const tCANMsgObject, + eMsgType: tMsgObjType, + ); +} \ No newline at end of file diff --git a/src/gpio.rs b/src/gpio.rs new file mode 100644 index 0000000..73bcad3 --- /dev/null +++ b/src/gpio.rs @@ -0,0 +1,250 @@ + +pub fn GPIODirModeSetWrap(ui32Port: u32, ui8Pins: u8, ui32PinIO: u32) { + unsafe { GPIODirModeSet(ui32Port, ui8Pins, ui32PinIO) }; +} + +pub fn GPIODirModeGetWrap(ui32Port: u32, ui8Pin: u8) -> u32 { + return unsafe { GPIODirModeGet(ui32Port, ui8Pin) }; +} + +pub fn GPIOIntTypeSetWrap(ui32Port: u32, ui8Pins: u8, ui32IntType: u32) { + unsafe { GPIOIntTypeSet(ui32Port, ui8Pins, ui32IntType) }; +} + +pub fn GPIOIntTypeGetWrap(ui32Port: u32, ui8Pin: u8) -> u32 { + return unsafe { GPIOIntTypeGet(ui32Port, ui8Pin) }; +} + +pub fn GPIOPadConfigSetWrap(ui32Port: u32, ui8Pins: u8, ui32Strength: u32, ui32PadType: u32) { + unsafe { GPIOPadConfigSet(ui32Port, ui8Pins, ui32Strength, ui32PadType) }; +} + +pub fn GPIOPadConfigGetWrap(ui32Port: u32, ui8Pin: u8, pui32Strength: *const u32, pui32PadType: *const u32) { + unsafe { GPIOPadConfigGet(ui32Port, ui8Pin, pui32Strength, pui32PadType) }; +} + +pub fn GPIOIntEnableWrap(ui32Port: u32, ui32IntFlags: u32) { + unsafe { GPIOIntEnable(ui32Port, ui32IntFlags) }; +} + +pub fn GPIOIntDisableWrap(ui32Port: u32, ui32IntFlags: u32) { + unsafe { GPIOIntDisable(ui32Port, ui32IntFlags) }; +} + +pub fn GPIOIntStatusWrap(ui32Port: u32, bMasked: bool) -> u32 { + return unsafe { GPIOIntStatus(ui32Port, bMasked) }; +} + +pub fn GPIOIntClearWrap(ui32Port: u32, ui32IntFlags: u32) { + unsafe { GPIOIntClear(ui32Port, ui32IntFlags) }; +} + +pub fn GPIOIntRegisterWrap(ui32Port: u32, pfnHandler: Option) { + unsafe { GPIOIntRegister(ui32Port, pfnHandler) }; +} + +pub fn GPIOIntUnregisterWrap(ui32Port: u32) { + unsafe { GPIOIntUnregister(ui32Port) }; +} + +pub fn GPIOIntRegisterPinWrap(ui32Port: u32, ui32Pin: u32, pfnHandler: Option) { + unsafe { GPIOIntRegisterPin(ui32Port, ui32Pin, pfnHandler) }; +} + +pub fn GPIOIntUnregisterPinWrap(ui32Port: u32, ui32Pin: u32) { + unsafe { GPIOIntUnregisterPin(ui32Port, ui32Pin) }; +} + +pub fn GPIOPinReadWrap(ui32Port: u32, ui8Pins: u8) -> i32 { + return unsafe { GPIOPinRead(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinWriteWrap(ui32Port: u32, ui8Pins: u8, ui8Val: u8) { + unsafe { GPIOPinWrite(ui32Port, ui8Pins, ui8Val) }; +} + +pub fn GPIOPinConfigureWrap(ui32PinConfig: u32) { + unsafe { GPIOPinConfigure(ui32PinConfig) }; +} + +pub fn GPIOPinTypeADCWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeADC(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeCANWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeCAN(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeComparatorWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeComparator(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeComparatorOutputWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeComparatorOutput(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeDIVSCLKWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeDIVSCLK(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeEPIWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeEPI(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeEthernetLEDWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeEthernetLED(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeEthernetMIIWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeEthernetMII(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeGPIOInputWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeGPIOInput(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeGPIOOutputWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeGPIOOutput(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeGPIOOutputODWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeGPIOOutputOD(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeHibernateRTCCLKWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeHibernateRTCCLK(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeI2CWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeI2C(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeI2CSCLWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeI2CSCL(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeLCDWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeLCD(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeOneWireWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeOneWire(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypePWMWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypePWM(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeQEIWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeQEI(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeSSIWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeSSI(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeTimerWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeTimer(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeTraceWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeTrace(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeUARTWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeUART(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeUSBAnalogWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeUSBAnalog(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeUSBDigitalWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeUSBDigital(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeWakeHighWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeWakeHigh(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinTypeWakeLowWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOPinTypeWakeLow(ui32Port, ui8Pins) }; +} + +pub fn GPIOPinWakeStatusWrap(ui32Port: u32) -> u32 { + return unsafe { GPIOPinWakeStatus(ui32Port) }; +} + +pub fn GPIODMATriggerEnableWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIODMATriggerEnable(ui32Port, ui8Pins) }; +} + +pub fn GPIODMATriggerDisableWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIODMATriggerDisable(ui32Port, ui8Pins) }; +} + +pub fn GPIOADCTriggerEnableWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOADCTriggerEnable(ui32Port, ui8Pins) }; +} + +pub fn GPIOADCTriggerDisableWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOADCTriggerDisable(ui32Port, ui8Pins) }; +} + +pub fn GPIOUnlockPinWrap(ui32Port: u32, ui8Pins: u8) { + unsafe { GPIOUnlockPin(ui32Port, ui8Pins) }; +} + + + #[link(name="gpio", kind="static")] + extern "C" { + pub fn GPIODirModeSet(ui32Port: u32, ui8Pins: u8, ui32PinIO: u32); + pub fn GPIODirModeGet(ui32Port: u32, ui8Pin: u8) -> u32; + pub fn GPIOIntTypeSet(ui32Port: u32, ui8Pins: u8, ui32IntType: u32); + pub fn GPIOIntTypeGet(ui32Port: u32, ui8Pin: u8) -> u32; + pub fn GPIOPadConfigSet(ui32Port: u32, ui8Pins: u8, ui32Strength: u32, ui32PadType: u32); + pub fn GPIOPadConfigGet(ui32Port: u32, ui8Pin: u8, pui32Strength: *const u32, pui32PadType: *const u32); + pub fn GPIOIntEnable(ui32Port: u32, ui32IntFlags: u32); + pub fn GPIOIntDisable(ui32Port: u32, ui32IntFlags: u32); + pub fn GPIOIntStatus(ui32Port: u32, bMasked: bool) -> u32; + pub fn GPIOIntClear(ui32Port: u32, ui32IntFlags: u32); + pub fn GPIOIntRegister(ui32Port: u32, pfnHandler: Option); + pub fn GPIOIntUnregister(ui32Port: u32); + pub fn GPIOIntRegisterPin(ui32Port: u32, ui32Pin: u32, pfnHandler: Option); + pub fn GPIOIntUnregisterPin(ui32Port: u32, ui32Pin: u32); + pub fn GPIOPinRead(ui32Port: u32, ui8Pins: u8) -> i32; + pub fn GPIOPinWrite(ui32Port: u32, ui8Pins: u8, ui8Val: u8); + pub fn GPIOPinConfigure(ui32PinConfig: u32); + pub fn GPIOPinTypeADC(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeCAN(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeComparator(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeComparatorOutput(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeDIVSCLK(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeEPI(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeEthernetLED(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeEthernetMII(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeGPIOInput(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeGPIOOutput(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeGPIOOutputOD(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeHibernateRTCCLK(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeI2C(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeI2CSCL(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeLCD(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeOneWire(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypePWM(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeQEI(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeSSI(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeTimer(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeTrace(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeUART(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeUSBAnalog(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeUSBDigital(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeWakeHigh(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinTypeWakeLow(ui32Port: u32, ui8Pins: u8); + pub fn GPIOPinWakeStatus(ui32Port: u32) -> u32; + pub fn GPIODMATriggerEnable(ui32Port: u32, ui8Pins: u8); + pub fn GPIODMATriggerDisable(ui32Port: u32, ui8Pins: u8); + pub fn GPIOADCTriggerEnable(ui32Port: u32, ui8Pins: u8); + pub fn GPIOADCTriggerDisable(ui32Port: u32, ui8Pins: u8); + pub fn GPIOUnlockPin(ui32Port: u32, ui8Pins: u8); + } diff --git a/src/i2c.rs b/src/i2c.rs new file mode 100644 index 0000000..2f698c0 --- /dev/null +++ b/src/i2c.rs @@ -0,0 +1,266 @@ + +pub fn I2CIntUnregisterWrap(ui32Base: u32) { + unsafe { I2CIntUnregister(ui32Base); } +} + +pub fn I2CTxFIFOConfigSetWrap(ui32Base: u32, ui32Config: u32) { + unsafe { I2CTxFIFOConfigSet(ui32Base, ui32Config); } +} + +pub fn I2CTxFIFOFlushWrap(ui32Base: u32) { + unsafe { I2CTxFIFOFlush(ui32Base); } +} + +pub fn I2CRxFIFOConfigSetWrap(ui32Base: u32, ui32Config: u32) { + unsafe { I2CRxFIFOConfigSet(ui32Base, ui32Config); } +} + +pub fn I2CRxFIFOFlushWrap(ui32Base: u32) { + unsafe { I2CRxFIFOFlush(ui32Base); } +} + +pub fn I2CFIFOStatusWrap(ui32Base: u32) -> u32 { + unsafe { I2CFIFOStatus(ui32Base) } +} + +pub fn I2CFIFODataPutWrap(ui32Base: u32, ui8Data: u8) { + unsafe { I2CFIFODataPut(ui32Base, ui8Data); } +} + +pub fn I2CFIFODataPutNonBlockingWrap(ui32Base: u32, ui8Data: u8) -> u32 { + unsafe { I2CFIFODataPutNonBlocking(ui32Base, ui8Data) } +} + +pub fn I2CFIFODataGetWrap(ui32Base: u32) -> u32 { + unsafe { I2CFIFODataGet(ui32Base) } +} + +pub fn I2CFIFODataGetNonBlockingWrap(ui32Base: u32, pui8Data: *const u8) -> u32 { + unsafe { I2CFIFODataGetNonBlocking(ui32Base, pui8Data) } +} + +pub fn I2CMasterBurstLengthSetWrap(ui32Base: u32, ui8Length: u8) { + unsafe { I2CMasterBurstLengthSet(ui32Base, ui8Length); } +} + +pub fn I2CMasterBurstCountGetWrap(ui32Base: u32) -> u32 { + unsafe { I2CMasterBurstCountGet(ui32Base) } +} + +pub fn I2CMasterGlitchFilterConfigSetWrap(ui32Base: u32, ui32Config: u32) { + unsafe { I2CMasterGlitchFilterConfigSet(ui32Base, ui32Config); } +} + +pub fn I2CSlaveFIFOEnableWrap(ui32Base: u32, ui32Config: u32) { + unsafe { I2CSlaveFIFOEnable(ui32Base, ui32Config); } +} + +pub fn I2CSlaveFIFODisableWrap(ui32Base: u32) { + unsafe { I2CSlaveFIFODisable(ui32Base); } +} + +pub fn I2CMasterBusBusyWrap(ui32Base: u32) -> bool { + unsafe { I2CMasterBusBusy(ui32Base) } +} + +pub fn I2CMasterBusyWrap(ui32Base: u32) -> bool { + unsafe { I2CMasterBusy(ui32Base) } +} + +pub fn I2CMasterControlWrap(ui32Base: u32, ui32Cmd: u32) { + unsafe { I2CMasterControl(ui32Base, ui32Cmd); } +} + +pub fn I2CMasterDataGetWrap(ui32Base: u32) -> u32 { + unsafe { I2CMasterDataGet(ui32Base) } +} + +pub fn I2CMasterDataPutWrap(ui32Base: u32, ui8Data: u8) { + unsafe { I2CMasterDataPut(ui32Base, ui8Data); } +} + +pub fn I2CMasterDisableWrap(ui32Base: u32) { + unsafe { I2CMasterDisable(ui32Base); } +} + +pub fn I2CMasterEnableWrap(ui32Base: u32) { + unsafe { I2CMasterEnable(ui32Base); } +} + +pub fn I2CMasterErrWrap(ui32Base: u32) -> u32 { + unsafe { I2CMasterErr(ui32Base) } +} + +pub fn I2CMasterInitExpClkWrap(ui32Base: u32, ui32I2CClk: u32, bFast: bool) { + unsafe { I2CMasterInitExpClk(ui32Base, ui32I2CClk, bFast); } +} + +pub fn I2CMasterIntClearWrap(ui32Base: u32) { + unsafe { I2CMasterIntClear(ui32Base); } +} + +pub fn I2CMasterIntDisableWrap(ui32Base: u32) { + unsafe { I2CMasterIntDisable(ui32Base); } +} + +pub fn I2CMasterIntEnableWrap(ui32Base: u32) { + unsafe { I2CMasterIntEnable(ui32Base); } +} + +pub fn I2CMasterIntStatusWrap(ui32Base: u32, bMasked: bool) -> bool { + unsafe { I2CMasterIntStatus(ui32Base, bMasked) } +} + +pub fn I2CMasterIntEnableExWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { I2CMasterIntEnableEx(ui32Base, ui32IntFlags); } +} + +pub fn I2CMasterIntDisableExWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { I2CMasterIntDisableEx(ui32Base, ui32IntFlags); } +} + +pub fn I2CMasterIntStatusExWrap(ui32Base: u32, bMasked: bool) -> u32 { + unsafe { I2CMasterIntStatusEx(ui32Base, bMasked) } +} + +pub fn I2CMasterIntClearExWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { I2CMasterIntClearEx(ui32Base, ui32IntFlags); } +} + +pub fn I2CMasterTimeoutSetWrap(ui32Base: u32, ui32Value: u32) { + unsafe { I2CMasterTimeoutSet(ui32Base, ui32Value); } +} + +pub fn I2CSlaveACKOverrideWrap(ui32Base: u32, bEnable: bool) { + unsafe { I2CSlaveACKOverride(ui32Base, bEnable); } +} + +pub fn I2CSlaveACKValueSetWrap(ui32Base: u32, bACK: bool) { + unsafe { I2CSlaveACKValueSet(ui32Base, bACK); } +} + +pub fn I2CMasterLineStateGetWrap(ui32Base: u32) -> u32 { + unsafe { I2CMasterLineStateGet(ui32Base) } +} + +pub fn I2CSlaveDataGetWrap(ui32Base: u32) -> u32 { + unsafe { I2CSlaveDataGet(ui32Base) } +} + +pub fn I2CSlaveDataPutWrap(ui32Base: u32, ui8Data: u8) { + unsafe { I2CSlaveDataPut(ui32Base, ui8Data); } +} + +pub fn I2CSlaveDisableWrap(ui32Base: u32) { + unsafe { I2CSlaveDisable(ui32Base); } +} + +pub fn I2CSlaveEnableWrap(ui32Base: u32) { + unsafe { I2CSlaveEnable(ui32Base); } +} + +pub fn I2CSlaveInitWrap(ui32Base: u32, ui8SlaveAddr: u8) { + unsafe { I2CSlaveInit(ui32Base, ui8SlaveAddr); } +} + +pub fn I2CSlaveAddressSetWrap(ui32Base: u32, ui8AddrNum: u8, ui8SlaveAddr: u8) { + unsafe { I2CSlaveAddressSet(ui32Base, ui8AddrNum, ui8SlaveAddr); } +} + +pub fn I2CSlaveIntClearWrap(ui32Base: u32) { + unsafe { I2CSlaveIntClear(ui32Base); } +} + +pub fn I2CSlaveIntDisableWrap(ui32Base: u32) { + unsafe { I2CSlaveIntDisable(ui32Base); } +} + +pub fn I2CSlaveIntEnableWrap(ui32Base: u32) { + unsafe { I2CSlaveIntEnable(ui32Base); } +} + +pub fn I2CSlaveIntClearExWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { I2CSlaveIntClearEx(ui32Base, ui32IntFlags); } +} + +pub fn I2CSlaveIntDisableExWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { I2CSlaveIntDisableEx(ui32Base, ui32IntFlags); } +} + +pub fn I2CSlaveIntEnableExWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { I2CSlaveIntEnableEx(ui32Base, ui32IntFlags); } +} + +pub fn I2CSlaveIntStatusWrap(ui32Base: u32, bMasked: bool) -> bool { + unsafe { I2CSlaveIntStatus(ui32Base, bMasked) } +} + +pub fn I2CSlaveIntStatusExWrap(ui32Base: u32, bMasked: bool) -> u32 { + unsafe { I2CSlaveIntStatusEx(ui32Base, bMasked) } +} + +pub fn I2CSlaveStatusWrap(ui32Base: u32) -> u32 { + unsafe { I2CSlaveStatus(ui32Base) } +} + +pub fn I2CLoopbackEnableWrap(ui32Base: u32) { + unsafe { I2CLoopbackEnable(ui32Base); } +} + + +#[link(name="i2c", kind="static")] +extern "C" { + pub fn I2CIntRegister(ui32Base: u32, pfnHandler: Option); + pub fn I2CIntUnregister(ui32Base: u32); + pub fn I2CTxFIFOConfigSet(ui32Base: u32, ui32Config: u32); + pub fn I2CTxFIFOFlush(ui32Base: u32); + pub fn I2CRxFIFOConfigSet(ui32Base: u32, ui32Config: u32); + pub fn I2CRxFIFOFlush(ui32Base: u32); + pub fn I2CFIFOStatus(ui32Base: u32) -> u32; + pub fn I2CFIFODataPut(ui32Base: u32, ui8Data: u8); + pub fn I2CFIFODataPutNonBlocking(ui32Base: u32, ui8Data: u8) -> u32; + pub fn I2CFIFODataGet(ui32Base: u32) -> u32; + pub fn I2CFIFODataGetNonBlocking(ui32Base: u32, pui8Data: *const u8) -> u32; + pub fn I2CMasterBurstLengthSet(ui32Base: u32, ui8Length: u8); + pub fn I2CMasterBurstCountGet(ui32Base: u32) -> u32; + pub fn I2CMasterGlitchFilterConfigSet(ui32Base: u32, ui32Config: u32); + pub fn I2CSlaveFIFOEnable(ui32Base: u32, ui32Config: u32); + pub fn I2CSlaveFIFODisable(ui32Base: u32); + pub fn I2CMasterBusBusy(ui32Base: u32) -> bool; + pub fn I2CMasterBusy(ui32Base: u32) -> bool; + pub fn I2CMasterControl(ui32Base: u32, ui32Cmd: u32); + pub fn I2CMasterDataGet(ui32Base: u32) -> u32; + pub fn I2CMasterDataPut(ui32Base: u32, ui8Data: u8); + pub fn I2CMasterDisable(ui32Base: u32); + pub fn I2CMasterEnable(ui32Base: u32); + pub fn I2CMasterErr(ui32Base: u32) -> u32; + pub fn I2CMasterInitExpClk(ui32Base: u32, ui32I2CClk: u32, bFast: bool); + pub fn I2CMasterIntClear(ui32Base: u32); + pub fn I2CMasterIntDisable(ui32Base: u32); + pub fn I2CMasterIntEnable(ui32Base: u32); + pub fn I2CMasterIntStatus(ui32Base: u32, bMasked: bool) -> bool; + pub fn I2CMasterIntEnableEx(ui32Base: u32, ui32IntFlags: u32); + pub fn I2CMasterIntDisableEx(ui32Base: u32, ui32IntFlags: u32); + pub fn I2CMasterIntStatusEx(ui32Base: u32, bMasked: bool) -> u32; + pub fn I2CMasterIntClearEx(ui32Base: u32, ui32IntFlags: u32); + pub fn I2CMasterTimeoutSet(ui32Base: u32, ui32Value: u32); + pub fn I2CSlaveACKOverride(ui32Base: u32, bEnable: bool); + pub fn I2CSlaveACKValueSet(ui32Base: u32, bACK: bool); + pub fn I2CMasterLineStateGet(ui32Base: u32) -> u32; + pub fn I2CSlaveDataGet(ui32Base: u32) -> u32; + pub fn I2CSlaveDataPut(ui32Base: u32, ui8Data: u8); + pub fn I2CSlaveDisable(ui32Base: u32); + pub fn I2CSlaveEnable(ui32Base: u32); + pub fn I2CSlaveInit(ui32Base: u32, ui8SlaveAddr: u8); + pub fn I2CSlaveAddressSet(ui32Base: u32, ui8AddrNum: u8, ui8SlaveAddr: u8); + pub fn I2CSlaveIntClear(ui32Base: u32); + pub fn I2CSlaveIntDisable(ui32Base: u32); + pub fn I2CSlaveIntEnable(ui32Base: u32); + pub fn I2CSlaveIntClearEx(ui32Base: u32, ui32IntFlags: u32); + pub fn I2CSlaveIntDisableEx(ui32Base: u32, ui32IntFlags: u32); + pub fn I2CSlaveIntEnableEx(ui32Base: u32, ui32IntFlags: u32); + pub fn I2CSlaveIntStatus(ui32Base: u32, bMasked: bool) -> bool; + pub fn I2CSlaveIntStatusEx(ui32Base: u32, bMasked: bool) -> u32; + pub fn I2CSlaveStatus(ui32Base: u32) -> u32; + pub fn I2CLoopbackEnable(ui32Base: u32); +} \ No newline at end of file diff --git a/src/int.rs b/src/int.rs new file mode 100644 index 0000000..ecc7e80 --- /dev/null +++ b/src/int.rs @@ -0,0 +1,74 @@ + +pub fn IntMasterEnableWrap() -> bool { + return unsafe { IntMasterEnable() }; +} + +pub fn IntMasterDisableWrap() -> bool { + return unsafe { IntMasterDisable() }; +} + +pub fn IntPriorityGroupingSetWrap(ui32Bits: u32) { + unsafe { IntPriorityGroupingSet(ui32Bits) }; +} + +pub fn IntPriorityGroupingGetWrap() -> u32 { + return unsafe { IntPriorityGroupingGet() }; +} + +pub fn IntPrioritySetWrap(ui32Interrupt: u32, ui8Priority: u8) { + unsafe { IntPrioritySet(ui32Interrupt, ui8Priority) }; +} + +pub fn IntPriorityGetWrap(ui32Interrupt: u32) -> i32 { + return unsafe { IntPriorityGet(ui32Interrupt) }; +} + +pub fn IntEnableWrap(ui32Interrupt: u32) { + unsafe { IntEnable(ui32Interrupt) }; +} + +pub fn IntDisableWrap(ui32Interrupt: u32) { + unsafe { IntDisable(ui32Interrupt) }; +} + +pub fn IntIsEnabledWrap(ui32Interrupt: u32) -> u32 { + return unsafe { IntIsEnabled(ui32Interrupt) }; +} + +pub fn IntPendSetWrap(ui32Interrupt: u32) { + unsafe { IntPendSet(ui32Interrupt) }; +} + +pub fn IntPendClearWrap(ui32Interrupt: u32) { + unsafe { IntPendClear(ui32Interrupt) }; +} + +pub fn IntPriorityMaskSetWrap(ui32PriorityMask: u32) { + unsafe { IntPriorityMaskSet(ui32PriorityMask) }; +} + +pub fn IntPriorityMaskGetWrap() -> u32 { + return unsafe { IntPriorityMaskGet() }; +} + +pub fn IntTriggerWrap(ui32Interrupt: u32) { + unsafe { IntTrigger(ui32Interrupt) }; +} + +#[link(name="interrupt", kind="static")] +extern "C" { + pub fn IntMasterEnable() -> bool; + pub fn IntMasterDisable() -> bool; + pub fn IntPriorityGroupingSet(ui32Bits: u32); + pub fn IntPriorityGroupingGet() -> u32; + pub fn IntPrioritySet(ui32Interrupt: u32, ui8Priority: u8); + pub fn IntPriorityGet(ui32Interrupt: u32) -> i32; + pub fn IntEnable(ui32Interrupt: u32); + pub fn IntDisable(ui32Interrupt: u32); + pub fn IntIsEnabled(ui32Interrupt: u32) -> u32; + pub fn IntPendSet(ui32Interrupt: u32); + pub fn IntPendClear(ui32Interrupt: u32); + pub fn IntPriorityMaskSet(ui32PriorityMask: u32); + pub fn IntPriorityMaskGet() -> u32; + pub fn IntTrigger(ui32Interrupt: u32); +} diff --git a/src/main.rs b/src/main.rs new file mode 100644 index 0000000..b311316 --- /dev/null +++ b/src/main.rs @@ -0,0 +1,149 @@ +#![no_std] +#![no_main] +#![allow(dead_code)] // this will supress all dead codes including unused constants +#![allow(unused_variables)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(unused_mut)] +#![allow(non_upper_case_globals)] +#![allow(unused_assignments)] +extern crate tm4c123x; +use cortex_m_rt::{entry}; +use cortex_m_rt::exception; +use cortex_m_rt::ExceptionFrame; +use cortex_m; +use core::arch::asm; +use tm4c123x::interrupt; +use panic_halt as _; + +use cortex_m::interrupt::Mutex; +use core::cell::RefCell; + +mod sysctl; +mod tm123; +mod timer; +mod int; +mod gpio; +use crate::sysctl::*; +use crate::tm123::*; +use crate::timer::*; +use crate::int::*; +use crate::gpio::*; + +const RED_LED:u8 = GPIO_PIN_1; +const BLUE_LED:u8 = GPIO_PIN_2; +const GREEN_LED:u8 = GPIO_PIN_3; + +// Global counter wrapped in a Mutex and RefCell +static COUNTER: Mutex> = Mutex::new(RefCell::new(0)); + +/// Custom HardFault handler +#[exception] +unsafe fn HardFault(ef: &ExceptionFrame) -> ! { + // You can log or debug the exception frame + loop{} +} + +/// Delay function (simple busy-wait), each loop takes around 14-15 clock cycles +#[inline(always)] +pub fn SysCtlDelay(mut cycles: u32) { + unsafe { + while cycles > 0 { + asm!( + "nop", + "nop", + "nop", + options(nostack, nomem) + ); + cycles -= 1; + } + } +} + +#[entry] +fn main() -> ! { + // + // Setup the system clock to run at 50 Mhz from PLL with crystal reference + // + SysCtlClockSetWrap(SYSCTL_SYSDIV_4|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ| + SYSCTL_OSC_MAIN); + + // + // Enable the GPIO port that is used for the on-board LED. + // + SysCtlPeripheralEnableWrap(SYSCTL_PERIPH_GPIOF); + + // + // Check if the peripheral access is enabled. + // + while !SysCtlPeripheralReadyWrap(SYSCTL_PERIPH_GPIOF) + { + } + + // + // Enable the GPIO pin for the LED (PF3). Set the direction as output, and + // enable the GPIO pin for digital function. + // + GPIOPinTypeGPIOOutputWrap(GPIO_PORTF_BASE, RED_LED|BLUE_LED); + + // turn off RED_LED and BLUE_LED when power off + GPIOPinWriteWrap(GPIO_PORTF_BASE, RED_LED|BLUE_LED, 0); + + // + // Enable the peripherals used by this example. + // + SysCtlPeripheralEnableWrap(SYSCTL_PERIPH_TIMER0); + + + // + // Configure the two 32-bit periodic timers. + // + + TimerConfigureWrap(TIMER0_BASE, TIMER_CFG_PERIODIC); + TimerLoadSetWrap(TIMER0_BASE, TIMER_A, 1_000_000); // every 20 ms interrupt + // + // Setup the interrupts for the timer timeouts. + // + + TimerIntEnableWrap(TIMER0_BASE, TIMER_TIMA_TIMEOUT); // TIMER0 A enable interrupt + + // + // Enable the timers. + // + TimerEnableWrap(TIMER0_BASE, TIMER_A); // enable timer0 + + + IntEnableWrap(0x23); // NVIC enable TIMER0A + // + // Enable processor interrupts. + // + unsafe{cortex_m::interrupt::enable();} // enable global interrupt on MCU PRIMSK register https://docs.rs/cortex-m/0.7.7/cortex_m/interrupt/fn.enable.html + + loop { + // Read the counter safely + let current_count = cortex_m::interrupt::free(|cs| { + *COUNTER.borrow(cs).borrow() + }); + + if current_count==2 { + cortex_m::interrupt::free(|cs| *COUNTER.borrow(cs).borrow_mut() = 0); + // Perform the required action + GPIOPinWriteWrap(GPIO_PORTF_BASE, BLUE_LED, (GPIOPinReadWrap(GPIO_PORTF_BASE,BLUE_LED) as u8)^ BLUE_LED); + } + } +} + +#[interrupt] +fn TIMER0A() { + static mut TICKS: u32 = 0; + *TICKS += 1; // Increment system tick count + TimerIntClearWrap(TIMER0_BASE, TIMER_TIMA_TIMEOUT); + if *TICKS>=25{ + *TICKS=0; + // Set the SECONDS_FLAG + cortex_m::interrupt::free(|cs| { + let mut counter = COUNTER.borrow(cs).borrow_mut(); + *counter += 1; + }); + } +} diff --git a/src/ssi.rs b/src/ssi.rs new file mode 100644 index 0000000..e6d4613 --- /dev/null +++ b/src/ssi.rs @@ -0,0 +1,121 @@ + +pub fn SSIDataGetWrap(ui32Base: u32, pui32Data: *const u32) { + unsafe { SSIDataGet(ui32Base, pui32Data); } +} + +pub fn SSIDataGetNonBlockingWrap(ui32Base: u32, pui32Data: *const u32) -> i32 { + unsafe { SSIDataGetNonBlocking(ui32Base, pui32Data) } +} + +pub fn SSIDataPutWrap(ui32Base: u32, ui32Data: u32) { + unsafe { SSIDataPut(ui32Base, ui32Data); } +} + +pub fn SSIDataPutNonBlockingWrap(ui32Base: u32, ui32Data: u32) -> i32 { + unsafe { SSIDataPutNonBlocking(ui32Base, ui32Data) } +} + +pub fn SSIDisableWrap(ui32Base: u32) { + unsafe { SSIDisable(ui32Base); } +} + +pub fn SSIEnableWrap(ui32Base: u32) { + unsafe { SSIEnable(ui32Base); } +} + +pub fn SSIIntClearWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { SSIIntClear(ui32Base, ui32IntFlags); } +} + +pub fn SSIIntDisableWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { SSIIntDisable(ui32Base, ui32IntFlags); } +} + +pub fn SSIIntEnableWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { SSIIntEnable(ui32Base, ui32IntFlags); } +} + +pub fn SSIIntStatusWrap(ui32Base: u32, bMasked: bool) -> u32 { + unsafe { SSIIntStatus(ui32Base, bMasked) } +} + +pub fn SSIIntUnregisterWrap(ui32Base: u32) { + unsafe { SSIIntUnregister(ui32Base); } +} + +pub fn SSIDMAEnableWrap(ui32Base: u32, ui32DMAFlags: u32) { + unsafe { SSIDMAEnable(ui32Base, ui32DMAFlags); } +} + +pub fn SSIDMADisableWrap(ui32Base: u32, ui32DMAFlags: u32) { + unsafe { SSIDMADisable(ui32Base, ui32DMAFlags); } +} + +pub fn SSIBusyWrap(ui32Base: u32) -> bool { + unsafe { SSIBusy(ui32Base) } +} + +pub fn SSIClockSourceSetWrap(ui32Base: u32, ui32Source: u32) { + unsafe { SSIClockSourceSet(ui32Base, ui32Source); } +} + +pub fn SSIClockSourceGetWrap(ui32Base: u32) -> u32 { + unsafe { SSIClockSourceGet(ui32Base) } +} + +pub fn SSIAdvModeSetWrap(ui32Base: u32, ui32Mode: u32) { + unsafe { SSIAdvModeSet(ui32Base, ui32Mode); } +} + +pub fn SSIAdvDataPutFrameEndWrap(ui32Base: u32, ui32Data: u32) { + unsafe { SSIAdvDataPutFrameEnd(ui32Base, ui32Data); } +} + +pub fn SSIAdvDataPutFrameEndNonBlockingWrap(ui32Base: u32, ui32Data: u32) -> i32 { + unsafe { SSIAdvDataPutFrameEndNonBlocking(ui32Base, ui32Data) } +} + +pub fn SSIAdvFrameHoldEnableWrap(ui32Base: u32) { + unsafe { SSIAdvFrameHoldEnable(ui32Base); } +} + +pub fn SSIAdvFrameHoldDisableWrap(ui32Base: u32) { + unsafe { SSIAdvFrameHoldDisable(ui32Base); } +} + +pub fn SSILoopbackEnableWrap(ui32Base: u32) { + unsafe { SSILoopbackEnable(ui32Base); } +} + +pub fn SSILoopbackDisableWrap(ui32Base: u32) { + unsafe { SSILoopbackDisable(ui32Base); } +} + + +#[link(name="ssi", kind="static")] +extern "C" { + pub fn SSIDataGet(ui32Base: u32, pui32Data: *const u32); + pub fn SSIDataGetNonBlocking(ui32Base: u32, pui32Data: *const u32) -> i32; + pub fn SSIDataPut(ui32Base: u32, ui32Data: u32); + pub fn SSIDataPutNonBlocking(ui32Base: u32, ui32Data: u32) -> i32; + pub fn SSIDisable(ui32Base: u32); + pub fn SSIEnable(ui32Base: u32); + pub fn SSIIntClear(ui32Base: u32, ui32IntFlags: u32); + pub fn SSIIntDisable(ui32Base: u32, ui32IntFlags: u32); + pub fn SSIIntEnable(ui32Base: u32, ui32IntFlags: u32); + pub fn SSIIntRegister(ui32Base: u32, pfnHandler: Option ); + pub fn SSIIntStatus(ui32Base: u32, bMasked: bool) -> u32; + pub fn SSIIntUnregister(ui32Base: u32); + pub fn SSIDMAEnable(ui32Base: u32, ui32DMAFlags: u32); + pub fn SSIDMADisable(ui32Base: u32, ui32DMAFlags: u32); + pub fn SSIBusy(ui32Base: u32) -> bool; + pub fn SSIClockSourceSet(ui32Base: u32, ui32Source: u32); + pub fn SSIClockSourceGet(ui32Base: u32) -> u32; + pub fn SSIAdvModeSet(ui32Base: u32, ui32Mode: u32); + pub fn SSIAdvDataPutFrameEnd(ui32Base: u32, ui32Data: u32); + pub fn SSIAdvDataPutFrameEndNonBlocking(ui32Base: u32, ui32Data: u32) -> i32; + pub fn SSIAdvFrameHoldEnable(ui32Base: u32); + pub fn SSIAdvFrameHoldDisable(ui32Base: u32); + pub fn SSILoopbackEnable(ui32Base: u32); + pub fn SSILoopbackDisable(ui32Base: u32); +} \ No newline at end of file diff --git a/src/sysctl.rs b/src/sysctl.rs new file mode 100644 index 0000000..42bfc21 --- /dev/null +++ b/src/sysctl.rs @@ -0,0 +1,310 @@ + +pub fn SysCtlSRAMSizeGetWrap() -> u32 { + return unsafe { SysCtlSRAMSizeGet() }; +} + +pub fn SysCtlFlashSizeGetWrap() -> u32 { + return unsafe { SysCtlFlashSizeGet() }; +} + +pub fn SysCtlFlashSectorSizeGetWrap() -> u32 { + return unsafe { SysCtlFlashSectorSizeGet() }; +} + +pub fn SysCtlPeripheralPresentWrap(ui32Peripheral: u32) -> bool { + return unsafe { SysCtlPeripheralPresent(ui32Peripheral) }; +} + +pub fn SysCtlPeripheralReadyWrap(ui32Peripheral: u32) -> bool { + return unsafe { SysCtlPeripheralReady(ui32Peripheral) }; +} + +pub fn SysCtlPeripheralPowerOnWrap(ui32Peripheral: u32) { + unsafe { SysCtlPeripheralPowerOn(ui32Peripheral) }; +} + +pub fn SysCtlPeripheralPowerOffWrap(ui32Peripheral: u32) { + unsafe { SysCtlPeripheralPowerOff(ui32Peripheral) }; +} + +pub fn SysCtlPeripheralResetWrap(ui32Peripheral: u32) { + unsafe { SysCtlPeripheralReset(ui32Peripheral) }; +} + +pub fn SysCtlPeripheralEnableWrap(ui32Peripheral: u32) { + unsafe { SysCtlPeripheralEnable(ui32Peripheral) }; +} + +pub fn SysCtlPeripheralDisableWrap(ui32Peripheral: u32) { + unsafe { SysCtlPeripheralDisable(ui32Peripheral) }; +} + +pub fn SysCtlPeripheralSleepEnableWrap(ui32Peripheral: u32) { + unsafe { SysCtlPeripheralSleepEnable(ui32Peripheral) }; +} + +pub fn SysCtlPeripheralSleepDisableWrap(ui32Peripheral: u32) { + unsafe { SysCtlPeripheralSleepDisable(ui32Peripheral) }; +} + +pub fn SysCtlPeripheralDeepSleepEnableWrap(ui32Peripheral: u32) { + unsafe { SysCtlPeripheralDeepSleepEnable(ui32Peripheral) }; +} + +pub fn SysCtlPeripheralDeepSleepDisableWrap(ui32Peripheral: u32) { + unsafe { SysCtlPeripheralDeepSleepDisable(ui32Peripheral) }; +} + +pub fn SysCtlPeripheralClockGatingWrap(bEnable: bool) { + unsafe { SysCtlPeripheralClockGating(bEnable) }; +} + +pub fn SysCtlIntRegisterWrap(pfnHandler: Option ) { + unsafe { SysCtlIntRegister(pfnHandler) }; +} + +pub fn SysCtlIntUnregisterWrap() { + unsafe { SysCtlIntUnregister() }; +} + +pub fn SysCtlIntEnableWrap(ui32Ints: u32) { + unsafe { SysCtlIntEnable(ui32Ints) }; +} + +pub fn SysCtlIntDisableWrap(ui32Ints: u32) { + unsafe { SysCtlIntDisable(ui32Ints) }; +} + +pub fn SysCtlIntClearWrap(ui32Ints: u32) { + unsafe { SysCtlIntClear(ui32Ints) }; +} + +pub fn SysCtlIntStatusWrap(bMasked: bool) -> u32 { + return unsafe { SysCtlIntStatus(bMasked) }; +} + +pub fn SysCtlLDOSleepSetWrap(ui32Voltage: u32) { + unsafe { SysCtlLDOSleepSet(ui32Voltage) }; +} + +pub fn SysCtlLDOSleepGetWrap() -> u32 { + return unsafe { SysCtlLDOSleepGet() }; +} + +pub fn SysCtlLDODeepSleepSetWrap(ui32Voltage: u32) { + unsafe { SysCtlLDODeepSleepSet(ui32Voltage) }; +} + +pub fn SysCtlLDODeepSleepGetWrap() -> u32 { + return unsafe { SysCtlLDODeepSleepGet() }; +} + +pub fn SysCtlSleepPowerSetWrap(ui32Config: u32) { + unsafe { SysCtlSleepPowerSet(ui32Config) }; +} + +pub fn SysCtlDeepSleepPowerSetWrap(ui32Config: u32) { + unsafe { SysCtlDeepSleepPowerSet(ui32Config) }; +} + +pub fn SysCtlResetWrap() { + unsafe { SysCtlReset() }; +} + +pub fn SysCtlSleepWrap() { + unsafe { SysCtlSleep() }; +} + +pub fn SysCtlDeepSleepWrap() { + unsafe { SysCtlDeepSleep() }; +} + +pub fn SysCtlResetCauseGetWrap() -> u32 { + return unsafe { SysCtlResetCauseGet() }; +} + +pub fn SysCtlResetCauseClearWrap(ui32Causes: u32) { + unsafe { SysCtlResetCauseClear(ui32Causes) }; +} + +pub fn SysCtlBrownOutConfigSetWrap(ui32Config: u32, ui32Delay: u32) { + unsafe { SysCtlBrownOutConfigSet(ui32Config, ui32Delay) }; +} + +pub fn SysCtlDelayWrap(ui32Count: u32) { + unsafe { SysCtlDelay(ui32Count) }; +} + +pub fn SysCtlMOSCConfigSetWrap(ui32Config: u32) { + unsafe { SysCtlMOSCConfigSet(ui32Config) }; +} + +pub fn SysCtlPIOSCCalibrateWrap(ui32Type: u32) -> u32 { + return unsafe { SysCtlPIOSCCalibrate(ui32Type) }; +} + +pub fn SysCtlClockSetWrap(ui32Config: u32) { + unsafe { SysCtlClockSet(ui32Config) }; +} + +pub fn SysCtlClockGetWrap() -> u32 { + return unsafe { SysCtlClockGet() }; +} + +pub fn SysCtlDeepSleepClockSetWrap(ui32Config: u32) { + unsafe { SysCtlDeepSleepClockSet(ui32Config) }; +} + +pub fn SysCtlDeepSleepClockConfigSetWrap(ui32Div: u32, ui32Config: u32) { + unsafe { SysCtlDeepSleepClockConfigSet(ui32Div, ui32Config) }; +} + +pub fn SysCtlPWMClockSetWrap(ui32Config: u32) { + unsafe { SysCtlPWMClockSet(ui32Config) }; +} + +pub fn SysCtlPWMClockGetWrap() -> u32 { + return unsafe { SysCtlPWMClockGet() }; +} + +pub fn SysCtlIOSCVerificationSetWrap(bEnable: bool) { + unsafe { SysCtlIOSCVerificationSet(bEnable) }; +} + +pub fn SysCtlMOSCVerificationSetWrap(bEnable: bool) { + unsafe { SysCtlMOSCVerificationSet(bEnable) }; +} + +pub fn SysCtlPLLVerificationSetWrap(bEnable: bool) { + unsafe { SysCtlPLLVerificationSet(bEnable) }; +} + +pub fn SysCtlClkVerificationClearWrap() { + unsafe { SysCtlClkVerificationClear() }; +} + +pub fn SysCtlGPIOAHBEnableWrap(ui32GPIOPeripheral: u32) { + unsafe { SysCtlGPIOAHBEnable(ui32GPIOPeripheral) }; +} + +pub fn SysCtlGPIOAHBDisableWrap(ui32GPIOPeripheral: u32) { + unsafe { SysCtlGPIOAHBDisable(ui32GPIOPeripheral) }; +} + +pub fn SysCtlUSBPLLEnableWrap() { + unsafe { SysCtlUSBPLLEnable() }; +} + +pub fn SysCtlUSBPLLDisableWrap() { + unsafe { SysCtlUSBPLLDisable() }; +} + +pub fn SysCtlClockFreqSetWrap(ui32Config: u32, ui32SysClock: u32) -> u32 { + return unsafe { SysCtlClockFreqSet(ui32Config, ui32SysClock) }; +} + +pub fn SysCtlResetBehaviorSetWrap(ui32Behavior: u32) { + unsafe { SysCtlResetBehaviorSet(ui32Behavior) }; +} + +pub fn SysCtlResetBehaviorGetWrap() -> u32 { + return unsafe { SysCtlResetBehaviorGet() }; +} + +pub fn SysCtlClockOutConfigWrap(ui32Config: u32, ui32Div: u32) { + unsafe { SysCtlClockOutConfig(ui32Config, ui32Div) }; +} + +pub fn SysCtlAltClkConfigWrap(ui32Config: u32) { + unsafe { SysCtlAltClkConfig(ui32Config) }; +} + +pub fn SysCtlNMIStatusWrap() -> u32 { + return unsafe { SysCtlNMIStatus() }; +} + +pub fn SysCtlNMIClearWrap(ui32Status: u32) { + unsafe { SysCtlNMIClear(ui32Status) }; +} + +pub fn SysCtlVoltageEventConfigWrap(ui32Config: u32) { + unsafe { SysCtlVoltageEventConfig(ui32Config) }; +} + +pub fn SysCtlVoltageEventStatusWrap() -> u32 { + return unsafe { SysCtlVoltageEventStatus() }; +} + +pub fn SysCtlVoltageEventClearWrap(ui32Status: u32) { + unsafe { SysCtlVoltageEventClear(ui32Status) }; +} + +pub fn SysCtlVCOGetWrap(ui32Crystal: u32, pui32VCOFrequency: *const u32) -> bool { + return unsafe { SysCtlVCOGet(ui32Crystal, pui32VCOFrequency) }; +} + + +#[link(name="sysctl", kind="static")] +extern "C" { + pub fn SysCtlSRAMSizeGet() -> u32; + pub fn SysCtlFlashSizeGet() -> u32; + pub fn SysCtlFlashSectorSizeGet() -> u32; + pub fn SysCtlPeripheralPresent(ui32Peripheral: u32) -> bool; + pub fn SysCtlPeripheralReady(ui32Peripheral: u32) -> bool; + pub fn SysCtlPeripheralPowerOn(ui32Peripheral: u32); + pub fn SysCtlPeripheralPowerOff(ui32Peripheral: u32); + pub fn SysCtlPeripheralReset(ui32Peripheral: u32); + pub fn SysCtlPeripheralEnable(ui32Peripheral: u32); + pub fn SysCtlPeripheralDisable(ui32Peripheral: u32); + pub fn SysCtlPeripheralSleepEnable(ui32Peripheral: u32); + pub fn SysCtlPeripheralSleepDisable(ui32Peripheral: u32); + pub fn SysCtlPeripheralDeepSleepEnable(ui32Peripheral: u32); + pub fn SysCtlPeripheralDeepSleepDisable(ui32Peripheral: u32); + pub fn SysCtlPeripheralClockGating(bEnable: bool); + pub fn SysCtlIntRegister(pfnHandler: Option); + pub fn SysCtlIntUnregister(); + pub fn SysCtlIntEnable(ui32Ints: u32); + pub fn SysCtlIntDisable(ui32Ints: u32); + pub fn SysCtlIntClear(ui32Ints: u32); + pub fn SysCtlIntStatus(bMasked: bool) -> u32; + pub fn SysCtlLDOSleepSet(ui32Voltage: u32); + pub fn SysCtlLDOSleepGet() -> u32; + pub fn SysCtlLDODeepSleepSet(ui32Voltage: u32); + pub fn SysCtlLDODeepSleepGet() -> u32; + pub fn SysCtlSleepPowerSet(ui32Config: u32); + pub fn SysCtlDeepSleepPowerSet(ui32Config: u32); + pub fn SysCtlReset(); + pub fn SysCtlSleep(); + pub fn SysCtlDeepSleep(); + pub fn SysCtlResetCauseGet() -> u32; + pub fn SysCtlResetCauseClear(ui32Causes: u32); + pub fn SysCtlBrownOutConfigSet(ui32Config: u32, ui32Delay: u32); + pub fn SysCtlDelay(ui32Count: u32); + pub fn SysCtlMOSCConfigSet(ui32Config: u32); + pub fn SysCtlPIOSCCalibrate(ui32Type: u32) -> u32; + pub fn SysCtlClockSet(ui32Config: u32); + pub fn SysCtlClockGet() -> u32; + pub fn SysCtlDeepSleepClockSet(ui32Config: u32); + pub fn SysCtlDeepSleepClockConfigSet(ui32Div: u32, ui32Config: u32); + pub fn SysCtlPWMClockSet(ui32Config: u32); + pub fn SysCtlPWMClockGet() -> u32; + pub fn SysCtlIOSCVerificationSet(bEnable: bool); + pub fn SysCtlMOSCVerificationSet(bEnable: bool); + pub fn SysCtlPLLVerificationSet(bEnable: bool); + pub fn SysCtlClkVerificationClear(); + pub fn SysCtlGPIOAHBEnable(ui32GPIOPeripheral: u32); + pub fn SysCtlGPIOAHBDisable(ui32GPIOPeripheral: u32); + pub fn SysCtlUSBPLLEnable(); + pub fn SysCtlUSBPLLDisable(); + pub fn SysCtlClockFreqSet(ui32Config: u32, ui32SysClock: u32) -> u32; + pub fn SysCtlResetBehaviorSet(ui32Behavior: u32); + pub fn SysCtlResetBehaviorGet() -> u32; + pub fn SysCtlClockOutConfig(ui32Config: u32, ui32Div: u32); + pub fn SysCtlAltClkConfig(ui32Config: u32); + pub fn SysCtlNMIStatus() -> u32; + pub fn SysCtlNMIClear(ui32Status: u32); + pub fn SysCtlVoltageEventConfig(ui32Config: u32); + pub fn SysCtlVoltageEventStatus() -> u32; + pub fn SysCtlVoltageEventClear(ui32Status: u32); + pub fn SysCtlVCOGet(ui32Crystal: u32, pui32VCOFrequency: *const u32) -> bool; +} \ No newline at end of file diff --git a/src/systick.rs b/src/systick.rs new file mode 100644 index 0000000..14ad293 --- /dev/null +++ b/src/systick.rs @@ -0,0 +1,45 @@ +pub fn SysTickEnableWrap() { + unsafe { SysTickEnable(); } +} + +pub fn SysTickDisableWrap() { + unsafe { SysTickDisable(); } +} + +pub fn SysTickIntUnregisterWrap() { + unsafe { SysTickIntUnregister(); } +} + +pub fn SysTickIntEnableWrap() { + unsafe { SysTickIntEnable(); } +} + +pub fn SysTickIntDisableWrap() { + unsafe { SysTickIntDisable(); } +} + +pub fn SysTickPeriodSetWrap(ui32Period: u32) { + unsafe { SysTickPeriodSet(ui32Period); } +} + +pub fn SysTickPeriodGetWrap() -> u32 { + unsafe { SysTickPeriodGet() } +} + +pub fn SysTickValueGetWrap() -> u32 { + unsafe { SysTickValueGet() } +} + + +#[link(name="systick", kind="static")] +extern "C" { + pub fn SysTickEnable(); + pub fn SysTickDisable(); +// pub fn SysTickIntRegister((*pfnHandler)(void): ); + pub fn SysTickIntUnregister(); + pub fn SysTickIntEnable(); + pub fn SysTickIntDisable(); + pub fn SysTickPeriodSet(ui32Period: u32); + pub fn SysTickPeriodGet() -> u32; + pub fn SysTickValueGet() -> u32; +} \ No newline at end of file diff --git a/src/timer.rs b/src/timer.rs new file mode 100644 index 0000000..517877d --- /dev/null +++ b/src/timer.rs @@ -0,0 +1,194 @@ +pub fn TimerEnableWrap(ui32Base: u32, ui32Timer: u32) { + unsafe { TimerEnable(ui32Base, ui32Timer) }; +} + +pub fn TimerDisableWrap(ui32Base: u32, ui32Timer: u32) { + unsafe { TimerDisable(ui32Base, ui32Timer) }; +} + +pub fn TimerConfigureWrap(ui32Base: u32, ui32Config: u32) { + unsafe { TimerConfigure(ui32Base, ui32Config) }; +} + +pub fn TimerControlLevelWrap(ui32Base: u32, ui32Timer: u32, bInvert: bool) { + unsafe { TimerControlLevel(ui32Base, ui32Timer, bInvert) }; +} + +pub fn TimerControlTriggerWrap(ui32Base: u32, ui32Timer: u32, bEnable: bool) { + unsafe { TimerControlTrigger(ui32Base, ui32Timer, bEnable) }; +} + +pub fn TimerControlEventWrap(ui32Base: u32, ui32Timer: u32, ui32Event: u32) { + unsafe { TimerControlEvent(ui32Base, ui32Timer, ui32Event) }; +} + +pub fn TimerControlStallWrap(ui32Base: u32, ui32Timer: u32, bStall: bool) { + unsafe { TimerControlStall(ui32Base, ui32Timer, bStall) }; +} + +pub fn TimerControlWaitOnTriggerWrap(ui32Base: u32, ui32Timer: u32, bWait: bool) { + unsafe { TimerControlWaitOnTrigger(ui32Base, ui32Timer, bWait) }; +} + +pub fn TimerRTCEnableWrap(ui32Base: u32) { + unsafe { TimerRTCEnable(ui32Base) }; +} + +pub fn TimerRTCDisableWrap(ui32Base: u32) { + unsafe { TimerRTCDisable(ui32Base) }; +} + +pub fn TimerPrescaleSetWrap(ui32Base: u32, ui32Timer: u32, ui32Value: u32) { + unsafe { TimerPrescaleSet(ui32Base, ui32Timer, ui32Value) }; +} + +pub fn TimerPrescaleGetWrap(ui32Base: u32, ui32Timer: u32) -> u32 { + return unsafe { TimerPrescaleGet(ui32Base, ui32Timer) }; +} + +pub fn TimerPrescaleMatchSetWrap(ui32Base: u32, ui32Timer: u32, ui32Value: u32) { + unsafe { TimerPrescaleMatchSet(ui32Base, ui32Timer, ui32Value) }; +} + +pub fn TimerPrescaleMatchGetWrap(ui32Base: u32, ui32Timer: u32) -> u32 { + return unsafe { TimerPrescaleMatchGet(ui32Base, ui32Timer) }; +} + +pub fn TimerLoadSetWrap(ui32Base: u32, ui32Timer: u32, ui32Value: u32) { + unsafe { TimerLoadSet(ui32Base, ui32Timer, ui32Value) }; +} + +pub fn TimerLoadGetWrap(ui32Base: u32, ui32Timer: u32) -> u32 { + return unsafe { TimerLoadGet(ui32Base, ui32Timer) }; +} + +pub fn TimerLoadSet64Wrap(ui32Base: u32, ui64Value: u64) { + unsafe { TimerLoadSet64(ui32Base, ui64Value) }; +} + +pub fn TimerLoadGet64Wrap(ui32Base: u32) -> u64 { + return unsafe { TimerLoadGet64(ui32Base) }; +} + +pub fn TimerValueGetWrap(ui32Base: u32, ui32Timer: u32) -> u32 { + return unsafe { TimerValueGet(ui32Base, ui32Timer) }; +} + +pub fn TimerValueGet64Wrap(ui32Base: u32) -> u64 { + return unsafe { TimerValueGet64(ui32Base) }; +} + +pub fn TimerMatchSetWrap(ui32Base: u32, ui32Timer: u32, ui32Value: u32) { + unsafe { TimerMatchSet(ui32Base, ui32Timer, ui32Value) }; +} + +pub fn TimerMatchGetWrap(ui32Base: u32, ui32Timer: u32) -> u32 { + return unsafe { TimerMatchGet(ui32Base, ui32Timer) }; +} + +pub fn TimerMatchSet64Wrap(ui32Base: u32, ui64Value: u64) { + unsafe { TimerMatchSet64(ui32Base, ui64Value) }; +} + +pub fn TimerMatchGet64Wrap(ui32Base: u32) -> u64 { + return unsafe { TimerMatchGet64(ui32Base) }; +} + +pub fn TimerIntRegisterWrap(ui32Base: u32, ui32Timer: u32, pfnHandler: Option) { + unsafe { TimerIntRegister(ui32Base, ui32Timer, pfnHandler) }; +} + +pub fn TimerIntUnregisterWrap(ui32Base: u32, ui32Timer: u32) { + unsafe { TimerIntUnregister(ui32Base, ui32Timer) }; +} + +pub fn TimerIntEnableWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { TimerIntEnable(ui32Base, ui32IntFlags) }; +} + +pub fn TimerIntDisableWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { TimerIntDisable(ui32Base, ui32IntFlags) }; +} + +pub fn TimerIntStatusWrap(ui32Base: u32, bMasked: bool) -> u32 { + return unsafe { TimerIntStatus(ui32Base, bMasked) }; +} + +pub fn TimerIntClearWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { TimerIntClear(ui32Base, ui32IntFlags) }; +} + +pub fn TimerSynchronizeWrap(ui32Base: u32, ui32Timers: u32) { + unsafe { TimerSynchronize(ui32Base, ui32Timers) }; +} + +pub fn TimerClockSourceGetWrap(ui32Base: u32) -> u32 { + return unsafe { TimerClockSourceGet(ui32Base) }; +} + +pub fn TimerClockSourceSetWrap(ui32Base: u32, ui32Source: u32) { + unsafe { TimerClockSourceSet(ui32Base, ui32Source) }; +} + +pub fn TimerADCEventGetWrap(ui32Base: u32) -> u32 { + return unsafe { TimerADCEventGet(ui32Base) }; +} + +pub fn TimerADCEventSetWrap(ui32Base: u32, ui32ADCEvent: u32) { + unsafe { TimerADCEventSet(ui32Base, ui32ADCEvent) }; +} + +pub fn TimerDMAEventGetWrap(ui32Base: u32) -> u32 { + return unsafe { TimerDMAEventGet(ui32Base) }; +} + +pub fn TimerDMAEventSetWrap(ui32Base: u32, ui32DMAEvent: u32) { + unsafe { TimerDMAEventSet(ui32Base, ui32DMAEvent) }; +} + +pub fn TimerUpdateModeWrap(ui32Base: u32, ui32Timer: u32, ui32Config: u32) { + unsafe { TimerUpdateMode(ui32Base, ui32Timer, ui32Config) }; +} + + +#[link(name="timer", kind="static")] +extern "C" { + pub fn TimerEnable(ui32Base: u32, ui32Timer: u32); + pub fn TimerDisable(ui32Base: u32, ui32Timer: u32); + pub fn TimerConfigure(ui32Base: u32, ui32Config: u32); + pub fn TimerControlLevel(ui32Base: u32, ui32Timer: u32, bInvert: bool); + pub fn TimerControlTrigger(ui32Base: u32, ui32Timer: u32, bEnable: bool); + pub fn TimerControlEvent(ui32Base: u32, ui32Timer: u32, ui32Event: u32); + pub fn TimerControlStall(ui32Base: u32, ui32Timer: u32, bStall: bool); + pub fn TimerControlWaitOnTrigger(ui32Base: u32, ui32Timer: u32, bWait: bool); + pub fn TimerRTCEnable(ui32Base: u32); + pub fn TimerRTCDisable(ui32Base: u32); + pub fn TimerPrescaleSet(ui32Base: u32, ui32Timer: u32, ui32Value: u32); + pub fn TimerPrescaleGet(ui32Base: u32, ui32Timer: u32) -> u32; + pub fn TimerPrescaleMatchSet(ui32Base: u32, ui32Timer: u32, ui32Value: u32); + pub fn TimerPrescaleMatchGet(ui32Base: u32, ui32Timer: u32) -> u32; + pub fn TimerLoadSet(ui32Base: u32, ui32Timer: u32, ui32Value: u32); + pub fn TimerLoadGet(ui32Base: u32, ui32Timer: u32) -> u32; + pub fn TimerLoadSet64(ui32Base: u32, ui64Value: u64); + pub fn TimerLoadGet64(ui32Base: u32) -> u64; + pub fn TimerValueGet(ui32Base: u32, ui32Timer: u32) -> u32; + pub fn TimerValueGet64(ui32Base: u32) -> u64; + pub fn TimerMatchSet(ui32Base: u32, ui32Timer: u32, ui32Value: u32); + pub fn TimerMatchGet(ui32Base: u32, ui32Timer: u32) -> u32; + pub fn TimerMatchSet64(ui32Base: u32, ui64Value: u64); + pub fn TimerMatchGet64(ui32Base: u32) -> u64; + pub fn TimerIntRegister(ui32Base: u32, ui32Timer: u32, pfnHandler: Option); + pub fn TimerIntUnregister(ui32Base: u32, ui32Timer: u32); + pub fn TimerIntEnable(ui32Base: u32, ui32IntFlags: u32); + pub fn TimerIntDisable(ui32Base: u32, ui32IntFlags: u32); + pub fn TimerIntStatus(ui32Base: u32, bMasked: bool) -> u32; + pub fn TimerIntClear(ui32Base: u32, ui32IntFlags: u32); + pub fn TimerSynchronize(ui32Base: u32, ui32Timers: u32); + pub fn TimerClockSourceGet(ui32Base: u32) -> u32; + pub fn TimerClockSourceSet(ui32Base: u32, ui32Source: u32); + pub fn TimerADCEventGet(ui32Base: u32) -> u32; + pub fn TimerADCEventSet(ui32Base: u32, ui32ADCEvent: u32); + pub fn TimerDMAEventGet(ui32Base: u32) -> u32; + pub fn TimerDMAEventSet(ui32Base: u32, ui32DMAEvent: u32); + pub fn TimerUpdateMode(ui32Base: u32, ui32Timer: u32, ui32Config: u32); +} \ No newline at end of file diff --git a/src/tm123.rs b/src/tm123.rs new file mode 100644 index 0000000..1041ac6 --- /dev/null +++ b/src/tm123.rs @@ -0,0 +1,18734 @@ +// TM4C123GH6PM interrupt bit definitions + +pub const NUM_PRIORITY:u32 = 8; +pub const NUM_PRIORITY_BITS:u32= 3; + + + +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ui32Trigger +// parameter. +// +//***************************************************************************** +pub const ADC_TRIGGER_PROCESSOR: u32 = 0x00000000; // Processor event +pub const ADC_TRIGGER_COMP0: u32 = 0x00000001; // Analog comparator 0 event +pub const ADC_TRIGGER_COMP1: u32 = 0x00000002; // Analog comparator 1 event +pub const ADC_TRIGGER_COMP2: u32 = 0x00000003; // Analog comparator 2 event +pub const ADC_TRIGGER_EXTERNAL: u32 = 0x00000004; // External event +pub const ADC_TRIGGER_TIMER: u32 = 0x00000005; // Timer event +pub const ADC_TRIGGER_PWM0: u32 = 0x00000006; // PWM0 event +pub const ADC_TRIGGER_PWM1: u32 = 0x00000007; // PWM1 event +pub const ADC_TRIGGER_PWM2: u32 = 0x00000008; // PWM2 event +pub const ADC_TRIGGER_PWM3: u32 = 0x00000009; // PWM3 event +pub const ADC_TRIGGER_NEVER: u32 = 0x0000000E; // Never Trigger +pub const ADC_TRIGGER_ALWAYS: u32 = 0x0000000F; // Always event +pub const ADC_TRIGGER_PWM_MOD0: u32 = 0x00000000; // PWM triggers from PWM0 +pub const ADC_TRIGGER_PWM_MOD1: u32 = 0x00000010; // PWM triggers from PWM1 +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ui32Config +// parameter. +// +//***************************************************************************** +pub const ADC_CTL_TS: u32 = 0x00000080; // Temperature sensor select +pub const ADC_CTL_IE: u32 = 0x00000040; // Interrupt enable +pub const ADC_CTL_END: u32 = 0x00000020; // Sequence end select +pub const ADC_CTL_D: u32 = 0x00000010; // Differential select +pub const ADC_CTL_CH0: u32 = 0x00000000; // Input channel 0 +pub const ADC_CTL_CH1: u32 = 0x00000001; // Input channel 1 +pub const ADC_CTL_CH2: u32 = 0x00000002; // Input channel 2 +pub const ADC_CTL_CH3: u32 = 0x00000003; // Input channel 3 +pub const ADC_CTL_CH4: u32 = 0x00000004; // Input channel 4 +pub const ADC_CTL_CH5: u32 = 0x00000005; // Input channel 5 +pub const ADC_CTL_CH6: u32 = 0x00000006; // Input channel 6 +pub const ADC_CTL_CH7: u32 = 0x00000007; // Input channel 7 +pub const ADC_CTL_CH8: u32 = 0x00000008; // Input channel 8 +pub const ADC_CTL_CH9: u32 = 0x00000009; // Input channel 9 +pub const ADC_CTL_CH10: u32 = 0x0000000A; // Input channel 10 +pub const ADC_CTL_CH11: u32 = 0x0000000B; // Input channel 11 +pub const ADC_CTL_CH12: u32 = 0x0000000C; // Input channel 12 +pub const ADC_CTL_CH13: u32 = 0x0000000D; // Input channel 13 +pub const ADC_CTL_CH14: u32 = 0x0000000E; // Input channel 14 +pub const ADC_CTL_CH15: u32 = 0x0000000F; // Input channel 15 +pub const ADC_CTL_CH16: u32 = 0x00000100; // Input channel 16 +pub const ADC_CTL_CH17: u32 = 0x00000101; // Input channel 17 +pub const ADC_CTL_CH18: u32 = 0x00000102; // Input channel 18 +pub const ADC_CTL_CH19: u32 = 0x00000103; // Input channel 19 +pub const ADC_CTL_CH20: u32 = 0x00000104; // Input channel 20 +pub const ADC_CTL_CH21: u32 = 0x00000105; // Input channel 21 +pub const ADC_CTL_CH22: u32 = 0x00000106; // Input channel 22 +pub const ADC_CTL_CH23: u32 = 0x00000107; // Input channel 23 +pub const ADC_CTL_CMP0: u32 = 0x00080000; // Select Comparator 0 +pub const ADC_CTL_CMP1: u32 = 0x00090000; // Select Comparator 1 +pub const ADC_CTL_CMP2: u32 = 0x000A0000; // Select Comparator 2 +pub const ADC_CTL_CMP3: u32 = 0x000B0000; // Select Comparator 3 +pub const ADC_CTL_CMP4: u32 = 0x000C0000; // Select Comparator 4 +pub const ADC_CTL_CMP5: u32 = 0x000D0000; // Select Comparator 5 +pub const ADC_CTL_CMP6: u32 = 0x000E0000; // Select Comparator 6 +pub const ADC_CTL_CMP7: u32 = 0x000F0000; // Select Comparator 7 +pub const ADC_CTL_SHOLD_4: u32 = 0x00000000; // Sample and hold 4 ADC clocks +pub const ADC_CTL_SHOLD_8: u32 = 0x00200000; // Sample and hold 8 ADC clocks +pub const ADC_CTL_SHOLD_16: u32 = 0x00400000; // Sample and hold 16 ADC clocks +pub const ADC_CTL_SHOLD_32: u32 = 0x00600000; // Sample and hold 32 ADC clocks +pub const ADC_CTL_SHOLD_64: u32 = 0x00800000; // Sample and hold 64 ADC clocks +pub const ADC_CTL_SHOLD_128: u32 = 0x00A00000; // Sample and hold 128 ADC clocks +pub const ADC_CTL_SHOLD_256: u32 = 0x00C00000; // Sample and hold 256 ADC clocks +//***************************************************************************** +// +// Values that can be passed to ADCComparatorConfigure as part of the +// ui32Config parameter. +// +//***************************************************************************** +pub const ADC_COMP_TRIG_NONE: u32 = 0x00000000; // Trigger Disabled +pub const ADC_COMP_TRIG_LOW_ALWAYS: u32 = 0x00001000; // Trigger Low Always +pub const ADC_COMP_TRIG_LOW_ONCE: u32 = 0x00001100; // Trigger Low Once +pub const ADC_COMP_TRIG_LOW_HALWAYS: u32 = 0x00001200; // Trigger Low Always (Hysteresis) +pub const ADC_COMP_TRIG_LOW_HONCE: u32 = 0x00001300; // Trigger Low Once (Hysteresis) +pub const ADC_COMP_TRIG_MID_ALWAYS: u32 = 0x00001400; // Trigger Mid Always +pub const ADC_COMP_TRIG_MID_ONCE: u32 = 0x00001500; // Trigger Mid Once +pub const ADC_COMP_TRIG_HIGH_ALWAYS: u32 = 0x00001C00; // Trigger High Always +pub const ADC_COMP_TRIG_HIGH_ONCE: u32 = 0x00001D00; // Trigger High Once +pub const ADC_COMP_TRIG_HIGH_HALWAYS: u32 = 0x00001E00; // Trigger High Always (Hysteresis) +pub const ADC_COMP_TRIG_HIGH_HONCE: u32 = 0x00001F00; // Trigger High Once (Hysteresis) +pub const ADC_COMP_INT_NONE: u32 = 0x00000000; // Interrupt Disabled +pub const ADC_COMP_INT_LOW_ALWAYS: u32 = 0x00000010; // Interrupt Low Always +pub const ADC_COMP_INT_LOW_ONCE: u32 = 0x00000011; // Interrupt Low Once +pub const ADC_COMP_INT_LOW_HALWAYS: u32 = 0x00000012; // Interrupt Low Always + // (Hysteresis) +pub const ADC_COMP_INT_LOW_HONCE: u32 = 0x00000013; // Interrupt Low Once (Hysteresis) +pub const ADC_COMP_INT_MID_ALWAYS: u32 = 0x00000014; // Interrupt Mid Always +pub const ADC_COMP_INT_MID_ONCE: u32 = 0x00000015; // Interrupt Mid Once +pub const ADC_COMP_INT_HIGH_ALWAYS: u32 = 0x0000001C; // Interrupt High Always +pub const ADC_COMP_INT_HIGH_ONCE: u32 = 0x0000001D; // Interrupt High Once +pub const ADC_COMP_INT_HIGH_HALWAYS: u32 = 0x0000001E; // Interrupt High Always + // (Hysteresis) +pub const ADC_COMP_INT_HIGH_HONCE: u32 = 0x0000001F; // Interrupt High Once (Hysteresis) +//***************************************************************************** +// +// Values that can be used to modify the sequence number passed to +// ADCProcessorTrigger in order to get cross-module synchronous processor +// triggers. +// +//***************************************************************************** +pub const ADC_TRIGGER_WAIT: u32 = 0x08000000; // Wait for the synchronous trigger +pub const ADC_TRIGGER_SIGNAL: u32 = 0x80000000; // Signal the synchronous trigger +//***************************************************************************** +// +// Values that can be passed to ADCPhaseDelaySet as the ui32Phase parameter and +// returned from ADCPhaseDelayGet. +// +//***************************************************************************** +pub const ADC_PHASE_0: u32 = 0x00000000; // 0 degrees +pub const ADC_PHASE_22_5: u32 = 0x00000001; // 22.5 degrees +pub const ADC_PHASE_45: u32 = 0x00000002; // 45 degrees +pub const ADC_PHASE_67_5: u32 = 0x00000003; // 67.5 degrees +pub const ADC_PHASE_90: u32 = 0x00000004; // 90 degrees +pub const ADC_PHASE_112_5: u32 = 0x00000005; // 112.5 degrees +pub const ADC_PHASE_135: u32 = 0x00000006; // 135 degrees +pub const ADC_PHASE_157_5: u32 = 0x00000007; // 157.5 degrees +pub const ADC_PHASE_180: u32 = 0x00000008; // 180 degrees +pub const ADC_PHASE_202_5: u32 = 0x00000009; // 202.5 degrees +pub const ADC_PHASE_225: u32 = 0x0000000A; // 225 degrees +pub const ADC_PHASE_247_5: u32 = 0x0000000B; // 247.5 degrees +pub const ADC_PHASE_270: u32 = 0x0000000C; // 270 degrees +pub const ADC_PHASE_292_5: u32 = 0x0000000D; // 292.5 degrees +pub const ADC_PHASE_315: u32 = 0x0000000E; // 315 degrees +pub const ADC_PHASE_337_5: u32 = 0x0000000F; // 337.5 degrees +//***************************************************************************** +// +// Values that can be passed to ADCReferenceSet as the ui32Ref parameter. +// +//***************************************************************************** +pub const ADC_REF_INT: u32 = 0x00000000; // Internal reference +pub const ADC_REF_EXT_3V: u32 = 0x00000001; // External 3V reference +//***************************************************************************** +// +// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(), +// ADCIntClearEx() and ADCIntStatusEx(). +// +//***************************************************************************** +pub const ADC_INT_SS0: u32 = 0x00000001; +pub const ADC_INT_SS1: u32 = 0x00000002; +pub const ADC_INT_SS2: u32 = 0x00000004; +pub const ADC_INT_SS3: u32 = 0x00000008; +pub const ADC_INT_DMA_SS0: u32 = 0x00000100; +pub const ADC_INT_DMA_SS1: u32 = 0x00000200; +pub const ADC_INT_DMA_SS2: u32 = 0x00000400; +pub const ADC_INT_DMA_SS3: u32 = 0x00000800; +pub const ADC_INT_DCON_SS0: u32 = 0x00010000; +pub const ADC_INT_DCON_SS1: u32 = 0x00020000; +pub const ADC_INT_DCON_SS2: u32 = 0x00040000; +pub const ADC_INT_DCON_SS3: u32 = 0x00080000; +//***************************************************************************** +// +// Values that can be passed to ADCClockConfigSet() and ADCClockConfigGet(). +// +//***************************************************************************** +pub const ADC_CLOCK_RATE_FULL: u32 = 0x00000070; +pub const ADC_CLOCK_RATE_HALF: u32 = 0x00000050; +pub const ADC_CLOCK_RATE_FOURTH: u32 = 0x00000030; +pub const ADC_CLOCK_RATE_EIGHTH: u32 = 0x00000010; +pub const ADC_CLOCK_SRC_PLL: u32 = 0x00000000; +pub const ADC_CLOCK_SRC_PIOSC: u32 = 0x00000001; +pub const ADC_CLOCK_SRC_ALTCLK: u32 = 0x00000001; +pub const ADC_CLOCK_SRC_MOSC: u32 = 0x00000002; +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// aes.h - Defines and Macros for the AES module. +// +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// The following defines are used to specify the operation direction in the +// ui32Config argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +pub const AES_CFG_DIR_ENCRYPT: u32 = 0x00000004; +pub const AES_CFG_DIR_DECRYPT: u32 = 0x00000000; +//***************************************************************************** +// +// The following defines are used to specify the key size in the ui32Config +// argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +pub const AES_CFG_KEY_SIZE_128BIT: u32 = 0x00000008; +pub const AES_CFG_KEY_SIZE_192BIT: u32 = 0x00000010; +pub const AES_CFG_KEY_SIZE_256BIT: u32 = 0x00000018; +//***************************************************************************** +// +// The following defines are used to specify the mode of operation in the +// ui32Config argument in the AESConfig function. Only one is permitted. +// +//***************************************************************************** +pub const AES_CFG_MODE_M: u32 = 0x2007fe60; +pub const AES_CFG_MODE_ECB: u32 = 0x00000000; +pub const AES_CFG_MODE_CBC: u32 = 0x00000020; +pub const AES_CFG_MODE_CTR: u32 = 0x00000040; +pub const AES_CFG_MODE_ICM: u32 = 0x00000200; +pub const AES_CFG_MODE_CFB: u32 = 0x00000400; +pub const AES_CFG_MODE_XTS_TWEAKJL: u32 = 0x00000800; +pub const AES_CFG_MODE_XTS_K2IJL: u32 = 0x00001000; +pub const AES_CFG_MODE_XTS_K2ILJ0: u32 = 0x00001800; +pub const AES_CFG_MODE_F8: u32 = 0x00002000; +pub const AES_CFG_MODE_F9: u32 = 0x20004000; +pub const AES_CFG_MODE_CBCMAC: u32 = 0x20008000; +pub const AES_CFG_MODE_GCM_HLY0ZERO: u32 = 0x20010000; +pub const AES_CFG_MODE_GCM_HLY0CALC: u32 = 0x20020040; +pub const AES_CFG_MODE_GCM_HY0CALC: u32 = 0x20030040; +pub const AES_CFG_MODE_CCM: u32 = 0x20040040; +//***************************************************************************** +// +// The following defines are used to specify the counter width in the +// ui32Config argument in the AESConfig function. It is only required to +// be defined when using CTR, CCM, or GCM modes. Only one length is permitted. +// +//***************************************************************************** +pub const AES_CFG_CTR_WIDTH_32: u32 = 0x00000000; +pub const AES_CFG_CTR_WIDTH_64: u32 = 0x00000080; +pub const AES_CFG_CTR_WIDTH_96: u32 = 0x00000100; +pub const AES_CFG_CTR_WIDTH_128: u32 = 0x00000180; +//***************************************************************************** +// +// The following defines are used to define the width of the length field for +// CCM operation through the ui32Config argument in the AESConfig function. +// This value is also known as L. Only one is permitted. +// +//***************************************************************************** +pub const AES_CFG_CCM_L_1: u32 = 0x00000000; +pub const AES_CFG_CCM_L_2: u32 = 0x00080000; +pub const AES_CFG_CCM_L_3: u32 = 0x00100000; +pub const AES_CFG_CCM_L_4: u32 = 0x00180000; +pub const AES_CFG_CCM_L_5: u32 = 0x00200000; +pub const AES_CFG_CCM_L_6: u32 = 0x00280000; +pub const AES_CFG_CCM_L_7: u32 = 0x00300000; +pub const AES_CFG_CCM_L_8: u32 = 0x00380000; +//***************************************************************************** +// +// The following defines are used to define the length of the authentication +// field for CCM operations through the ui32Config argument in the AESConfig +// function. This value is also known as M. Only one is permitted. +// +//***************************************************************************** +pub const AES_CFG_CCM_M_4: u32 = 0x00400000; +pub const AES_CFG_CCM_M_6: u32 = 0x00800000; +pub const AES_CFG_CCM_M_8: u32 = 0x00c00000; +pub const AES_CFG_CCM_M_10: u32 = 0x01000000; +pub const AES_CFG_CCM_M_12: u32 = 0x01400000; +pub const AES_CFG_CCM_M_14: u32 = 0x01800000; +pub const AES_CFG_CCM_M_16: u32 = 0x01c00000; +//***************************************************************************** +// +// Interrupt flags for use with the AESIntEnable, AESIntDisable, and +// AESIntStatus functions. +// +//***************************************************************************** +pub const AES_INT_CONTEXT_IN: u32 = 0x00000001; +pub const AES_INT_CONTEXT_OUT: u32 = 0x00000008; +pub const AES_INT_DATA_IN: u32 = 0x00000002; +pub const AES_INT_DATA_OUT: u32 = 0x00000004; +pub const AES_INT_DMA_CONTEXT_IN: u32 = 0x00010000; +pub const AES_INT_DMA_CONTEXT_OUT: u32 = 0x00080000; +pub const AES_INT_DMA_DATA_IN: u32 = 0x00020000; +pub const AES_INT_DMA_DATA_OUT: u32 = 0x00040000; +//***************************************************************************** +// +// Defines used when enabling and disabling DMA requests in the +// AESEnableDMA and AESDisableDMA functions. +// +//***************************************************************************** +pub const AES_DMA_DATA_IN: u32 = 0x00000020; +pub const AES_DMA_DATA_OUT: u32 = 0x00000040; +pub const AES_DMA_CONTEXT_IN: u32 = 0x00000080; +pub const AES_DMA_CONTEXT_OUT: u32 = 0x00000100; +//***************************************************************************** +// +// Function prototypes. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// can.h - Defines and Macros for the CAN controller. +// +// Copyright (c) 2006-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// \addtogroup can_api +// @{ +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Miscellaneous defines for Message ID Types +// +//***************************************************************************** +//***************************************************************************** +// +// These are the flags used by the tCANMsgObject.ui32Flags value when calling +// the CANMessageSet() and CANMessageGet() functions. +// +//***************************************************************************** +// +// This indicates that transmit interrupts are enabled. +// +pub const MSG_OBJ_TX_INT_ENABLE: u32 = 0x00000001; +// +// This indicates that receive interrupts are enabled. +// +pub const MSG_OBJ_RX_INT_ENABLE: u32 = 0x00000002; +// +// This indicates that a message object is using an extended identifier. +// +pub const MSG_OBJ_EXTENDED_ID: u32 = 0x00000004; +// +// This indicates that a message object is using filtering based on the +// object's message identifier. +// +pub const MSG_OBJ_USE_ID_FILTER: u32 = 0x00000008; +// +// This indicates that new data was available in the message object. +// +pub const MSG_OBJ_NEW_DATA: u32 = 0x00000080; +// +// This indicates that data was lost since this message object was last +// read. +// +pub const MSG_OBJ_DATA_LOST: u32 = 0x00000100; +// +// This indicates that a message object uses or is using filtering +// based on the direction of the transfer. If the direction filtering is +// used, then ID filtering must also be enabled. +// +pub const MSG_OBJ_USE_DIR_FILTER: u32 = 0x00000010; +// +// This indicates that a message object uses or is using message +// identifier filtering based on the extended identifier. If the extended +// identifier filtering is used, then ID filtering must also be enabled. +// +pub const MSG_OBJ_USE_EXT_FILTER: u32 = 0x00000020; +// +// This indicates that a message object is a remote frame. +// +pub const MSG_OBJ_REMOTE_FRAME: u32 = 0x00000040; +// +// This indicates that this message object is part of a FIFO structure and +// not the final message object in a FIFO. +// +pub const MSG_OBJ_FIFO: u32 = 0x00000200; +// +// This indicates that a message object has no flags set. +// +pub const MSG_OBJ_NO_FLAGS: u32 = 0x00000000; +//***************************************************************************** +// +// This define is used with the flag values to allow checking only status +// flags and not configuration flags. +// +//***************************************************************************** +pub const MSG_OBJ_STATUS_MASK: u32 = MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST; +//***************************************************************************** +// +// The structure used for encapsulating all the items associated with a CAN +// message object in the CAN controller. +// +//***************************************************************************** + // + // The CAN message identifier used for 11 or 29 bit identifiers. + // + // + // The message identifier mask used when identifier filtering is enabled. + // + // + // This value holds various status flags and settings specified by + // tCANObjFlags. + // + // + // This value is the number of bytes of data in the message object. + // + // + // This is a pointer to the message object's data. + // +//***************************************************************************** +// +// This structure is used for encapsulating the values associated with setting +// up the bit timing for a CAN controller. The structure is used when calling +// the CANGetBitTiming and CANSetBitTiming functions. +// +//***************************************************************************** + // + // This value holds the sum of the Synchronization, Propagation, and Phase + // Buffer 1 segments, measured in time quanta. The valid values for this + // setting range from 2 to 16. + // + // + // This value holds the Phase Buffer 2 segment in time quanta. The valid + // values for this setting range from 1 to 8. + // + // + // This value holds the Resynchronization Jump Width in time quanta. The + // valid values for this setting range from 1 to 4. + // + // + // This value holds the CAN_CLK divider used to determine time quanta. + // The valid values for this setting range from 1 to 1023. + // +//***************************************************************************** +// +// This data type is used to identify the interrupt status register. This is +// used when calling the CANIntStatus() function. +// +//***************************************************************************** + // + // Read the CAN interrupt status information. + // + // + // Read a message object's interrupt status. + // +//***************************************************************************** +// +// This data type is used to identify which of several status registers to +// read when calling the CANStatusGet() function. +// +//***************************************************************************** + // + // Read the full CAN controller status. + // + // + // Read the full 32-bit mask of message objects with a transmit request + // set. + // + // + // Read the full 32-bit mask of message objects with new data available. + // + // + // Read the full 32-bit mask of message objects that are enabled. + // +//***************************************************************************** +// +// These definitions are used to specify interrupt sources to CANIntEnable() +// and CANIntDisable(). +// +//***************************************************************************** +// +// This flag is used to allow a CAN controller to generate error +// interrupts. +// +pub const CAN_INT_ERROR: u32 = 0x00000008; +// +// This flag is used to allow a CAN controller to generate status +// interrupts. +// +pub const CAN_INT_STATUS: u32 = 0x00000004; +// +// This flag is used to allow a CAN controller to generate any CAN +// interrupts. If this is not set, then no interrupts are generated +// by the CAN controller. +// +pub const CAN_INT_MASTER: u32 = 0x00000002; +//***************************************************************************** +// +// This definition is used to determine the type of message object that is +// set up via a call to the CANMessageSet() API. +// +//***************************************************************************** + // + // Transmit message object. + // + // + // Transmit remote request message object + // + // + // Receive message object. + // + // + // Receive remote request message object. + // + // + // Remote frame receive remote, with auto-transmit message object. + // +//***************************************************************************** +// +// The following enumeration contains all error or status indicators that can +// be returned when calling the CANStatusGet() function. +// +//***************************************************************************** +// +// CAN controller has entered a Bus Off state. +// +pub const CAN_STATUS_BUS_OFF: u32 = 0x00000080; +// +// CAN controller error level has reached warning level. +// +pub const CAN_STATUS_EWARN: u32 = 0x00000040; +// +// CAN controller error level has reached error passive level. +// +pub const CAN_STATUS_EPASS: u32 = 0x00000020; +// +// A message was received successfully since the last read of this status. +// +pub const CAN_STATUS_RXOK: u32 = 0x00000010; +// +// A message was transmitted successfully since the last read of this +// status. +// +pub const CAN_STATUS_TXOK: u32 = 0x00000008; +// +// This is the mask for the last error code field. +// +pub const CAN_STATUS_LEC_MSK: u32 = 0x00000007; +// +// There was no error. +// +pub const CAN_STATUS_LEC_NONE: u32 = 0x00000000; +// +// A bit stuffing error has occurred. +// +pub const CAN_STATUS_LEC_STUFF: u32 = 0x00000001; +// +// A formatting error has occurred. +// +pub const CAN_STATUS_LEC_FORM: u32 = 0x00000002; +// +// An acknowledge error has occurred. +// +pub const CAN_STATUS_LEC_ACK: u32 = 0x00000003; +// +// The bus remained a bit level of 1 for longer than is allowed. +// +pub const CAN_STATUS_LEC_BIT1: u32 = 0x00000004; +// +// The bus remained a bit level of 0 for longer than is allowed. +// +pub const CAN_STATUS_LEC_BIT0: u32 = 0x00000005; +// +// A CRC error has occurred. +// +pub const CAN_STATUS_LEC_CRC: u32 = 0x00000006; +// +// This is the mask for the CAN Last Error Code (LEC). +// +pub const CAN_STATUS_LEC_MASK: u32 = 0x00000007; +//***************************************************************************** +// +// Close the Doxygen group. +// @} +// +//***************************************************************************** +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ui32Config +// parameter. For each group (in other words, COMP_TRIG_xxx, COMP_INT_xxx, and +// so on), one of the values may be selected and combined together with values +// from the other groups via a logical OR. +// +//***************************************************************************** +pub const COMP_TRIG_NONE: u32 = 0x00000000; // No ADC trigger +pub const COMP_TRIG_HIGH: u32 = 0x00000880; // Trigger when high +pub const COMP_TRIG_LOW: u32 = 0x00000800; // Trigger when low +pub const COMP_TRIG_FALL: u32 = 0x00000820; // Trigger on falling edge +pub const COMP_TRIG_RISE: u32 = 0x00000840; // Trigger on rising edge +pub const COMP_TRIG_BOTH: u32 = 0x00000860; // Trigger on both edges +pub const COMP_INT_HIGH: u32 = 0x00000010; // Interrupt when high +pub const COMP_INT_LOW: u32 = 0x00000000; // Interrupt when low +pub const COMP_INT_FALL: u32 = 0x00000004; // Interrupt on falling edge +pub const COMP_INT_RISE: u32 = 0x00000008; // Interrupt on rising edge +pub const COMP_INT_BOTH: u32 = 0x0000000C; // Interrupt on both edges +pub const COMP_ASRCP_PIN: u32 = 0x00000000; // Dedicated Comp+ pin +pub const COMP_ASRCP_PIN0: u32 = 0x00000200; // Comp0+ pin +pub const COMP_ASRCP_REF: u32 = 0x00000400; // Internal voltage reference +pub const COMP_OUTPUT_NORMAL: u32 = 0x00000000; // Comparator output normal +pub const COMP_OUTPUT_INVERT: u32 = 0x00000002; // Comparator output inverted +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ui32Ref parameter. +// +//***************************************************************************** +pub const COMP_REF_OFF: u32 = 0x00000000; // Turn off the internal reference +pub const COMP_REF_0V: u32 = 0x00000300; // Internal reference of 0V +pub const COMP_REF_0_1375V: u32 = 0x00000301; // Internal reference of 0.1375V +pub const COMP_REF_0_275V: u32 = 0x00000302; // Internal reference of 0.275V +pub const COMP_REF_0_4125V: u32 = 0x00000303; // Internal reference of 0.4125V +pub const COMP_REF_0_55V: u32 = 0x00000304; // Internal reference of 0.55V +pub const COMP_REF_0_6875V: u32 = 0x00000305; // Internal reference of 0.6875V +pub const COMP_REF_0_825V: u32 = 0x00000306; // Internal reference of 0.825V +pub const COMP_REF_0_928125V: u32 = 0x00000201; // Internal reference of 0.928125V +pub const COMP_REF_0_9625V: u32 = 0x00000307; // Internal reference of 0.9625V +pub const COMP_REF_1_03125V: u32 = 0x00000202; // Internal reference of 1.03125V +pub const COMP_REF_1_134375V: u32 = 0x00000203; // Internal reference of 1.134375V +pub const COMP_REF_1_1V: u32 = 0x00000308; // Internal reference of 1.1V +pub const COMP_REF_1_2375V: u32 = 0x00000309; // Internal reference of 1.2375V +pub const COMP_REF_1_340625V: u32 = 0x00000205; // Internal reference of 1.340625V +pub const COMP_REF_1_375V: u32 = 0x0000030A; // Internal reference of 1.375V +pub const COMP_REF_1_44375V: u32 = 0x00000206; // Internal reference of 1.44375V +pub const COMP_REF_1_5125V: u32 = 0x0000030B; // Internal reference of 1.5125V +pub const COMP_REF_1_546875V: u32 = 0x00000207; // Internal reference of 1.546875V +pub const COMP_REF_1_65V: u32 = 0x0000030C; // Internal reference of 1.65V +pub const COMP_REF_1_753125V: u32 = 0x00000209; // Internal reference of 1.753125V +pub const COMP_REF_1_7875V: u32 = 0x0000030D; // Internal reference of 1.7875V +pub const COMP_REF_1_85625V: u32 = 0x0000020A; // Internal reference of 1.85625V +pub const COMP_REF_1_925V: u32 = 0x0000030E; // Internal reference of 1.925V +pub const COMP_REF_1_959375V: u32 = 0x0000020B; // Internal reference of 1.959375V +pub const COMP_REF_2_0625V: u32 = 0x0000030F; // Internal reference of 2.0625V +pub const COMP_REF_2_165625V: u32 = 0x0000020D; // Internal reference of 2.165625V +pub const COMP_REF_2_26875V: u32 = 0x0000020E; // Internal reference of 2.26875V +pub const COMP_REF_2_371875V: u32 = 0x0000020F; // Internal reference of 2.371875V +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// crc.h - Defines and Macros for CRC module. +// +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// The following defines are used in the ui32Config argument of the +// ECConfig function. +// +//***************************************************************************** +pub const CRC_CFG_INIT_SEED: u32 = 0x00000000; // Initialize with seed +pub const CRC_CFG_INIT_0: u32 = 0x00004000; // Initialize to all '0s' +pub const CRC_CFG_INIT_1: u32 = 0x00006000; // Initialize to all '1s' +pub const CRC_CFG_SIZE_8BIT: u32 = 0x00001000; // Input Data Size +pub const CRC_CFG_SIZE_32BIT: u32 = 0x00000000; // Input Data Size +pub const CRC_CFG_RESINV: u32 = 0x00000200; // Result Inverse Enable +pub const CRC_CFG_OBR: u32 = 0x00000100; // Output Reverse Enable +pub const CRC_CFG_IBR: u32 = 0x00000080; // Bit reverse enable +pub const CRC_CFG_ENDIAN_SBHW: u32 = 0x00000020; // Swap byte in half-word +pub const CRC_CFG_ENDIAN_SHW: u32 = 0x00000010; // Swap half-word +pub const CRC_CFG_TYPE_P8005: u32 = 0x00000000; // Polynomial 0x8005 +pub const CRC_CFG_TYPE_P1021: u32 = 0x00000001; // Polynomial 0x1021 +pub const CRC_CFG_TYPE_P4C11DB7: u32 = 0x00000002; // Polynomial 0x4C11DB7 +pub const CRC_CFG_TYPE_P1EDC6F41: u32 = 0x00000003; // Polynomial 0x1EDC6F41 +pub const CRC_CFG_TYPE_TCPCHKSUM: u32 = 0x00000008; // TCP checksum +//***************************************************************************** +// +// Function prototypes. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// des.h - Defines and Macros for the DES module. +// +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// The following defines are used to specify the direction with the +// ui32Config argument in the DESConfig() function. Only one is permitted. +// +//***************************************************************************** +pub const DES_CFG_DIR_DECRYPT: u32 = 0x00000000; +pub const DES_CFG_DIR_ENCRYPT: u32 = 0x00000004; +//***************************************************************************** +// +// The following defines are used to specify the operational with the +// ui32Config argument in the DESConfig() function. Only one is permitted. +// +//***************************************************************************** +pub const DES_CFG_MODE_ECB: u32 = 0x00000000; +pub const DES_CFG_MODE_CBC: u32 = 0x00000010; +pub const DES_CFG_MODE_CFB: u32 = 0x00000020; +//***************************************************************************** +// +// The following defines are used to select between single DES and triple DES +// with the ui32Config argument in the DESConfig() function. Only one is +// permitted. +// +//***************************************************************************** +pub const DES_CFG_SINGLE: u32 = 0x00000000; +pub const DES_CFG_TRIPLE: u32 = 0x00000008; +//***************************************************************************** +// +// The following defines are used with the DESIntEnable(), DESIntDisable() and +// DESIntStatus() functions. +// +//***************************************************************************** +pub const DES_INT_CONTEXT_IN: u32 = 0x00000001; +pub const DES_INT_DATA_IN: u32 = 0x00000002; +pub const DES_INT_DATA_OUT: u32 = 0x00000004; +pub const DES_INT_DMA_CONTEXT_IN: u32 = 0x00010000; +pub const DES_INT_DMA_DATA_IN: u32 = 0x00020000; +pub const DES_INT_DMA_DATA_OUT: u32 = 0x00040000; +//***************************************************************************** +// +// The following defines are used with the DESEnableDMA() and DESDisableDMA() +// functions. +// +//***************************************************************************** +pub const DES_DMA_CONTEXT_IN: u32 = 0x00000080; +pub const DES_DMA_DATA_OUT: u32 = 0x00000040; +pub const DES_DMA_DATA_IN: u32 = 0x00000020; +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// eeprom.h - Prototypes for the EEPROM driver. +// +// Copyright (c) 2010-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// \addtogroup eeprom_api +// @{ +// +//***************************************************************************** +//***************************************************************************** +// +// Values returned by EEPROMInit. +// +//***************************************************************************** +// +// This value may be returned from a call to EEPROMInit(). It indicates that +// no previous write operations were interrupted by a reset event and that the +// EEPROM peripheral is ready for use. +// +pub const EEPROM_INIT_OK: u32 = 0; +// +// This value may be returned from a call to EEPROMInit(). It indicates that +// a previous data or protection write operation was interrupted by a reset +// event and that the EEPROM peripheral was unable to clean up after the +// problem. This situation may be resolved with another reset or may be fatal +// depending upon the cause of the problem. For example, if the voltage to +// the part is unstable, retrying once the voltage has stabilized may clear +// the error. +// +pub const EEPROM_INIT_ERROR: u32 = 2; +//***************************************************************************** +// +// Error indicators returned by various EEPROM API calls. These will be ORed +// together into the final return code. +// +//***************************************************************************** +// +// This return code bit indicates that an attempt was made to read from +// the EEPROM while a write operation was in progress. +// +pub const EEPROM_RC_WRBUSY: u32 = 0x00000020; +// +// This return code bit indicates that an attempt was made to write a +// value but the destination permissions disallow write operations. This +// may be due to the destination block being locked, access protection set +// to prohibit writes or an attempt to write a password when one is already +// written. +// +pub const EEPROM_RC_NOPERM: u32 = 0x00000010; +// +// This return code bit indicates that the EEPROM programming state machine +// is currently copying to or from the internal copy buffer to make room for +// a newly written value. It is provided as a status indicator and does not +// indicate an error. +// +pub const EEPROM_RC_WKCOPY: u32 = 0x00000008; +// +// This return code bit indicates that the EEPROM programming state machine +// is currently erasing the internal copy buffer. It is provided as a +// status indicator and does not indicate an error. +// +pub const EEPROM_RC_WKERASE: u32 = 0x00000004; +// +// This return code bit indicates that the EEPROM programming state machine +// is currently working. No new write operations should be attempted until +// this bit is clear. +// +pub const EEPROM_RC_WORKING: u32 = 0x00000001; +//***************************************************************************** +// +// Values that can be passed to EEPROMBlockProtectSet() in the ui32Protect +// parameter, and returned by EEPROMBlockProtectGet(). +// +//***************************************************************************** +// +// This bit may be ORed with the protection option passed to +// EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet(). It +// restricts EEPROM access to threads running in supervisor mode and prevents +// access to an EEPROM block when the CPU is in user mode. +// +pub const EEPROM_PROT_SUPERVISOR_ONLY: u32 = 0x00000008; +// +// This value may be passed to EEPROMBlockProtectSet() or returned from +// EEPROMBlockProtectGet(). It indicates that the block should offer +// read/write access when no password is set or when a password is set and +// the block is unlocked, and read-only access when a password is set but +// the block is locked. +// +pub const EEPROM_PROT_RW_LRO_URW: u32 = 0x00000000; +// +// This value may be passed to EEPROMBlockProtectSet() or returned from +// EEPROMBlockProtectGet(). It indicates that the block should offer neither +// read nor write access unless it is protected by a password and unlocked. +// +pub const EEPROM_PROT_NA_LNA_URW: u32 = 0x00000001; +// +// This value may be passed to EEPROMBlockProtectSet() or returned from +// EEPROMBlockProtectGet(). It indicates that the block should offer +// read-only access when no password is set or when a password is set and the +// block is unlocked. When a password is set and the block is locked, neither +// read nor write access is permitted. +// +pub const EEPROM_PROT_RO_LNA_URO: u32 = 0x00000002; +//***************************************************************************** +// +// This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is +// returned by EEPROMIntStatus() if an EEPROM interrupt is currently being +// signaled. +// +//***************************************************************************** +pub const EEPROM_INT_PROGRAM: u32 = 0x00000004; +//***************************************************************************** +// +// +//***************************************************************************** +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// The following definitions appeared in previous revisions of this file +// but have been deprecated and should not be used by applications. +// +//***************************************************************************** +// +// This value used to be one of those which could be returned from a call to +// EEPROMInit(). It transpires that it is was incorrect and has been removed +// after EEPROMInit() was reworked for TivaWare 2.1. +// +pub const EEPROM_INIT_RETRY: u32 = 1; +// +// This return code is not available from any Tiva part and has been removed. +// +pub const EEPROM_RC_INVPL: u32 = 0x00000100; +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// emac.h - Defines and Macros for the Ethernet module on Snowflake-class +// devices. +// +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// \addtogroup emac_api +// @{ +// +//***************************************************************************** +//***************************************************************************** +// +// The physical address of the internal PHY. This should be in hw_emac.h. +// +//***************************************************************************** +pub const EMAC_PHY_ADDR: u32 = 0; +//***************************************************************************** +// +// Helper Macros for Ethernet Processing +// +//***************************************************************************** +// +// htonl/ntohl - Big endian/little endian byte swapping macros for 32-bit +// values. +// +//***************************************************************************** +//***************************************************************************** +// +// htons/ntohs - Big endian/little endian byte swapping macros for 16-bit +// values. +// +//***************************************************************************** +//***************************************************************************** +// +// Forward reference to the Ethernet DMA descriptor structure. +// +//***************************************************************************** +//***************************************************************************** +// +// A union used to describe the two overlapping fields forming the third +// word of the Ethernet DMA descriptor. +// +//***************************************************************************** + // + // When DMA descriptors are used in chained mode, this field is used to + // provide a link to the next descriptor. + // + // + // When the DMA descriptors are unchained, this field may be used to point + // to a second buffer containing data for transmission or providing + // storage for a received frame. + // +//***************************************************************************** +// +// A structure defining a single Ethernet DMA buffer descriptor. +// +//***************************************************************************** + // + // The first DMA descriptor word contains various control and status bits + // depending upon whether the descriptor is in the transmit or receive + // queue. Bit 31 is always the ``OWN'' bit which, when set, indicates + // that the hardware has control of the descriptor. + // + // + // The second descriptor word contains information on the size of the + // buffer or buffers attached to the descriptor and various additional + // control bits. + // + // + // The third descriptor word contains a pointer to the buffer containing + // data to transmit or into which received data should be written. This + // pointer must refer to a buffer in internal SRAM. Pointers to flash or + // EPI-connected memory may not be used and will result in the MAC + // reporting a bus error. + // + // + // The fourth descriptor word contains either a pointer to the next + // descriptor in the ring or a pointer to a second data buffer. The + // meaning of the word is controlled by the ``CHAINED'' control bit which + // appears in the first word of the transmit descriptor or the second + // word of the receive descriptor. + // + // + // The fifth descriptor word is reserved for transmit descriptors but + // used to report extended status in a receive descriptor. + // + // + // The sixth descriptor word is reserved for both transmit and receive + // descriptors. + // + // + // The seventh descriptor word contains the low 32 bits of the 64-bit + // timestamp captured for transmitted or received data. The value is set + // only when the transmitted or received data contains the end of a + // packet. Availability of the timestamp is indicated via a status bit + // in the first descriptor word. + // + // + // The eighth descriptor word contains the high 32 bits of the 64-bit + // timestamp captured for transmitted or received data. + // +//***************************************************************************** +// +// Fields found in the DES0 word of the transmit descriptor (ui32CtrlStatus in +// tEMACDMADescriptor) +// +//***************************************************************************** +pub const DES0_TX_CTRL_OWN: u32 = 0x80000000; +pub const DES0_TX_CTRL_INTERRUPT: u32 = 0x40000000; +pub const DES0_TX_CTRL_LAST_SEG: u32 = 0x20000000; +pub const DES0_TX_CTRL_FIRST_SEG: u32 = 0x10000000; +// +// This value indicates that the MAC should not append a CRC to transmitted +// packets. If used with DES0_TX_CTRL_REPLACE_CRC, the last 4 bytes of the +// packet passed to the transmitter are replaced with a newly calculated CRC. +// If DES0_TX_CTRL_REPLACE_CRC is not specified, it is assumed that packets +// transmitted have valid CRCs precomputed and included in the frame data. +// +// If DES0_TX_CTRL_DISABLE_CRC is not specified, the MAC will calculate the +// CRC for all frames transmitted and append this value as the 4-byte FCS +// after the last data byte in the frame. +// +pub const DES0_TX_CTRL_DISABLE_CRC: u32 = 0x08000000; +pub const DES0_TX_CTRL_DISABLE_PADDING: u32 = 0x04000000; +pub const DES0_TX_CTRL_ENABLE_TS: u32 = 0x02000000; +// +// This value is only valid if used alongside DES0_TX_CTRL_DISABLE_CRC. When +// specified, the MAC will replace the last 4 bytes of a transmitted frame +// with a newly calculated CRC. +// +pub const DES0_TX_CTRL_REPLACE_CRC: u32 = 0x01000000; +pub const DES0_TX_CTRL_CHKSUM_M: u32 = 0x00C00000; +pub const DES0_TX_CTRL_NO_CHKSUM: u32 = 0x00000000; +pub const DES0_TX_CTRL_IP_HDR_CHKSUM: u32 = 0x00400000; +pub const DES0_TX_CTRL_IP_HDR_PAY_CHKSUM: u32 = 0x00800000; +pub const DES0_TX_CTRL_IP_ALL_CKHSUMS: u32 = 0x00C00000; +pub const DES0_TX_CTRL_END_OF_RING: u32 = 0x00200000; +pub const DES0_TX_CTRL_CHAINED: u32 = 0x00100000; +pub const DES0_TX_CTRL_VLAN_M: u32 = 0x000C0000; +pub const DES0_TX_CTRL_VLAN_NONE: u32 = 0x00000000; +pub const DES0_TX_CTRL_VLAN_REMOVE: u32 = 0x00040000; +pub const DES0_TX_CTRL_VLAN_INSERT: u32 = 0x00080000; +pub const DES0_TX_CTRL_VLAN_REPLACE: u32 = 0x000C0000; +pub const DES0_TX_STAT_TS_CAPTURED: u32 = 0x00020000; +pub const DES0_TX_STAT_IPH_ERR: u32 = 0x00010000; +pub const DES0_TX_STAT_ERR: u32 = 0x00008000; +pub const DES0_TX_STAT_JABBER_TO: u32 = 0x00004000; +pub const DES0_TX_STAT_FLUSHED: u32 = 0x00002000; +pub const DES0_TX_STAT_PAYLOAD_ERR: u32 = 0x00001000; +pub const DES0_TX_STAT_CARRIER_LOST: u32 = 0x00000800; +pub const DES0_TX_STAT_NO_CARRIER: u32 = 0x00000400; +pub const DES0_TX_STAT_TX_L_COLLISION: u32 = 0x00000200; +pub const DES0_TX_STAT_E_COLLISION: u32 = 0x00000100; +pub const DES0_TX_STAT_VLAN_FRAME: u32 = 0x00000080; +pub const DES0_TX_STAT_COL_COUNT_M: u32 = 0x00000078; +pub const DES0_TX_STAT_COL_COUNT_S: u32 = 3; +pub const DES0_TX_STAT_E_DEFERRAL: u32 = 0x00000004; +pub const DES0_TX_STAT_UNDERFLOW: u32 = 0x00000002; +pub const DES0_TX_STAT_DEFERRED: u32 = 0x00000001; +//***************************************************************************** +// +// Fields found in the DES1 word of the transmit descriptor (ui32Count in +// tEMACDMADescriptor) +// +//***************************************************************************** +pub const DES1_TX_CTRL_SADDR_MAC1: u32 = 0x80000000; +pub const DES1_TX_CTRL_SADDR_M: u32 = 0x60000000; +pub const DES1_TX_CTRL_SADDR_NONE: u32 = 0x00000000; +pub const DES1_TX_CTRL_SADDR_INSERT: u32 = 0x20000000; +pub const DES1_TX_CTRL_SADDR_REPLACE: u32 = 0x40000000; +pub const DES1_TX_CTRL_BUFF2_SIZE_M: u32 = 0x1FFF0000; +pub const DES1_TX_CTRL_BUFF1_SIZE_M: u32 = 0x00001FFF; +pub const DES1_TX_CTRL_BUFF2_SIZE_S: u32 = 16; +pub const DES1_TX_CTRL_BUFF1_SIZE_S: u32 = 0; +//***************************************************************************** +// +// Fields found in the DES0 word of the receive descriptor (ui32CtrlStatus in +// tEMACDMADescriptor) +// +//***************************************************************************** +pub const DES0_RX_CTRL_OWN: u32 = 0x80000000; +pub const DES0_RX_STAT_DEST_ADDR_FAIL: u32 = 0x40000000; +pub const DES0_RX_STAT_FRAME_LENGTH_M: u32 = 0x3FFF0000; +pub const DES0_RX_STAT_FRAME_LENGTH_S: u32 = 16; +pub const DES0_RX_STAT_ERR: u32 = 0x00008000; +pub const DES0_RX_STAT_DESCRIPTOR_ERR: u32 = 0x00004000; +pub const DES0_RX_STAT_SRC_ADDR_FAIL: u32 = 0x00002000; +pub const DES0_RX_STAT_LENGTH_ERR: u32 = 0x00001000; +pub const DES0_RX_STAT_OVERFLOW: u32 = 0x00000800; +pub const DES0_RX_STAT_VLAN_TAG: u32 = 0x00000400; +pub const DES0_RX_STAT_FIRST_DESC: u32 = 0x00000200; +pub const DES0_RX_STAT_LAST_DESC: u32 = 0x00000100; +pub const DES0_RX_STAT_TS_AVAILABLE: u32 = 0x00000080; +pub const DES0_RX_STAT_RX_L_COLLISION: u32 = 0x00000040; +pub const DES0_RX_STAT_FRAME_TYPE: u32 = 0x00000020; +pub const DES0_RX_STAT_WDOG_TIMEOUT: u32 = 0x00000010; +pub const DES0_RX_STAT_RX_ERR: u32 = 0x00000008; +pub const DES0_RX_STAT_DRIBBLE_ERR: u32 = 0x00000004; +pub const DES0_RX_STAT_CRC_ERR: u32 = 0x00000002; +pub const DES0_RX_STAT_MAC_ADDR: u32 = 0x00000001; +pub const DES0_RX_STAT_EXT_AVAILABLE: u32 = 0x00000001; +//***************************************************************************** +// +// Fields found in the DES1 word of the receive descriptor (ui32Count in +// tEMACDMADescriptor) +// +//***************************************************************************** +pub const DES1_RX_CTRL_DISABLE_INT: u32 = 0x80000000; +pub const DES1_RX_CTRL_BUFF2_SIZE_M: u32 = 0x1FFF0000; +pub const DES1_RX_CTRL_BUFF2_SIZE_S: u32 = 16; +pub const DES1_RX_CTRL_END_OF_RING: u32 = 0x00008000; +pub const DES1_RX_CTRL_CHAINED: u32 = 0x00004000; +pub const DES1_RX_CTRL_BUFF1_SIZE_M: u32 = 0x00001FFF; +pub const DES1_RX_CTRL_BUFF1_SIZE_S: u32 = 0; +//***************************************************************************** +// +// Fields found in the DES4 word of the receive descriptor (ui32ExtRxStatus in +// tEMACDMADescriptor) +// +//***************************************************************************** +pub const DES4_RX_STAT_TS_DROPPED: u32 = 0x00004000; +pub const DES4_RX_STAT_PTP_VERSION2: u32 = 0x00002000; +pub const DES4_RX_STAT_PTP_TYPE_ETH: u32 = 0x00001000; +pub const DES4_RX_STAT_PTP_TYPE_UDP: u32 = 0x00000000; +pub const DES4_RX_STAT_PTP_MT_M: u32 = 0x00000F00; +pub const DES4_RX_STAT_PTP_MT_NONE: u32 = 0x00000000; +pub const DES4_RX_STAT_PTP_MT_SYNC: u32 = 0x00000100; +pub const DES4_RX_STAT_PTP_MT_FOLLOW_UP: u32 = 0x00000200; +pub const DES4_RX_STAT_PTP_MT_DELAY_REQ: u32 = 0x00000300; +pub const DES4_RX_STAT_PTP_MT_DELAY_RESP: u32 = 0x00000400; +pub const DES4_RX_STAT_PTP_MT_PDELAY_REQ: u32 = 0x00000500; +pub const DES4_RX_STAT_PTP_MT_PDELAY_RESP: u32 = 0x00000600; +pub const DES4_RX_STAT_PTP_MT_PDELAY_RFU: u32 = 0x00000700; +pub const DES4_RX_STAT_PTP_MT_ANNOUNCE: u32 = 0x00000800; +pub const DES4_RX_STAT_PTP_MT_SIGNALLING: u32 = 0x00000A00; +pub const DES4_RX_STAT_PTP_MT_RESERVED: u32 = 0x00000F00; +pub const DES4_RX_STAT_IPV6: u32 = 0x00000080; +pub const DES4_RX_STAT_IPV4: u32 = 0x00000040; +pub const DES4_RX_STAT_IP_CHK_BYPASSED: u32 = 0x00000020; +pub const DES4_RX_STAT_IP_PAYLOAD_ERR: u32 = 0x00000010; +pub const DES4_RX_STAT_IP_HEADER_ERR: u32 = 0x00000008; +pub const DES4_RX_STAT_PAYLOAD_M: u32 = 0x00000007; +pub const DES4_RX_STAT_PAYLOAD_UNKNOWN: u32 = 0x00000000; +pub const DES4_RX_STAT_PAYLOAD_UDP: u32 = 0x00000001; +pub const DES4_RX_STAT_PAYLOAD_TCP: u32 = 0x00000002; +pub const DES4_RX_STAT_PAYLOAD_ICMP: u32 = 0x00000003; +//***************************************************************************** +// +// Values used in the ui32BusConfig parameter to EMACInit(). +// +//*************************************************************************** +pub const EMAC_BCONFIG_DMA_PRIO_WEIGHT_M: u32 = 0x30000000; +pub const EMAC_BCONFIG_DMA_PRIO_WEIGHT_1: u32 = 0x00000000; +pub const EMAC_BCONFIG_DMA_PRIO_WEIGHT_2: u32 = 0x10000000; +pub const EMAC_BCONFIG_DMA_PRIO_WEIGHT_3: u32 = 0x20000000; +pub const EMAC_BCONFIG_DMA_PRIO_WEIGHT_4: u32 = 0x30000000; +pub const EMAC_BCONFIG_TX_PRIORITY: u32 = 0x08000000; +pub const EMAC_BCONFIG_ADDR_ALIGNED: u32 = 0x02000000; +pub const EMAC_BCONFIG_PRIORITY_M: u32 = 0x0000C000; +pub const EMAC_BCONFIG_PRIORITY_1_1: u32 = 0x0<<14; +pub const EMAC_BCONFIG_PRIORITY_2_1: u32 = 0x1<<14; +pub const EMAC_BCONFIG_PRIORITY_3_1: u32 = 0x2<<14; +pub const EMAC_BCONFIG_PRIORITY_4_1: u32 = 0x3<<14; +pub const EMAC_BCONFIG_PRIORITY_FIXED: u32 = 0x00000002; +pub const EMAC_BCONFIG_FIXED_BURST: u32 = 0x00010000; +pub const EMAC_BCONFIG_MIXED_BURST: u32 = 0x04000000; +//***************************************************************************** +// +// Options used in the ui32Config parameter to EMACPHYConfigSet(). +// +//***************************************************************************** +pub const EMAC_PHY_TYPE_INTERNAL: u32 = 0x00000000; +pub const EMAC_PHY_TYPE_EXTERNAL_MII: u32 = 0x80000000; +pub const EMAC_PHY_TYPE_EXTERNAL_RMII: u32 = 0xC0000000; +pub const EMAC_PHY_INT_NIB_TXERR_DET_DIS: u32 = 0x01000000; +pub const EMAC_PHY_INT_RX_ER_DURING_IDLE: u32 = 0x00800000; +pub const EMAC_PHY_INT_ISOLATE_MII_LLOSS: u32 = 0x00400000; +pub const EMAC_PHY_INT_LINK_LOSS_RECOVERY: u32 = 0x00200000; +pub const EMAC_PHY_INT_TDRRUN: u32 = 0x00100000; +pub const EMAC_PHY_INT_LD_ON_RX_ERR_COUNT: u32 = 0x00040000; +pub const EMAC_PHY_INT_LD_ON_MTL3_ERR_COUNT: u32 = 0x00020000; +pub const EMAC_PHY_INT_LD_ON_LOW_SNR: u32 = 0x00010000; +pub const EMAC_PHY_INT_LD_ON_SIGNAL_ENERGY: u32 = 0x00008000; +pub const EMAC_PHY_INT_POLARITY_SWAP: u32 = 0x00004000; +pub const EMAC_PHY_INT_MDI_SWAP: u32 = 0x00002000; +pub const EMAC_PHY_INT_ROBUST_MDIX: u32 = 0x00001000; +pub const EMAC_PHY_INT_FAST_MDIX: u32 = 0x00000800; +pub const EMAC_PHY_INT_MDIX_EN: u32 = 0x00000400; +pub const EMAC_PHY_INT_FAST_RXDV_DETECT: u32 = 0x00000200; +pub const EMAC_PHY_INT_FAST_L_UP_DETECT: u32 = 0x00000100; +pub const EMAC_PHY_INT_EXT_FULL_DUPLEX: u32 = 0x00000080; +pub const EMAC_PHY_INT_FAST_AN_80_50_35: u32 = 0x00000040; +pub const EMAC_PHY_INT_FAST_AN_120_75_50: u32 = 0x00000050; +pub const EMAC_PHY_INT_FAST_AN_140_150_100: u32 = 0x00000060; +pub const EMAC_PHY_FORCE_10B_T_HALF_DUPLEX: u32 = 0x00000000; +pub const EMAC_PHY_FORCE_10B_T_FULL_DUPLEX: u32 = 0x00000002; +pub const EMAC_PHY_FORCE_100B_T_HALF_DUPLEX: u32 = 0x00000004; +pub const EMAC_PHY_FORCE_100B_T_FULL_DUPLEX: u32 = 0x00000006; +pub const EMAC_PHY_AN_10B_T_HALF_DUPLEX: u32 = 0x00000008; +pub const EMAC_PHY_AN_10B_T_FULL_DUPLEX: u32 = 0x0000000A; +pub const EMAC_PHY_AN_100B_T_HALF_DUPLEX: u32 = 0x0000000C; +pub const EMAC_PHY_AN_100B_T_FULL_DUPLEX: u32 = 0x0000000E; +pub const EMAC_PHY_INT_HOLD: u32 = 0x00000001; +pub const EMAC_PHY_TYPE_MASK: u32 = 0xC0000000; +//***************************************************************************** +// +// Options used in the ui32Config parameter to EMACConfigSet(). +// +//***************************************************************************** +pub const EMAC_CONFIG_USE_MACADDR1: u32 = 0x40000000; +pub const EMAC_CONFIG_USE_MACADDR0: u32 = 0x00000000; +pub const EMAC_CONFIG_SA_FROM_DESCRIPTOR: u32 = 0x00000000; +pub const EMAC_CONFIG_SA_INSERT: u32 = 0x20000000; +pub const EMAC_CONFIG_SA_REPLACE: u32 = 0x30000000; +pub const EMAC_CONFIG_2K_PACKETS: u32 = 0x08000000; +pub const EMAC_CONFIG_STRIP_CRC: u32 = 0x02000000; +pub const EMAC_CONFIG_JABBER_DISABLE: u32 = 0x00400000; +pub const EMAC_CONFIG_JUMBO_ENABLE: u32 = 0x00100000; +pub const EMAC_CONFIG_IF_GAP_MASK: u32 = 0x000E0000; +pub const EMAC_CONFIG_IF_GAP_96BITS: u32 = 0x0<<17; +pub const EMAC_CONFIG_IF_GAP_88BITS: u32 = 0x1<<17; +pub const EMAC_CONFIG_IF_GAP_80BITS: u32 = 0x2<<17; +pub const EMAC_CONFIG_IF_GAP_72BITS: u32 = 0x3<<17; +pub const EMAC_CONFIG_IF_GAP_64BITS: u32 = 0x4<<17; +pub const EMAC_CONFIG_IF_GAP_56BITS: u32 = 0x5<<17; +pub const EMAC_CONFIG_IF_GAP_48BITS: u32 = 0x6<<17; +pub const EMAC_CONFIG_IF_GAP_40BITS: u32 = 0x7<<17; +pub const EMAC_CONFIG_CS_DISABLE: u32 = 0x00010000; +pub const EMAC_CONFIG_100MBPS: u32 = 0x00004000; +pub const EMAC_CONFIG_10MBPS: u32 = 0x00000000; +pub const EMAC_CONFIG_RX_OWN_DISABLE: u32 = 0x00002000; +pub const EMAC_CONFIG_LOOPBACK: u32 = 0x00001000; +pub const EMAC_CONFIG_FULL_DUPLEX: u32 = 0x00000800; +pub const EMAC_CONFIG_HALF_DUPLEX: u32 = 0x00000000; +pub const EMAC_CONFIG_CHECKSUM_OFFLOAD: u32 = 0x00000400; +pub const EMAC_CONFIG_RETRY_DISABLE: u32 = 0x00000200; +pub const EMAC_CONFIG_AUTO_CRC_STRIPPING: u32 = 0x00000080; +pub const EMAC_CONFIG_BO_MASK: u32 = 0x00000060; +pub const EMAC_CONFIG_BO_LIMIT_1024: u32 = 0x0<<5; +pub const EMAC_CONFIG_BO_LIMIT_256: u32 = 0x1<<5; +pub const EMAC_CONFIG_BO_LIMIT_16: u32 = 0x2<<5; +pub const EMAC_CONFIG_BO_LIMIT_2: u32 = 0x3<<5; +pub const EMAC_CONFIG_DEFERRAL_CHK_ENABLE: u32 = 0x00000010; +pub const EMAC_CONFIG_PREAMBLE_MASK: u32 = 0x00000003; +pub const EMAC_CONFIG_7BYTE_PREAMBLE: u32 = 0x00000000; +pub const EMAC_CONFIG_5BYTE_PREAMBLE: u32 = 0x00000001; +pub const EMAC_CONFIG_3BYTE_PREAMBLE: u32 = 0x00000002; +//***************************************************************************** +// +// Options used in the ui32ModeFlags parameter to EMACConfigSet(). +// +//***************************************************************************** +pub const EMAC_MODE_KEEP_BAD_CRC: u32 = 0x04000000; +pub const EMAC_MODE_RX_STORE_FORWARD: u32 = 0x02000000; +pub const EMAC_MODE_RX_FLUSH_DISABLE: u32 = 0x01000000; +pub const EMAC_MODE_TX_STORE_FORWARD: u32 = 0x00200000; +pub const EMAC_MODE_TX_THRESHOLD_16_BYTES: u32 = 7<<14; +pub const EMAC_MODE_TX_THRESHOLD_24_BYTES: u32 = 6<<14; +pub const EMAC_MODE_TX_THRESHOLD_32_BYTES: u32 = 5<<14; +pub const EMAC_MODE_TX_THRESHOLD_40_BYTES: u32 = 4<<14; +pub const EMAC_MODE_TX_THRESHOLD_64_BYTES: u32 = 0<<14; +pub const EMAC_MODE_TX_THRESHOLD_128_BYTES: u32 = 1<<14; +pub const EMAC_MODE_TX_THRESHOLD_192_BYTES: u32 = 2<<14; +pub const EMAC_MODE_TX_THRESHOLD_256_BYTES: u32 = 3<<14; +pub const EMAC_MODE_RX_ERROR_FRAMES: u32 = 0x00000080; +pub const EMAC_MODE_RX_UNDERSIZED_FRAMES: u32 = 0x00000040; +pub const EMAC_MODE_RX_THRESHOLD_64_BYTES: u32 = 0<<3; +pub const EMAC_MODE_RX_THRESHOLD_32_BYTES: u32 = 1<<3; +pub const EMAC_MODE_RX_THRESHOLD_96_BYTES: u32 = 2<<3; +pub const EMAC_MODE_RX_THRESHOLD_128_BYTES: u32 =3<<3; +pub const EMAC_MODE_OPERATE_2ND_FRAME: u32 = 0x00000002; +//***************************************************************************** +// +// These two values may be returned by EMACConfigGet() in the *pui32Config +// parameter. The transmitter and receiver are, however, enabled and disabled +// using independent functions, EMACTxEnable/Disable() and +// EMACRxEnable/Disable(). +// +//***************************************************************************** +pub const EMAC_CONFIG_TX_ENABLED: u32 = 0x00000008; +pub const EMAC_CONFIG_RX_ENABLED: u32 = 0x00000004; +//***************************************************************************** +// +// These two values may be returned by EMACConfigGet() in the *pui32Mode +// parameter. The transmit and receive DMA channels are, however, enabled and +// disabled using independent functions, EMACTxEnable/Disable() and +// EMACRxEnable/Disable(). +// +//***************************************************************************** +pub const EMAC_MODE_TX_DMA_ENABLED: u32 = 0x00002000; +pub const EMAC_MODE_RX_DMA_ENABLED: u32 = 0x00000002; +//***************************************************************************** +// +// These values may be passed to EMACFrameFilterSet() in the ui32FilterOpts +// parameter, and are returned by EMACFrameFilterGet(). +// +//***************************************************************************** +pub const EMAC_FRMFILTER_RX_ALL: u32 = 0x80000000; +pub const EMAC_FRMFILTER_VLAN: u32 = 0x00010000; +pub const EMAC_FRMFILTER_HASH_AND_PERFECT: u32 = 0x00000400; +pub const EMAC_FRMFILTER_SADDR: u32 = 0x00000200; +pub const EMAC_FRMFILTER_INV_SADDR: u32 = 0x00000100; +pub const EMAC_FRMFILTER_PASS_MASK: u32 = 0x03<<6; +pub const EMAC_FRMFILTER_PASS_NO_CTRL: u32 = 0x00<<6; +pub const EMAC_FRMFILTER_PASS_NO_PAUSE: u32 = 0x01<<6; +pub const EMAC_FRMFILTER_PASS_ALL_CTRL: u32 = 0x02<<6; +pub const EMAC_FRMFILTER_PASS_ADDR_CTRL: u32 = 0x03<<6; +pub const EMAC_FRMFILTER_BROADCAST: u32 = 0x00000020; +pub const EMAC_FRMFILTER_PASS_MULTICAST: u32 = 0x00000010; +pub const EMAC_FRMFILTER_INV_DADDR: u32 = 0x00000008; +pub const EMAC_FRMFILTER_HASH_MULTICAST: u32 = 0x00000004; +pub const EMAC_FRMFILTER_HASH_UNICAST: u32 = 0x00000002; +pub const EMAC_FRMFILTER_PROMISCUOUS: u32 = 0x00000001; +//***************************************************************************** +// +// Values which may be returned by EMACStatusGet(). +// +//***************************************************************************** +pub const EMAC_STATUS_TX_NOT_EMPTY: u32 = 0x01000000; +pub const EMAC_STATUS_TX_WRITING_FIFO: u32 = 0x00400000; +pub const EMAC_STATUS_TRC_STATE_MASK: u32 = 0x00300000; +pub const EMAC_STATUS_TRC_STATE_IDLE: u32 = 0x00<<20; +pub const EMAC_STATUS_TRC_STATE_READING: u32 = 0x01<<20; +pub const EMAC_STATUS_TRC_STATE_WAITING: u32 = 0x02<<20; +pub const EMAC_STATUS_TRC_STATE_STATUS: u32 = 0x03<<20; +pub const EMAC_STATUS_TX_PAUSED: u32 = 0x00080000; +pub const EMAC_STATUS_TFC_STATE_MASK: u32 = 0x00060000; +pub const EMAC_STATUS_TFC_STATE_IDLE: u32 = 0x00<<17; +pub const EMAC_STATUS_TFC_STATE_WAITING: u32 = 0x01<<17; +pub const EMAC_STATUS_TFC_STATE_PAUSING: u32 = 0x02<<17; +pub const EMAC_STATUS_TFC_STATE_WRITING: u32 = 0x03<<17; +pub const EMAC_STATUS_MAC_NOT_IDLE: u32 = 0x00010000; +pub const EMAC_STATUS_RX_FIFO_LEVEL_MASK: u32 = 0x00000300; +pub const EMAC_STATUS_RX_FIFO_EMPTY: u32 = 0x00<<8; +pub const EMAC_STATUS_RX_FIFO_BELOW: u32 = 0x01<<8; +pub const EMAC_STATUS_RX_FIFO_ABOVE: u32 = 0x02<<8; +pub const EMAC_STATUS_RX_FIFO_FULL: u32 = 0x03<<8; +pub const EMAC_STATUS_RX_FIFO_STATE_MASK: u32 = 0x00000060; +pub const EMAC_STATUS_RX_FIFO_IDLE: u32 = 0x00<<5; +pub const EMAC_STATUS_RX_FIFO_READING: u32 = 0x01<<5; +pub const EMAC_STATUS_RX_FIFO_STATUS: u32 = 0x02<<5; +pub const EMAC_STATUS_RX_FIFO_FLUSHING: u32 = 0x03<<5; +pub const EMAC_STATUS_RWC_ACTIVE: u32 = 0x00000010; +pub const EMAC_STATUS_RPE_ACTIVE: u32 = 0x00000001; +//***************************************************************************** +// +// Values which may be returned by EMACDMAStateGet(). +// +//***************************************************************************** +pub const EMAC_DMA_TXSTAT_MASK: u32 = 0x07<<20; +pub const EMAC_DMA_TXSTAT_STOPPED: u32 = 0x00<<20; +pub const EMAC_DMA_TXSTAT_RUN_FETCH_DESC: u32 = 0x01<<20; +pub const EMAC_DMA_TXSTAT_RUN_WAIT_STATUS: u32 = 0x02<<20; +pub const EMAC_DMA_TXSTAT_RUN_READING: u32 = 0x03<<20; +pub const EMAC_DMA_TXSTAT_RUN_CLOSE_DESC: u32 = 0x07<<20; +pub const EMAC_DMA_TXSTAT_TS_WRITE: u32 = 0x04<<20; +pub const EMAC_DMA_TXSTAT_SUSPENDED: u32 = 0x06<<20; + +pub const EMAC_DMA_RXSTAT_MASK: u32 = 0x07<<17; +pub const EMAC_DMA_RXSTAT_STOPPED: u32 = 0x00<<17; +pub const EMAC_DMA_RXSTAT_RUN_FETCH_DESC: u32 = 0x01<<17; +pub const EMAC_DMA_RXSTAT_RUN_WAIT_PACKET: u32 = 0x03<<17; +pub const EMAC_DMA_RXSTAT_SUSPENDED: u32 = 0x04<<17; +pub const EMAC_DMA_RXSTAT_RUN_CLOSE_DESC: u32 = 0x05<<17; +pub const EMAC_DMA_RXSTAT_TS_WRITE: u32 = 0x06<<17; +pub const EMAC_DMA_RXSTAT_RUN_RECEIVING: u32 = 0x07<<17; + +pub const EMAC_DMA_ERROR: u32 = 0x00002000; +pub const EMAC_DMA_ERR_MASK: u32 = 0x03800000; +pub const EMAC_DMA_ERR_RX_DATA_WRITE: u32 = 0x00000000; +pub const EMAC_DMA_ERR_TX_DATA_READ: u32 = 0x01800000; +pub const EMAC_DMA_ERR_RX_DESC_WRITE: u32 = 0x02000000; +pub const EMAC_DMA_ERR_TX_DESC_WRITE: u32 = 0x02800000; +pub const EMAC_DMA_ERR_RX_DESC_READ: u32 = 0x03000000; +pub const EMAC_DMA_ERR_TX_DESC_READ: u32 = 0x03800000; +//***************************************************************************** +// +// Values which may be ORed together in the ui32Config parameter passed to +// EMACAddrFilterSet and which may be returned by EMACAddrFilterGet. +// +//***************************************************************************** +pub const EMAC_FILTER_ADDR_ENABLE: u32 = 0x80000000; +pub const EMAC_FILTER_SOURCE_ADDR: u32 = 0x40000000; +pub const EMAC_FILTER_MASK_BYTE_6: u32 = 0x20000000; +pub const EMAC_FILTER_MASK_BYTE_5: u32 = 0x10000000; +pub const EMAC_FILTER_MASK_BYTE_4: u32 = 0x08000000; +pub const EMAC_FILTER_MASK_BYTE_3: u32 = 0x04000000; +pub const EMAC_FILTER_MASK_BYTE_2: u32 = 0x03000000; +pub const EMAC_FILTER_MASK_BYTE_1: u32 = 0x01000000; +pub const EMAC_FILTER_BYTE_MASK_M: u32 = 0x3F000000; +pub const EMAC_FILTER_BYTE_MASK_S: u32 = 24; +//***************************************************************************** +// +// Flags passed to EMACTimestampConfigSet or returned from +// EMACTimestampConfigGet. +// +//***************************************************************************** +pub const EMAC_TS_MAC_FILTER_ENABLE: u32 = 0x00040000; +pub const EMAC_TS_MAC_FILTER_DISABLE: u32 = 0x00000000; +pub const EMAC_TS_SYNC_FOLLOW_DREQ_DRESP: u32 = 0x00000000; +pub const EMAC_TS_SYNC_ONLY: u32 = 0x00004000; +pub const EMAC_TS_DELAYREQ_ONLY: u32 = 0x0000C000; +pub const EMAC_TS_ALL: u32 = 0x00010000; +pub const EMAC_TS_SYNC_PDREQ_PDRESP: u32 = 0x00014000; +pub const EMAC_TS_DREQ_PDREQ_PDRESP: u32 = 0x0001C000; +pub const EMAC_TS_SYNC_DELAYREQ: u32 = 0x00020000; +pub const EMAC_TS_PDREQ_PDRESP: u32 = 0x00030000; +pub const EMAC_TS_PROCESS_IPV4_UDP: u32 = 0x00002000; +pub const EMAC_TS_PROCESS_IPV6_UDP: u32 = 0x00001000; +pub const EMAC_TS_PROCESS_ETHERNET: u32 = 0x00000800; +pub const EMAC_TS_PTP_VERSION_2: u32 = 0x00000400; +pub const EMAC_TS_PTP_VERSION_1: u32 = 0x00000000; +pub const EMAC_TS_DIGITAL_ROLLOVER: u32 = 0x00000200; +pub const EMAC_TS_BINARY_ROLLOVER: u32 = 0x00000000; +pub const EMAC_TS_ALL_RX_FRAMES: u32 = 0x00000100; +pub const EMAC_TS_UPDATE_FINE: u32 = 0x00000002; +pub const EMAC_TS_UPDATE_COARSE: u32 = 0x00000000; +//***************************************************************************** +// +// Some register bit definitions relating to external PHYs. These are not +// relevant (or available) when using the internal Ethernet PHY but having +// the definitions here helps when using an external MII or RMII PHY. +// +//***************************************************************************** +pub const EPHY_SCR_INPOL_EXT: u32 = 0x00000008; +pub const EPHY_SCR_TINT_EXT: u32 = 0x00000004; +pub const EPHY_SCR_INTEN_EXT: u32 = 0x00000002; +pub const EPHY_SCR_INTOE_EXT: u32 = 0x00000001; +//***************************************************************************** +// +// These interrupt sources may be passed to EMACIntEnable() and +// EMACIntDisable() to enable or disable various Ethernet interrupt sources. +// +//***************************************************************************** +// +// Note that interrupts relating to timestamping and power management must be +// independently enabled via calls to functions EMACTimestampTargetIntEnable +// and EMACPowerManagementControlSet. +// +// EMAC_INT_PHY is deliberately set to a reserved bit in the MAC interrupt +// register. We handle the fact that the PHY interrupt is controlled via an +// independent register within the code. If we didn't do this, the app would +// have to enable the MAC interrupt then enable the PHY interrupt via a +// different API (since they share a vector). To further complicate matters, +// they would have to call EMACIntStatus() and then, if it returned 0, +// read the PHY interrupt status to see that it fired. This would be nasty +// and unfriendly so we hide it inside DriverLib. +// +//***************************************************************************** +pub const EMAC_INT_PHY: u32 = 0x80000000; +pub const EMAC_INT_EARLY_RECEIVE: u32 = 0x00004000; +pub const EMAC_INT_BUS_ERROR: u32 = 0x00002000; +pub const EMAC_INT_EARLY_TRANSMIT: u32 = 0x00000400; +pub const EMAC_INT_RX_WATCHDOG: u32 = 0x00000200; +pub const EMAC_INT_RX_STOPPED: u32 = 0x00000100; +pub const EMAC_INT_RX_NO_BUFFER: u32 = 0x00000080; +pub const EMAC_INT_RECEIVE: u32 = 0x00000040; +pub const EMAC_INT_TX_UNDERFLOW: u32 = 0x00000020; +pub const EMAC_INT_RX_OVERFLOW: u32 = 0x00000010; +pub const EMAC_INT_TX_JABBER: u32 = 0x00000008; +pub const EMAC_INT_TX_NO_BUFFER: u32 = 0x00000004; +pub const EMAC_INT_TX_STOPPED: u32 = 0x00000002; +pub const EMAC_INT_TRANSMIT: u32 = 0x00000001; +// +// These interrupt sources are summary indicators. They are readable +// using EMACIntStatus() and must be cleared using EMACIntClear(). They +// may be enabled or disabled independently of the group of interrupts that +// they are derived from but offer merely a simple way to be informed of a +// normal or abnormal condition requiring software attention. +// +// EMAC_INT_NORMAL_INT is the logical OR of the masked state of +// EMAC_INT_TRANSMIT | EMAC_INT_RECEIVE | EMAC_INT_TX_NO_BUFFER | +// EMAC_INT_EARLY_RECEIVE. +// +// EMAC_INT_ABNORMAL_INT is the logical OR of the masked state of +// EMAC_INT_TX_STOPPED | EMAC_INT_TX_JABBER | EMAC_INT_RX_OVERFLOW | +// EMAC_INT_TX_UNDERFLOW | EMAC_INT_RX_NO_BUFFER | EMAC_INT_RX_STOPPED | +// EMAC_INT_RX_WATCHDOG | EMAC_INT_EARLY_TRANSMIT | EMAC_INT_BUS_ERROR. +// +pub const EMAC_INT_NORMAL_INT: u32 = 0x00010000; +pub const EMAC_INT_ABNORMAL_INT: u32 = 0x00008000; +// +// This interrupt source is readable using EMACIntStatus but must +// be cleared by calling the EMACEEEStatus(). +// +pub const EMAC_INT_LPI: u32 = 0x40000000; +// +// This interrupt source is readable using EMACIntStatus but must +// be cleared by calling the EMACTimestampIntStatus(). +// +pub const EMAC_INT_TIMESTAMP: u32 = 0x20000000; +// +// Interrupt sources which may be returned from EMACTimestampIntStatus(). +// +pub const EMAC_TS_INT_TARGET_REACHED: u32 = 0x00000002; +pub const EMAC_TS_INT_TS_SEC_OVERFLOW: u32 = 0x00000001; +// +// This interrupt source is readable using EMACIntStatus but must +// be cleared by calling EMACPowerManagementStatusGet(). +// +pub const EMAC_INT_POWER_MGMNT: u32 = 0x10000000; +//***************************************************************************** +// +// Configuration flags that may be passed in the ui32FreqConfig parameter to +// EMACTimestampPPSSimpleModeSet(). +// +//***************************************************************************** +pub const EMAC_PPS_SINGLE_PULSE: u32 = 0x00000000; +pub const EMAC_PPS_1HZ: u32 = 0x00000001; +pub const EMAC_PPS_2HZ: u32 = 0x00000002; +pub const EMAC_PPS_4HZ: u32 = 0x00000003; +pub const EMAC_PPS_8HZ: u32 = 0x00000004; +pub const EMAC_PPS_16HZ: u32 = 0x00000005; +pub const EMAC_PPS_32HZ: u32 = 0x00000006; +pub const EMAC_PPS_64HZ: u32 = 0x00000007; +pub const EMAC_PPS_128HZ: u32 = 0x00000008; +pub const EMAC_PPS_256HZ: u32 = 0x00000009; +pub const EMAC_PPS_512HZ: u32 = 0x0000000A; +pub const EMAC_PPS_1024HZ: u32 = 0x0000000B; +pub const EMAC_PPS_2048HZ: u32 = 0x0000000C; +pub const EMAC_PPS_4096HZ: u32 = 0x0000000D; +pub const EMAC_PPS_8192HZ: u32 = 0x0000000E; +pub const EMAC_PPS_16384HZ: u32 = 0x0000000F; +pub const EMAC_PPS_32768HZ: u32 = 0x00000010; +//***************************************************************************** +// +// Configuration flags that may be passed in the ui32Config parameter to +// EMACTimestampPPSCommandModeSet(). +// +//***************************************************************************** +pub const EMAC_PPS_TARGET_INT: u32 = 0x00000000; +pub const EMAC_PPS_TARGET_PPS: u32 = 0x00000060; +pub const EMAC_PPS_TARGET_BOTH: u32 = 0x00000040; +//***************************************************************************** +// +// Commands which may be passed to EMACTimestampPPSCmd. +// +//***************************************************************************** +pub const EMAC_PPS_COMMAND_NONE: u32 = 0x00; +pub const EMAC_PPS_COMMAND_START_SINGLE: u32 = 0x01; +pub const EMAC_PPS_COMMAND_START_TRAIN: u32 = 0x02; +pub const EMAC_PPS_COMMAND_CANCEL_START: u32 = 0x03; +pub const EMAC_PPS_COMMAND_STOP_AT_TIME: u32 = 0x04; +pub const EMAC_PPS_COMMAND_STOP_NOW: u32 = 0x05; +pub const EMAC_PPS_COMMAND_CANCEL_STOP: u32 = 0x06; +//***************************************************************************** +// +// Values which may be passed to EMACVLANRxConfigSet in the ui32Config +// parameter and which may be returned from EMACVLANRxConfigGet. +// +//***************************************************************************** +pub const EMAC_VLAN_RX_HASH_ENABLE: u32 = 0x00080000; +pub const EMAC_VLAN_RX_HASH_DISABLE: u32 = 0x00000000; +pub const EMAC_VLAN_RX_SVLAN_ENABLE: u32 = 0x00040000; +pub const EMAC_VLAN_RX_SVLAN_DISABLE: u32 = 0x00000000; +pub const EMAC_VLAN_RX_NORMAL_MATCH: u32 = 0x00000000; +pub const EMAC_VLAN_RX_INVERSE_MATCH: u32 = 0x00020000; +pub const EMAC_VLAN_RX_12BIT_TAG: u32 = 0x00010000; +pub const EMAC_VLAN_RX_16BIT_TAG: u32 = 0x00000000; +//***************************************************************************** +// +// Values which may be passed to EMACVLANTxConfigSet in the ui32Config +// parameter and which may be returned from EMACVLANTxConfigGet. +// +//***************************************************************************** +pub const EMAC_VLAN_TX_CVLAN: u32 = 0x00000000; +pub const EMAC_VLAN_TX_SVLAN: u32 = 0x00080000; +pub const EMAC_VLAN_TX_USE_VLC: u32 = 0x00040000; +pub const EMAC_VLAN_TX_VLC_NONE: u32 = 0x00000000; +pub const EMAC_VLAN_TX_VLC_DELETE: u32 = 0x00010000; +pub const EMAC_VLAN_TX_VLC_INSERT: u32 = 0x00020000; +pub const EMAC_VLAN_TX_VLC_REPLACE: u32 = 0x00030000; +pub const EMAC_VLAN_TX_VLC_MASK: u32 = 0x00030000; +pub const EMAC_RWU_FILTER_ENABLE: u32 = 1; +pub const EMAC_RWU_FILTER_DISABLE: u32 = 0; +pub const EMAC_RWU_FILTER_MULTICAST: u32 = 8; +pub const EMAC_RWU_FILTER_UNICAST: u32 = 0; +//***************************************************************************** +// +// The following structure fields must be packed. +// +//***************************************************************************** +//***************************************************************************** +// +// This structure defines up to 4 filters that can be used to define specific +// frames which will cause the MAC to wake up from sleep mode. +// +//***************************************************************************** + // + // A byte mask for each filter defining which bytes from a sequence of + // 31 (bit 31 must be clear in each mask) are used to filter incoming + // packets. A 1 indicates that the relevant byte is used to update the + // CRC16 for the filter, a 0 indicates that the byte is ignored. + // + // + // Defines whether each filter is enabled and, if so, whether it filters + // multicast or unicast frames. Valid values are one of + // EMAC_RWU_FILTER_ENABLE or EMAC_RWU_FILTER_DISABLE ORed with one of + // EMAC_RWU_FILTER_UNICAST or EMAC_RWU_FILTER_MULTICAST. + // + // + // Determines the byte offset within the frame at which the filter starts + // examining bytes. The minimum value for each offset is 12. The first + // byte of a frame is offset 0. + // + // + // The CRC16 value that is expected for each filter if it passes. The + // CRC is calculated using all bytes indicated by the filter's mask. + // +//***************************************************************************** +// +// Turn off structure packing again. +// +//***************************************************************************** +//***************************************************************************** +// +// Values which may be ORed together and used in the ui32Flags parameter to +// EMACPowerManagementControlSet. These may also returned be from a call to +// EMACPowerManagementControlGet. +// +//***************************************************************************** +pub const EMAC_PMT_GLOBAL_UNICAST_ENABLE: u32 = 0x00000200; +pub const EMAC_PMT_WAKEUP_PACKET_ENABLE: u32 = 0x00000004; +pub const EMAC_PMT_MAGIC_PACKET_ENABLE: u32 = 0x00000002; +pub const EMAC_PMT_POWER_DOWN: u32 = 0x00000001; +//***************************************************************************** +// +// Values which may be ORed together and returned from a call to +// EMACPowerManagementStatusGet. This call will also return +// EMAC_PMT_POWER_DOWN if the MAC is in power-down mode. +// +//***************************************************************************** +pub const EMAC_PMT_WAKEUP_PACKET_RECEIVED: u32 = 0x00000040; +pub const EMAC_PMT_MAGIC_PACKET_RECEIVED: u32 = 0x00000020; +//***************************************************************************** +// +// Close the Doxygen group. +// @} +// +//***************************************************************************** +//***************************************************************************** +// +// Public function prototypes. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// epi.h - Prototypes and macros for the EPI module. +// +// Copyright (c) 2008-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Values that can be passed to EPIModeSet() +// +//***************************************************************************** +pub const EPI_MODE_GENERAL: u32 = 0x00000010; +pub const EPI_MODE_SDRAM: u32 = 0x00000011; +pub const EPI_MODE_HB8: u32 = 0x00000012; +pub const EPI_MODE_HB16: u32 = 0x00000013; +pub const EPI_MODE_DISABLE: u32 = 0x00000000; +//***************************************************************************** +// +// Values that can be passed to EPIConfigSDRAMSet() +// +//***************************************************************************** +pub const EPI_SDRAM_CORE_FREQ_0_15: u32 = 0x00000000; +pub const EPI_SDRAM_CORE_FREQ_15_30: u32 = 0x40000000; +pub const EPI_SDRAM_CORE_FREQ_30_50: u32 = 0x80000000; +pub const EPI_SDRAM_CORE_FREQ_50_100: u32 = 0xC0000000; +pub const EPI_SDRAM_LOW_POWER: u32 = 0x00000200; +pub const EPI_SDRAM_FULL_POWER: u32 = 0x00000000; +pub const EPI_SDRAM_SIZE_64MBIT: u32 = 0x00000000; +pub const EPI_SDRAM_SIZE_128MBIT: u32 = 0x00000001; +pub const EPI_SDRAM_SIZE_256MBIT: u32 = 0x00000002; +pub const EPI_SDRAM_SIZE_512MBIT: u32 = 0x00000003; +//***************************************************************************** +// +// Values that can be passed to EPIConfigGPModeSet() +// +//***************************************************************************** +pub const EPI_GPMODE_CLKPIN: u32 = 0x80000000; +pub const EPI_GPMODE_CLKGATE: u32 = 0x40000000; +pub const EPI_GPMODE_FRAME50: u32 = 0x04000000; +pub const EPI_GPMODE_WRITE2CYCLE: u32 = 0x00080000; +pub const EPI_GPMODE_ASIZE_NONE: u32 = 0x00000000; +pub const EPI_GPMODE_ASIZE_4: u32 = 0x00000010; +pub const EPI_GPMODE_ASIZE_12: u32 = 0x00000020; +pub const EPI_GPMODE_ASIZE_20: u32 = 0x00000030; +pub const EPI_GPMODE_DSIZE_8: u32 = 0x00000000; +pub const EPI_GPMODE_DSIZE_16: u32 = 0x00000001; +pub const EPI_GPMODE_DSIZE_24: u32 = 0x00000002; +pub const EPI_GPMODE_DSIZE_32: u32 = 0x00000003; +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB8ModeSet() +// +//***************************************************************************** +pub const EPI_HB8_USE_TXEMPTY: u32 = 0x00800000; +pub const EPI_HB8_USE_RXFULL: u32 = 0x00400000; +pub const EPI_HB8_WRHIGH: u32 = 0x00200000; +pub const EPI_HB8_RDHIGH: u32 = 0x00100000; +pub const EPI_HB8_ALE_HIGH: u32 = 0x00080000; +pub const EPI_HB8_ALE_LOW: u32 = 0x00000000; +pub const EPI_HB8_WRWAIT_0: u32 = 0x00000000; +pub const EPI_HB8_WRWAIT_1: u32 = 0x00000040; +pub const EPI_HB8_WRWAIT_2: u32 = 0x00000080; +pub const EPI_HB8_WRWAIT_3: u32 = 0x000000C0; +pub const EPI_HB8_RDWAIT_0: u32 = 0x00000000; +pub const EPI_HB8_RDWAIT_1: u32 = 0x00000010; +pub const EPI_HB8_RDWAIT_2: u32 = 0x00000020; +pub const EPI_HB8_RDWAIT_3: u32 = 0x00000030; +pub const EPI_HB8_MODE_ADMUX: u32 = 0x00000000; +pub const EPI_HB8_MODE_ADDEMUX: u32 = 0x00000001; +pub const EPI_HB8_MODE_SRAM: u32 = 0x00000002; +pub const EPI_HB8_MODE_FIFO: u32 = 0x00000003; +pub const EPI_HB8_WORD_ACCESS: u32 = 0x00000100; +pub const EPI_HB8_CSCFG_ALE: u32 = 0x00000000; +pub const EPI_HB8_CSCFG_CS: u32 = 0x00000200; +pub const EPI_HB8_CSCFG_DUAL_CS: u32 = 0x00000400; +pub const EPI_HB8_CSCFG_ALE_DUAL_CS: u32 = 0x00000600; +pub const EPI_HB8_CSCFG_ALE_SINGLE_CS: u32 = 0x00001000; +pub const EPI_HB8_CSCFG_QUAD_CS: u32 = 0x00001200; +pub const EPI_HB8_CSCFG_ALE_QUAD_CS: u32 = 0x00001400; +pub const EPI_HB8_CSBAUD: u32 = 0x00000800; +pub const EPI_HB8_CLOCK_GATE: u32 = 0x80000000; +pub const EPI_HB8_CLOCK_GATE_IDLE: u32 = 0x40000000; +pub const EPI_HB8_CLOCK_INVERT: u32 = 0x20000000; +pub const EPI_HB8_IN_READY_EN: u32 = 0x10000000; +pub const EPI_HB8_IN_READY_EN_INVERT: u32 = 0x18000000; +pub const EPI_HB8_CSCFG_MASK: u32 = 0x00001600; +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB16ModeSet() +// +//***************************************************************************** +pub const EPI_HB16_USE_TXEMPTY: u32 = 0x00800000; +pub const EPI_HB16_USE_RXFULL: u32 = 0x00400000; +pub const EPI_HB16_WRHIGH: u32 = 0x00200000; +pub const EPI_HB16_RDHIGH: u32 = 0x00100000; +pub const EPI_HB16_WRWAIT_0: u32 = 0x00000000; +pub const EPI_HB16_WRWAIT_1: u32 = 0x00000040; +pub const EPI_HB16_WRWAIT_2: u32 = 0x00000080; +pub const EPI_HB16_WRWAIT_3: u32 = 0x000000C0; +pub const EPI_HB16_RDWAIT_0: u32 = 0x00000000; +pub const EPI_HB16_RDWAIT_1: u32 = 0x00000010; +pub const EPI_HB16_RDWAIT_2: u32 = 0x00000020; +pub const EPI_HB16_RDWAIT_3: u32 = 0x00000030; +pub const EPI_HB16_MODE_ADMUX: u32 = 0x00000000; +pub const EPI_HB16_MODE_ADDEMUX: u32 = 0x00000001; +pub const EPI_HB16_MODE_SRAM: u32 = 0x00000002; +pub const EPI_HB16_MODE_FIFO: u32 = 0x00000003; +pub const EPI_HB16_BSEL: u32 = 0x00000004; +pub const EPI_HB16_WORD_ACCESS: u32 = 0x00000100; +pub const EPI_HB16_CSCFG_ALE: u32 = 0x00000000; +pub const EPI_HB16_CSCFG_CS: u32 = 0x00000200; +pub const EPI_HB16_CSCFG_DUAL_CS: u32 = 0x00000400; +pub const EPI_HB16_CSCFG_ALE_DUAL_CS: u32 = 0x00000600; +pub const EPI_HB16_CSCFG_ALE_SINGLE_CS: u32 = 0x00001000; +pub const EPI_HB16_CSCFG_QUAD_CS: u32 = 0x00001200; +pub const EPI_HB16_CSCFG_ALE_QUAD_CS: u32 = 0x00001400; +pub const EPI_HB16_CLOCK_GATE: u32 = 0x80000000; +pub const EPI_HB16_CLOCK_GATE_IDLE: u32 = 0x40000000; +pub const EPI_HB16_CLOCK_INVERT: u32 = 0x20000000; +pub const EPI_HB16_IN_READY_EN: u32 = 0x10000000; +pub const EPI_HB16_IN_READY_EN_INVERTED: u32 = 0x18000000; +pub const EPI_HB16_ALE_HIGH: u32 = 0x00080000; +pub const EPI_HB16_ALE_LOW: u32 = 0x00000000; +pub const EPI_HB16_BURST_TRAFFIC: u32 = 0x00010000; +pub const EPI_HB16_CSBAUD: u32 = 0x00000800; +pub const EPI_HB16_CSCFG_MASK: u32 = 0x00001600; +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB8TimingSet(). +// +//***************************************************************************** +pub const EPI_HB8_IN_READY_DELAY_1: u32 = 0x01000000; +pub const EPI_HB8_IN_READY_DELAY_2: u32 = 0x02000000; +pub const EPI_HB8_IN_READY_DELAY_3: u32 = 0x03000000; +pub const EPI_HB8_CAP_WIDTH_1: u32 = 0x00001000; +pub const EPI_HB8_CAP_WIDTH_2: u32 = 0x00002000; +pub const EPI_HB8_WRWAIT_MINUS_DISABLE: u32 = 0x00000000; +pub const EPI_HB8_WRWAIT_MINUS_ENABLE: u32 = 0x00000010; +pub const EPI_HB8_RDWAIT_MINUS_DISABLE: u32 = 0x00000000; +pub const EPI_HB8_RDWAIT_MINUS_ENABLE: u32 = 0x00000001; +//***************************************************************************** +// +// Values that can be passed to EPIConfigHB16TimingSet(). +// +//***************************************************************************** +pub const EPI_HB16_IN_READY_DELAY_1: u32 = 0x01000000; +pub const EPI_HB16_IN_READY_DELAY_2: u32 = 0x02000000; +pub const EPI_HB16_IN_READY_DELAY_3: u32 = 0x03000000; +pub const EPI_HB16_PSRAM_NO_LIMIT: u32 = 0x00000000; +pub const EPI_HB16_PSRAM_128: u32 = 0x00010000; +pub const EPI_HB16_PSRAM_256: u32 = 0x00020000; +pub const EPI_HB16_PSRAM_512: u32 = 0x00030000; +pub const EPI_HB16_PSRAM_1024: u32 = 0x00040000; +pub const EPI_HB16_PSRAM_2048: u32 = 0x00050000; +pub const EPI_HB16_PSRAM_4096: u32 = 0x00060000; +pub const EPI_HB16_PSRAM_8192: u32 = 0x00070000; +pub const EPI_HB16_CAP_WIDTH_1: u32 = 0x00001000; +pub const EPI_HB16_CAP_WIDTH_2: u32 = 0x00002000; +pub const EPI_HB16_WRWAIT_MINUS_DISABLE: u32 = 0x00000000; +pub const EPI_HB16_WRWAIT_MINUS_ENABLE: u32 = 0x00000008; +pub const EPI_HB16_RDWAIT_MINUS_DISABLE: u32 = 0x00000000; +pub const EPI_HB16_RDWAIT_MINUS_ENABLE: u32 = 0x00000001; +//***************************************************************************** +// +// Values that can be passed to EPIAddressMapSet(). +// +//***************************************************************************** +pub const EPI_ADDR_PER_SIZE_256B: u32 = 0x00000000; +pub const EPI_ADDR_PER_SIZE_64KB: u32 = 0x00000040; +pub const EPI_ADDR_PER_SIZE_16MB: u32 = 0x00000080; +pub const EPI_ADDR_PER_SIZE_256MB: u32 = 0x000000C0; +pub const EPI_ADDR_PER_BASE_NONE: u32 = 0x00000000; +pub const EPI_ADDR_PER_BASE_A: u32 = 0x00000010; +pub const EPI_ADDR_PER_BASE_C: u32 = 0x00000020; +pub const EPI_ADDR_RAM_SIZE_256B: u32 = 0x00000000; +pub const EPI_ADDR_RAM_SIZE_64KB: u32 = 0x00000004; +pub const EPI_ADDR_RAM_SIZE_16MB: u32 = 0x00000008; +pub const EPI_ADDR_RAM_SIZE_256MB: u32 = 0x0000000C; +pub const EPI_ADDR_RAM_BASE_NONE: u32 = 0x00000000; +pub const EPI_ADDR_RAM_BASE_6: u32 = 0x00000001; +pub const EPI_ADDR_RAM_BASE_8: u32 = 0x00000002; +pub const EPI_ADDR_QUAD_MODE: u32 = 0x00000033; +pub const EPI_ADDR_CODE_SIZE_256B: u32 = 0x00000000; +pub const EPI_ADDR_CODE_SIZE_64KB: u32 = 0x00000400; +pub const EPI_ADDR_CODE_SIZE_16MB: u32 = 0x00000800; +pub const EPI_ADDR_CODE_SIZE_256MB: u32 = 0x00000C00; +pub const EPI_ADDR_CODE_BASE_NONE: u32 = 0x00000000; +pub const EPI_ADDR_CODE_BASE_1: u32 = 0x00000100; +//***************************************************************************** +// +// Values that can be passed to EPINonBlockingReadConfigure() +// +//***************************************************************************** +pub const EPI_NBCONFIG_SIZE_8: u32 = 1; +pub const EPI_NBCONFIG_SIZE_16: u32 = 2; +pub const EPI_NBCONFIG_SIZE_32: u32 = 3; +//***************************************************************************** +// +// Values that can be passed to EPIFIFOConfig() +// +//***************************************************************************** +pub const EPI_FIFO_CONFIG_WTFULLERR: u32 = 0x00020000; +pub const EPI_FIFO_CONFIG_RSTALLERR: u32 = 0x00010000; +pub const EPI_FIFO_CONFIG_TX_EMPTY: u32 = 0x00000000; +pub const EPI_FIFO_CONFIG_TX_1_4: u32 = 0x00000020; +pub const EPI_FIFO_CONFIG_TX_1_2: u32 = 0x00000030; +pub const EPI_FIFO_CONFIG_TX_3_4: u32 = 0x00000040; +pub const EPI_FIFO_CONFIG_RX_1_8: u32 = 0x00000001; +pub const EPI_FIFO_CONFIG_RX_1_4: u32 = 0x00000002; +pub const EPI_FIFO_CONFIG_RX_1_2: u32 = 0x00000003; +pub const EPI_FIFO_CONFIG_RX_3_4: u32 = 0x00000004; +pub const EPI_FIFO_CONFIG_RX_7_8: u32 = 0x00000005; +pub const EPI_FIFO_CONFIG_RX_FULL: u32 = 0x00000006; +//***************************************************************************** +// +// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned +// as flags from EPIIntStatus() +// +//***************************************************************************** +pub const EPI_INT_DMA_TX_DONE: u32 = 0x00000010; +pub const EPI_INT_DMA_RX_DONE: u32 = 0x00000008; +pub const EPI_INT_TXREQ: u32 = 0x00000004; +pub const EPI_INT_RXREQ: u32 = 0x00000002; +pub const EPI_INT_ERR: u32 = 0x00000001; +//***************************************************************************** +// +// Values that can be passed to EPIIntErrorClear(), or returned as flags from +// EPIIntErrorStatus() +// +//***************************************************************************** +pub const EPI_INT_ERR_DMAWRIC: u32 = 0x00000010; +pub const EPI_INT_ERR_DMARDIC: u32 = 0x00000008; +pub const EPI_INT_ERR_WTFULL: u32 = 0x00000004; +pub const EPI_INT_ERR_RSTALL: u32 = 0x00000002; +pub const EPI_INT_ERR_TIMEOUT: u32 = 0x00000001; +//***************************************************************************** +// +// Keil case. +// +//***************************************************************************** + // +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +//***************************************************************************** +// +// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and +// returned from FlashIntStatus(). +// +//***************************************************************************** +pub const FLASH_INT_PROGRAM: u32 = 0x00000002; // Programming Interrupt Mask +pub const FLASH_INT_ACCESS: u32 = 0x00000001; // Access Interrupt Mask +pub const FLASH_INT_EEPROM: u32 = 0x00000004; // EEPROM Interrupt Mask +pub const FLASH_INT_VOLTAGE_ERR: u32 = 0x00000200; // Voltage Error Interrupt Mask +pub const FLASH_INT_DATA_ERR: u32 = 0x00000400; // Invalid Data Interrupt Mask +pub const FLASH_INT_ERASE_ERR: u32 = 0x00000800; // Erase Error Interrupt Mask +pub const FLASH_INT_PROGRAM_ERR: u32 = 0x00002000; // Program Verify Error Interrupt Mask +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// fpu.h - Prototypes for the floatint point manipulation routines. +// +// Copyright (c) 2011-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Values that can be passed to FPUHalfPrecisionSet as the ui32Mode parameter. +// +//***************************************************************************** +pub const FPU_HALF_IEEE: u32 = 0x00000000; +pub const FPU_HALF_ALTERNATE: u32 = 0x04000000; +//***************************************************************************** +// +// Values that can be passed to FPUNaNModeSet as the ui32Mode parameter. +// +//***************************************************************************** +pub const FPU_NAN_PROPAGATE: u32 = 0x00000000; +pub const FPU_NAN_DEFAULT: u32 = 0x02000000; +//***************************************************************************** +// +// Values that can be passed to FPUFlushToZeroModeSet as the ui32Mode +// parameter. +// +//***************************************************************************** +pub const FPU_FLUSH_TO_ZERO_DIS: u32 = 0x00000000; +pub const FPU_FLUSH_TO_ZERO_EN: u32 = 0x01000000; +//***************************************************************************** +// +// Values that can be passed to FPURoundingModeSet as the ui32Mode parameter. +// +//***************************************************************************** +pub const FPU_ROUND_NEAREST: u32 = 0x00000000; +pub const FPU_ROUND_POS_INF: u32 = 0x00400000; +pub const FPU_ROUND_NEG_INF: u32 = 0x00800000; +pub const FPU_ROUND_ZERO: u32 = 0x00c00000; +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// The following values define the bit field for the ui8Pins argument to +// several of the APIs. +// +//***************************************************************************** +pub const GPIO_PIN_0: u8 = 0x01; // GPIO pin 0 +pub const GPIO_PIN_1: u8 = 0x02; // GPIO pin 1 +pub const GPIO_PIN_2: u8 = 0x04; // GPIO pin 2 +pub const GPIO_PIN_3: u8 = 0x08; // GPIO pin 3 +pub const GPIO_PIN_4: u8 = 0x10; // GPIO pin 4 +pub const GPIO_PIN_5: u8 = 0x20; // GPIO pin 5 +pub const GPIO_PIN_6: u8 = 0x40; // GPIO pin 6 +pub const GPIO_PIN_7: u8 = 0x80; // GPIO pin 7 +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +pub const GPIO_DIR_MODE_IN: u32 = 0x00000000; // Pin is a GPIO input +pub const GPIO_DIR_MODE_OUT: u32 = 0x00000001; // Pin is a GPIO output +pub const GPIO_DIR_MODE_HW: u32 = 0x00000002; // Pin is a peripheral function +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter, +// and returned from GPIOIntTypeGet. +// +//***************************************************************************** +pub const GPIO_FALLING_EDGE: u32 = 0x00000000; // Interrupt on falling edge +pub const GPIO_RISING_EDGE: u32 = 0x00000004; // Interrupt on rising edge +pub const GPIO_BOTH_EDGES: u32 = 0x00000001; // Interrupt on both edges +pub const GPIO_LOW_LEVEL: u32 = 0x00000002; // Interrupt on low level +pub const GPIO_HIGH_LEVEL: u32 = 0x00000006; // Interrupt on high level +pub const GPIO_DISCRETE_INT: u32 = 0x00010000; // Interrupt for individual pins +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter, +// and returned by GPIOPadConfigGet in the *pui32Strength parameter. +// +//***************************************************************************** +pub const GPIO_STRENGTH_2MA: u32 = 0x00000001; // 2mA drive strength +pub const GPIO_STRENGTH_4MA: u32 = 0x00000002; // 4mA drive strength +pub const GPIO_STRENGTH_6MA: u32 = 0x00000065; // 6mA drive strength +pub const GPIO_STRENGTH_8MA: u32 = 0x00000066; // 8mA drive strength +pub const GPIO_STRENGTH_8MA_SC: u32 = 0x0000006E; // 8mA drive with slew rate control +pub const GPIO_STRENGTH_10MA: u32 = 0x00000075; // 10mA drive strength +pub const GPIO_STRENGTH_12MA: u32 = 0x00000077; // 12mA drive strength +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter, +// and returned by GPIOPadConfigGet in the *pui32PadType parameter. +// +//***************************************************************************** +pub const GPIO_PIN_TYPE_STD: u32 = 0x00000008; // Push-pull +pub const GPIO_PIN_TYPE_STD_WPU: u32 = 0x0000000A; // Push-pull with weak pull-up +pub const GPIO_PIN_TYPE_STD_WPD: u32 = 0x0000000C; // Push-pull with weak pull-down +pub const GPIO_PIN_TYPE_OD: u32 = 0x00000009; // Open-drain +pub const GPIO_PIN_TYPE_ANALOG: u32 = 0x00000000; // Analog comparator +pub const GPIO_PIN_TYPE_WAKE_HIGH: u32 = 0x00000208; // Hibernate wake, high +pub const GPIO_PIN_TYPE_WAKE_LOW: u32 = 0x00000108; // Hibernate wake, low +//***************************************************************************** +// +// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions +// in the ui32IntFlags parameter. +// +//***************************************************************************** +pub const GPIO_INT_PIN_0: u32 = 0x00000001; +pub const GPIO_INT_PIN_1: u32 = 0x00000002; +pub const GPIO_INT_PIN_2: u32 = 0x00000004; +pub const GPIO_INT_PIN_3: u32 = 0x00000008; +pub const GPIO_INT_PIN_4: u32 = 0x00000010; +pub const GPIO_INT_PIN_5: u32 = 0x00000020; +pub const GPIO_INT_PIN_6: u32 = 0x00000040; +pub const GPIO_INT_PIN_7: u32 = 0x00000080; +pub const GPIO_INT_DMA: u32 = 0x00000100; +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// hibernate.h - API definition for the Hibernation module. +// +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Macros need to configure wake events for HibernateWakeSet() +// +//***************************************************************************** +pub const HIBERNATE_WAKE_PIN: u32 = 0x00000010; +pub const HIBERNATE_WAKE_RTC: u32 = 0x00000008; +pub const HIBERNATE_WAKE_LOW_BAT: u32 = 0x00000200; +pub const HIBERNATE_WAKE_GPIO: u32 = 0x00000010; +pub const HIBERNATE_WAKE_RESET: u32 = 0x00100010; +pub const HIBERNATE_WAKE_TAMPER: u32 = 0x08000010; +//***************************************************************************** +// +// Macros needed to configure low battery detect for HibernateLowBatSet() +// +//***************************************************************************** +pub const HIBERNATE_LOW_BAT_DETECT: u32 = 0x00000020; +pub const HIBERNATE_LOW_BAT_ABORT: u32 = 0x000000A0; +pub const HIBERNATE_LOW_BAT_1_9V: u32 = 0x00000000; +pub const HIBERNATE_LOW_BAT_2_1V: u32 = 0x00002000; +pub const HIBERNATE_LOW_BAT_2_3V: u32 = 0x00004000; +pub const HIBERNATE_LOW_BAT_2_5V: u32 = 0x00006000; +//***************************************************************************** +// +// Macros defining interrupt source bits for the interrupt functions. +// +//***************************************************************************** +pub const HIBERNATE_INT_VDDFAIL: u32 = 0x00000080; +pub const HIBERNATE_INT_RESET_WAKE: u32 = 0x00000040; +pub const HIBERNATE_INT_GPIO_WAKE: u32 = 0x00000020; +pub const HIBERNATE_INT_WR_COMPLETE: u32 = 0x00000010; +pub const HIBERNATE_INT_PIN_WAKE: u32 = 0x00000008; +pub const HIBERNATE_INT_LOW_BAT: u32 = 0x00000004; +pub const HIBERNATE_INT_RTC_MATCH_0: u32 = 0x00000001; +//***************************************************************************** +// +// Macros defining oscillator configuration options for the +// HibernateClockConfig() function. +// +//***************************************************************************** +pub const HIBERNATE_OSC_LFIOSC: u32 = 0x00080000; +pub const HIBERNATE_OSC_LOWDRIVE: u32 = 0x00000000; +pub const HIBERNATE_OSC_HIGHDRIVE: u32 = 0x00020000; +pub const HIBERNATE_OSC_DISABLE: u32 = 0x00010000; +pub const HIBERNATE_OUT_WRSTALL: u32 = 0x20000000; +pub const HIBERNATE_OUT_SYSCLK: u32 = 0x00000001; +//***************************************************************************** +// +// The following defines are used with the HibernateCounterMode() API. +// +//***************************************************************************** +pub const HIBERNATE_COUNTER_RTC: u32 = 0x00000000; +pub const HIBERNATE_COUNTER_12HR: u32 = 0x00000001; +pub const HIBERNATE_COUNTER_24HR: u32 = 0x00000005; +//***************************************************************************** +// +// Tamper event configuration options used with HibernateTamperEventsConfig(). +// +//***************************************************************************** +pub const HIBERNATE_TAMPER_EVENTS_NO_HIB_WAKE: u32 = 0x00000000; +pub const HIBERNATE_TAMPER_EVENTS_HIB_WAKE: u32 = 0x00000800; +pub const HIBERNATE_TAMPER_EVENTS_NO_ERASE_HIB_MEM: u32 = 0x00000000; +pub const HIBERNATE_TAMPER_EVENTS_ERASE_LOW_HIB_MEM: u32 = 0x00000100; +pub const HIBERNATE_TAMPER_EVENTS_ERASE_HIGH_HIB_MEM: u32 = 0x00000200; +pub const HIBERNATE_TAMPER_EVENTS_ERASE_ALL_HIB_MEM: u32 = 0x00000300; +//***************************************************************************** +// +// Status flags returned by the HibernateTamperStatus() function. +// +//***************************************************************************** +pub const HIBERNATE_TAMPER_STATUS_INACTIVE: u32 = 0x00000010; +pub const HIBERNATE_TAMPER_STATUS_ACTIVE: u32 = 0x00000020; +pub const HIBERNATE_TAMPER_STATUS_EVENT: u32 = 0x00000040; +pub const HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE: u32 = 0x00000008; +pub const HIBERNATE_TAMPER_STATUS_EXT_OSC_INACTIVE: u32 = 0x00000002; +pub const HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID: u32 = 0x00000004; +pub const HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED: u32 = 0x00000001; +//***************************************************************************** +// +// Configuration options used with HibernateTamperIOEnable(). +// +//***************************************************************************** +pub const HIBERNATE_TAMPER_IO_TRIGGER_LOW: u32 = 0x00000000; +pub const HIBERNATE_TAMPER_IO_TRIGGER_HIGH: u32 = 0x00000002; +pub const HIBERNATE_TAMPER_IO_WPU_DISABLED: u32 = 0x00000000; +pub const HIBERNATE_TAMPER_IO_WPU_ENABLED: u32 = 0x00000004; +pub const HIBERNATE_TAMPER_IO_MATCH_SHORT: u32 = 0x00000000; +pub const HIBERNATE_TAMPER_IO_MATCH_LONG: u32 = 0x00000008; +//***************************************************************************** +// +// Tamper log event flags. +// +//***************************************************************************** +pub const HIBERNATE_TAMPER_EVENT_0: u32 = 0x00000001; +pub const HIBERNATE_TAMPER_EVENT_1: u32 = 0x00000002; +pub const HIBERNATE_TAMPER_EVENT_2: u32 = 0x00000004; +pub const HIBERNATE_TAMPER_EVENT_3: u32 = 0x00000008; +pub const HIBERNATE_TAMPER_EVENT_EXT_OSC: u32 = 0x00010000; +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +pub const I2C_INT_MASTER: u32 = 0x00000001; +pub const I2C_INT_SLAVE: u32 = 0x00000002; +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +pub const I2C_MASTER_CMD_SINGLE_SEND: u32 = 0x00000007; +pub const I2C_MASTER_CMD_SINGLE_RECEIVE: u32 = 0x00000007; +pub const I2C_MASTER_CMD_BURST_SEND_START: u32 = 0x00000003; +pub const I2C_MASTER_CMD_BURST_SEND_CONT: u32 = 0x00000001; +pub const I2C_MASTER_CMD_BURST_SEND_FINISH: u32 = 0x00000005; +pub const I2C_MASTER_CMD_BURST_SEND_STOP: u32 = 0x00000004; +pub const I2C_MASTER_CMD_BURST_SEND_ERROR_STOP: u32 = 0x00000004; +pub const I2C_MASTER_CMD_BURST_RECEIVE_START: u32 = 0x0000000b; +pub const I2C_MASTER_CMD_BURST_RECEIVE_CONT: u32 = 0x00000009; +pub const I2C_MASTER_CMD_BURST_RECEIVE_FINISH: u32 = 0x00000005; +pub const I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP: u32 = 0x00000004; +pub const I2C_MASTER_CMD_QUICK_COMMAND: u32 = 0x00000027; +pub const I2C_MASTER_CMD_HS_MASTER_CODE_SEND: u32 = 0x00000013; +pub const I2C_MASTER_CMD_FIFO_SINGLE_SEND: u32 = 0x00000046; +pub const I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE: u32 = 0x00000046; +pub const I2C_MASTER_CMD_FIFO_BURST_SEND_START: u32 = 0x00000042; +pub const I2C_MASTER_CMD_FIFO_BURST_SEND_CONT: u32 = 0x00000040; +pub const I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH: u32 = 0x00000044; +pub const I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP: u32 = 0x00000004; +pub const I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START: u32 = 0x0000004a; +pub const I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT: u32 = 0x00000048; +pub const I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH: u32 = 0x00000044; +pub const I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP: u32 = 0x00000004; +//***************************************************************************** +// +// I2C Master glitch filter configuration. +// +//***************************************************************************** +pub const I2C_MASTER_GLITCH_FILTER_DISABLED: u32 = 0; +pub const I2C_MASTER_GLITCH_FILTER_1: u32 = 0x00010000; +pub const I2C_MASTER_GLITCH_FILTER_2: u32 = 0x00020000; +pub const I2C_MASTER_GLITCH_FILTER_3: u32 = 0x00030000; +pub const I2C_MASTER_GLITCH_FILTER_4: u32 = 0x00040000; +pub const I2C_MASTER_GLITCH_FILTER_8: u32 = 0x00050000; +pub const I2C_MASTER_GLITCH_FILTER_16: u32 = 0x00060000; +pub const I2C_MASTER_GLITCH_FILTER_32: u32 = 0x00070000; +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +pub const I2C_MASTER_ERR_NONE: u32 = 0; +pub const I2C_MASTER_ERR_ADDR_ACK: u32 = 0x00000004; +pub const I2C_MASTER_ERR_DATA_ACK: u32 = 0x00000008; +pub const I2C_MASTER_ERR_ARB_LOST: u32 = 0x00000010; +pub const I2C_MASTER_ERR_CLK_TOUT: u32 = 0x00000080; +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +pub const I2C_SLAVE_ACT_NONE: u32 = 0; +pub const I2C_SLAVE_ACT_RREQ: u32 = 0x00000001; // Master has sent data +pub const I2C_SLAVE_ACT_TREQ: u32 = 0x00000002; // Master has requested data +pub const I2C_SLAVE_ACT_RREQ_FBR: u32 = 0x00000005; // Master has sent first byte +pub const I2C_SLAVE_ACT_OWN2SEL: u32 = 0x00000008; // Master requested secondary slave +pub const I2C_SLAVE_ACT_QCMD: u32 = 0x00000010; // Master has sent a Quick Command +pub const I2C_SLAVE_ACT_QCMD_DATA: u32 = 0x00000020; // Master Quick Command value +//***************************************************************************** +// +// Miscellaneous I2C driver definitions. +// +//***************************************************************************** +pub const I2C_MASTER_MAX_RETRIES: u32 = 1000; // Number of retries +//***************************************************************************** +// +// I2C Master interrupts. +// +//***************************************************************************** +pub const I2C_MASTER_INT_RX_FIFO_FULL: u32 = 0x00000800; // RX FIFO Full Interrupt +pub const I2C_MASTER_INT_TX_FIFO_EMPTY: u32 = 0x00000400; // TX FIFO Empty Interrupt +pub const I2C_MASTER_INT_RX_FIFO_REQ: u32 = 0x00000200; // RX FIFO Request Interrupt +pub const I2C_MASTER_INT_TX_FIFO_REQ: u32 = 0x00000100; // TX FIFO Request Interrupt +pub const I2C_MASTER_INT_ARB_LOST: u32 = 0x00000080; // Arb Lost Interrupt +pub const I2C_MASTER_INT_STOP: u32 = 0x00000040; // Stop Condition Interrupt +pub const I2C_MASTER_INT_START: u32 = 0x00000020; // Start Condition Interrupt +pub const I2C_MASTER_INT_NACK: u32 = 0x00000010; // Addr/Data NACK Interrupt +pub const I2C_MASTER_INT_TX_DMA_DONE: u32 = 0x00000008; // TX DMA Complete Interrupt +pub const I2C_MASTER_INT_RX_DMA_DONE: u32 = 0x00000004; // RX DMA Complete Interrupt +pub const I2C_MASTER_INT_TIMEOUT: u32 = 0x00000002; // Clock Timeout Interrupt +pub const I2C_MASTER_INT_DATA: u32 = 0x00000001; // Data Interrupt +//***************************************************************************** +// +// I2C Slave interrupts. +// +//***************************************************************************** +pub const I2C_SLAVE_INT_RX_FIFO_FULL: u32 = 0x00000100; // RX FIFO Full Interrupt +pub const I2C_SLAVE_INT_TX_FIFO_EMPTY: u32 = 0x00000080; // TX FIFO Empty Interrupt +pub const I2C_SLAVE_INT_RX_FIFO_REQ: u32 = 0x00000040; // RX FIFO Request Interrupt +pub const I2C_SLAVE_INT_TX_FIFO_REQ: u32 = 0x00000020; // TX FIFO Request Interrupt +pub const I2C_SLAVE_INT_TX_DMA_DONE: u32 = 0x00000010; // TX DMA Complete Interrupt +pub const I2C_SLAVE_INT_RX_DMA_DONE: u32 = 0x00000008; // RX DMA Complete Interrupt +pub const I2C_SLAVE_INT_STOP: u32 = 0x00000004; // Stop Condition Interrupt +pub const I2C_SLAVE_INT_START: u32 = 0x00000002; // Start Condition Interrupt +pub const I2C_SLAVE_INT_DATA: u32 = 0x00000001; // Data Interrupt +//***************************************************************************** +// +// I2C Slave FIFO configuration macros. +// +//***************************************************************************** +pub const I2C_SLAVE_TX_FIFO_ENABLE: u32 = 0x00000002; +pub const I2C_SLAVE_RX_FIFO_ENABLE: u32 = 0x00000004; +//***************************************************************************** +// +// I2C FIFO configuration macros. +// +//***************************************************************************** +pub const I2C_FIFO_CFG_TX_MASTER: u32 = 0x00000000; +pub const I2C_FIFO_CFG_TX_SLAVE: u32 = 0x00008000; +pub const I2C_FIFO_CFG_RX_MASTER: u32 = 0x00000000; +pub const I2C_FIFO_CFG_RX_SLAVE: u32 = 0x80000000; +pub const I2C_FIFO_CFG_TX_MASTER_DMA: u32 = 0x00002000; +pub const I2C_FIFO_CFG_TX_SLAVE_DMA: u32 = 0x0000a000; +pub const I2C_FIFO_CFG_RX_MASTER_DMA: u32 = 0x20000000; +pub const I2C_FIFO_CFG_RX_SLAVE_DMA: u32 = 0xa0000000; +pub const I2C_FIFO_CFG_TX_NO_TRIG: u32 = 0x00000000; +pub const I2C_FIFO_CFG_TX_TRIG_1: u32 = 0x00000001; +pub const I2C_FIFO_CFG_TX_TRIG_2: u32 = 0x00000002; +pub const I2C_FIFO_CFG_TX_TRIG_3: u32 = 0x00000003; +pub const I2C_FIFO_CFG_TX_TRIG_4: u32 = 0x00000004; +pub const I2C_FIFO_CFG_TX_TRIG_5: u32 = 0x00000005; +pub const I2C_FIFO_CFG_TX_TRIG_6: u32 = 0x00000006; +pub const I2C_FIFO_CFG_TX_TRIG_7: u32 = 0x00000007; +pub const I2C_FIFO_CFG_TX_TRIG_8: u32 = 0x00000008; +pub const I2C_FIFO_CFG_RX_NO_TRIG: u32 = 0x00000000; +pub const I2C_FIFO_CFG_RX_TRIG_1: u32 = 0x00010000; +pub const I2C_FIFO_CFG_RX_TRIG_2: u32 = 0x00020000; +pub const I2C_FIFO_CFG_RX_TRIG_3: u32 = 0x00030000; +pub const I2C_FIFO_CFG_RX_TRIG_4: u32 = 0x00040000; +pub const I2C_FIFO_CFG_RX_TRIG_5: u32 = 0x00050000; +pub const I2C_FIFO_CFG_RX_TRIG_6: u32 = 0x00060000; +pub const I2C_FIFO_CFG_RX_TRIG_7: u32 = 0x00070000; +pub const I2C_FIFO_CFG_RX_TRIG_8: u32 = 0x00080000; +//***************************************************************************** +// +// I2C FIFO status. +// +//***************************************************************************** +pub const I2C_FIFO_RX_BELOW_TRIG_LEVEL: u32 = 0x00040000; +pub const I2C_FIFO_RX_FULL: u32 = 0x00020000; +pub const I2C_FIFO_RX_EMPTY: u32 = 0x00010000; +pub const I2C_FIFO_TX_BELOW_TRIG_LEVEL: u32 = 0x00000004; +pub const I2C_FIFO_TX_FULL: u32 = 0x00000002; +pub const I2C_FIFO_TX_EMPTY: u32 = 0x00000001; +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. +// +//***************************************************************************** + +pub const INT_PRIORITY_MASK: u32 = (0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF; +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// lcd.h - Defines and Macros for the LCD Controller module. +// +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// \addtogroup lcd_api +// @{ +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// This macro can be used to convert a 24-bit RGB color value as used by the +// TivaWare Graphics Library into a 12-bit LCD controller color palette +// entry. +// +//***************************************************************************** +//pub const PAL_FROM_RGB(ui32RGBColor): u32 = (((ui32RGBColor; +//***************************************************************************** +// +// This macro can be used to convert from time in microseconds to periods of +// the supplied clock in Hertz as required when setting up the LIDD and raster +// timing structures. The calculation will round such that the number of +// cycles returned represents no longer a time than specified in the +// ui32Time_uS parameter. Values of ui32Time_uS less than or equal to +// 4294967uS (4.29 seconds) are supported by the macro. Larger values will +// cause arithmetic overflow and yield incorrect values. It is further +// assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz). +// +//***************************************************************************** +//pub const CYCLES_FROM_TIME_US(ui32ClockFreq,: u32 = ui32Time_uS); +//***************************************************************************** +// +// This macro can be used to convert from time in nanoseconds to periods of +// the supplied clock in Hertz as required when setting up the LIDD and raster +// timing structures. The calculation will round such that the number of +// cycles returned represents no longer a time than specified in the +// ui32Time_nS parameter. Values of ui32Time_nS less than or equal to +// 35791394 (35.79 milliseconds) are supported by the macro. Larger values +// will cause arithmetic overflow and yield incorrect values. It is further +// assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz). +// +//***************************************************************************** +//pub const CYCLES_FROM_TIME_NS(ui32ClockFreq,: u32 = ui32Time_nS); +//***************************************************************************** +// +// A structure containing timing parameters for the LIDD (LCD Interface +// Display Driver) interface. This is used with the LCDIDDTimingSet function. +// +//***************************************************************************** + // + // Write Strobe Set-Up cycles. When performing a write access, this + // field defines the number of MCLK cycles that Data Bus/Pad Output + // Enable, ALE, the Direction bit, and Chip Select have to be ready before + // the Write Strobe is asserted. Valid values are from 0 to 31. + // + // + // Write Strobe Duration cycles. Field value defines the number of MCLK + // cycles for which the Write Strobe is held active when performing a + // write access. Valid values are from 1 to 63. + // + // + // Write Strobe Hold cycles. Field value defines the number of MCLK + // cycles for which Data Bus/Pad Output Enable, ALE, the Direction bit, + // and Chip Select are held after the Write Strobe is deasserted when + // performing a write access. Valid values are from 1 to 15. + // + // + // Read Strobe Set-Up cycles. When performing a read access, this field + // defines the number of MCLK cycles that Data Bus/Pad Output Enable, ALE, + // the Direction bit, and Chip Select have to be ready before the Read + // Strobe is asserted. Valid values are from 0 to 31. + // + // + // Read Strobe Duration cycles. Field value defines the number of MCLK + // cycles for which the Read Strobe is held active when performing a read + // access. Valid values are from 1 to 63. + // + // + // Read Strobe Hold cycles. Field value defines the number of MCLK cycles + // for which Data Bus/Pad Output Enable, ALE, the Direction bit, and Chip + // Select are held after the Read Strobe is deasserted when performing a + // read access. Valid values are from 1 to 15. + // + // + // Field value defines the number of MCLK cycles between the end of one + // device access and the start of another device access using the same + // Chip Select unless the two accesses are both Reads. In this case, + // this delay is not incurred. Valid vales are from 1 to 4. + // +// +// Values which can be ORed together within the ui32Flags field of the +// tLCDRasterTiming structure. +// +pub const RASTER_TIMING_SYNCS_OPPOSITE_PIXCLK: u32 = 0x00000000; +pub const RASTER_TIMING_SYNCS_ON_RISING_PIXCLK: u32 = 0x02000000; +pub const RASTER_TIMING_SYNCS_ON_FALLING_PIXCLK: u32 = 0x03000000; +pub const RASTER_TIMING_ACTIVE_HIGH_OE: u32 = 0x00000000; +pub const RASTER_TIMING_ACTIVE_LOW_OE: u32 = 0x00800000; +pub const RASTER_TIMING_ACTIVE_HIGH_PIXCLK: u32 = 0x00000000; +pub const RASTER_TIMING_ACTIVE_LOW_PIXCLK: u32 = 0x00400000; +pub const RASTER_TIMING_ACTIVE_HIGH_HSYNC: u32 = 0x00000000; +pub const RASTER_TIMING_ACTIVE_LOW_HSYNC: u32 = 0x00200000; +pub const RASTER_TIMING_ACTIVE_HIGH_VSYNC: u32 = 0x00000000; +pub const RASTER_TIMING_ACTIVE_LOW_VSYNC: u32 = 0x00100000; +// +// A structure containing timing parameters for the raster interface. This is +// used with the LCDRasterTimingSet function. +// + // + // Flags configuring the polarity and active edges of the various signals + // in the raster interface. This field is comprised of a logical OR of + // the labels with prefix ``RASTER_TIMING_''. + // + // + // The number of pixels contained within each line on the LCD display. + // Valid values are multiple of 16 less than or equal to 2048. + // + // + // The number of lines on the LCD display. Valid values are from 1 to + // 2048. + // + // + // A value from 1 to 1024 that specifies the number of pixel clock periods + // to add to the end of each line after active video has ended. + // + // + // A value from 1 to 1024 that specifies the number of pixel clock periods + // to add to the beginning of a line before active video is asserted. + // + // + // A value from 1 to 1024 that specifies the number of pixel clock periods + // to pulse the line clock at the end of each line. + // + // + // A value from 0 to 255 that specifies the number of line clock periods + // to add to the end of each frame after the last active line. + // + // + // A value from 0 to 255 that specifies the number of line clock periods + // to add to the beginning of a frame before the first active line is + // output to the display. + // + // + // In active mode, a value from 1 to 64 that specifies the number of + // line clock periods to set the lcd_fp pin active at the end of each + // frame after the vertical front porch period elapses. The number of + // The frame clock is used as the VSYNC signal in active mode. + // + // In passive mode, a value from 1 to 64 that specifies the number of + // extra line clock periods to insert after the vertical front porch + // period has elapsed. Note that the width of lcd_fp is not affected by + // this value in passive mode. + // + // + // A value from 0 to 255 that specifies the number of line clocks to + // count before transitioning the AC Bias pin. This pin is used to + // periodically invert the polarity of the power supply to prevent DC + // charge build-up within the display. + // +//***************************************************************************** +// +// Possible values for the ui8Mode parameter to LCDModeSet(). The label +// LCD_MODE_AUTO_UFLOW_RESTART may be ORed with either of the other two. +// +//***************************************************************************** +pub const LCD_MODE_LIDD: u8 = 0x0; +pub const LCD_MODE_RASTER: u8 = 0x01; +pub const LCD_MODE_AUTO_UFLOW_RESTART: u8 = 0x02; +//***************************************************************************** +// +// Values used to pub construct the ui32Config parameter to LCDIDDConfigSet(). +// +//***************************************************************************** +pub const LIDD_CONFIG_SYNC_MPU68: u32 = 0x00000000; +pub const LIDD_CONFIG_ASYNC_MPU68: u32 = 0x00000001; +pub const LIDD_CONFIG_SYNC_MPU80: u32 = 0x00000002; +pub const LIDD_CONFIG_ASYNC_MPU80: u32 = 0x00000003; +pub const LIDD_CONFIG_ASYNC_HITACHI: u32 = 0x00000004; +pub const LIDD_CONFIG_INVERT_ALE: u32 = 0x00000008; +pub const LIDD_CONFIG_INVERT_RS_EN: u32 = 0x00000010; +pub const LIDD_CONFIG_INVERT_WS_DIR: u32 = 0x00000020; +pub const LIDD_CONFIG_INVERT_CS0: u32 = 0x00000040; +pub const LIDD_CONFIG_INVERT_CS1: u32 = 0x00000080; +//***************************************************************************** +// +// Values used to pub construct the ui32Config parameter to +// LCDRasterConfigSet(). Valid parameters contain one of the RASTER_FMT_xxx +// labels optionally ORed with the other flags. Only one of +// RASTER_LOAD_DATA_ONLY and RASTER_LOAD_PALETTE_ONLY may be specified (if +// neither is specified, the controller will load both palette and data when +// scanning out the frame buffer). +// +//***************************************************************************** +pub const RASTER_FMT_ACTIVE_24BPP_PACKED: u32 = 0x02000080; +pub const RASTER_FMT_ACTIVE_24BPP_UNPACKED: u32 = 0x06000080; +pub const RASTER_FMT_ACTIVE_PALETTIZED_12BIT: u32 = 0x00000080; +pub const RASTER_FMT_ACTIVE_PALETTIZED_16BIT: u32 = 0x00800080; +pub const RASTER_FMT_PASSIVE_MONO_4PIX: u32 = 0x00000002; +pub const RASTER_FMT_PASSIVE_MONO_8PIX: u32 = 0x00000202; +pub const RASTER_FMT_PASSIVE_PALETTIZED: u32 = 0x00000000; +pub const RASTER_FMT_PASSIVE_COLOR_12BIT: u32 = 0x00000000; +pub const RASTER_FMT_PASSIVE_COLOR_16BIT: u32 = 0x01000000; +pub const RASTER_ACTVID_DURING_BLANK: u32 = 0x08000000; +pub const RASTER_NIBBLE_MODE_ENABLED: u32 = 0x00400000; +pub const RASTER_LOAD_DATA_ONLY: u32 = 0x00200000; +pub const RASTER_LOAD_PALETTE_ONLY: u32 = 0x00100000; +pub const RASTER_READ_ORDER_REVERSED: u32 = 0x00000100; +//***************************************************************************** +// +// Interrupt sources for the LCD controller. These may be ORed together and +// passed to LCDIntEnable(), LCDIntDisable() and LCDIntClear(). They are also +// returned by LCDIntStatus(). +// +//***************************************************************************** +pub const LCD_INT_DMA_DONE: u32 = 0x00000001; +pub const LCD_INT_RASTER_FRAME_DONE: u32 = 0x00000002; +pub const LCD_INT_SYNC_LOST: u32 = 0x00000004; +pub const LCD_INT_AC_BIAS_CNT: u32 = 0x00000008; +pub const LCD_INT_UNDERFLOW: u32 = 0x00000020; +pub const LCD_INT_PAL_LOAD: u32 = 0x00000040; +pub const LCD_INT_EOF0: u32 = 0x00000100; +pub const LCD_INT_EOF1: u32 = 0x00000200; +//***************************************************************************** +// +// Configuration values used with LCDDMAConfigSet(). +// +//***************************************************************************** +pub const LCD_DMA_FIFORDY_8_WORDS: u32 = 0x00000000; +pub const LCD_DMA_FIFORDY_16_WORDS: u32 = 0x00000100; +pub const LCD_DMA_FIFORDY_32_WORDS: u32 = 0x00000200; +pub const LCD_DMA_FIFORDY_64_WORDS: u32 = 0x00000300; +pub const LCD_DMA_FIFORDY_128_WORDS: u32 = 0x00000400; +pub const LCD_DMA_FIFORDY_256_WORDS: u32 = 0x00000500; +pub const LCD_DMA_FIFORDY_512_WORDS: u32 = 0x00000600; +pub const LCD_DMA_BURST_1: u32 = 0x00000010; +pub const LCD_DMA_BURST_2: u32 = 0x00000010; +pub const LCD_DMA_BURST_4: u32 = 0x00000020; +pub const LCD_DMA_BURST_8: u32 = 0x00000030; +pub const LCD_DMA_BURST_16: u32 = 0x00000040; +pub const LCD_DMA_BYTE_ORDER_0123: u32 = 0x00000000; +pub const LCD_DMA_BYTE_ORDER_1023: u32 = 0x00000008; +pub const LCD_DMA_BYTE_ORDER_3210: u32 = 0x00000002; +pub const LCD_DMA_BYTE_ORDER_2301: u32 = 0x0000000A; +pub const LCD_DMA_PING_PONG: u32 = 0x00000001; +//***************************************************************************** +// +// Type values used with LCDRasterPaletteSet(). +// +//***************************************************************************** +pub const LCD_PALETTE_TYPE_1BPP: u32 = 0x00000000; +pub const LCD_PALETTE_TYPE_2BPP: u32 = 0x00001000; +pub const LCD_PALETTE_TYPE_4BPP: u32 = 0x00002000; +pub const LCD_PALETTE_TYPE_8BPP: u32 = 0x00003000; +pub const LCD_PALETTE_TYPE_DIRECT: u32 = 0x00004000; +pub const LCD_PALETTE_SRC_24BIT: u32 = 0x80000000; +//***************************************************************************** +// +// Flags used in the ui32Clocks parameter to LCDClockReset(). +// +//***************************************************************************** +pub const LCD_CLOCK_MAIN: u32 = 0x00000008; +pub const LCD_CLOCK_DMA: u32 = 0x00000004; +pub const LCD_CLOCK_LIDD: u32 = 0x00000002; +pub const LCD_CLOCK_CORE: u32 = 0x00000001; +//***************************************************************************** +// +// Flags used in with LCDSubPanelConfigSet(). +// +//***************************************************************************** +pub const LCD_SUBPANEL_AT_TOP: u32 = 0x20000000; +pub const LCD_SUBPANEL_AT_BOTTOM: u32 = 0x00000000; +//***************************************************************************** +// +// Close the Doxygen group. +// @} +// +//***************************************************************************** +//***************************************************************************** +// +// Function Prototypes. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// mpu.h - Defines and Macros for the memory protection unit. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Flags that can be passed to MPUEnable. +// +//***************************************************************************** +pub const MPU_CONFIG_PRIV_DEFAULT: u32 = 4; +pub const MPU_CONFIG_HARDFLT_NMI: u32 = 2; +pub const MPU_CONFIG_NONE: u32 = 0; +//***************************************************************************** +// +// Flags for the region size to be passed to MPURegionSet. +// +//***************************************************************************** +pub const MPU_RGN_SIZE_32B: u32 = 4<<1; +pub const MPU_RGN_SIZE_64B: u32 = 5<<1; +pub const MPU_RGN_SIZE_128B: u32 = 6<<1; +pub const MPU_RGN_SIZE_256B: u32 = 7<<1; +pub const MPU_RGN_SIZE_512B: u32 = 8<<1; +pub const MPU_RGN_SIZE_1K: u32 = 9<<1; +pub const MPU_RGN_SIZE_2K: u32 = 10<<1; +pub const MPU_RGN_SIZE_4K: u32 = 11<<1; +pub const MPU_RGN_SIZE_8K: u32 = 12<<1; +pub const MPU_RGN_SIZE_16K: u32 = 13<<1; +pub const MPU_RGN_SIZE_32K: u32 = 14<<1; +pub const MPU_RGN_SIZE_64K: u32 = 15<<1; +pub const MPU_RGN_SIZE_128K: u32 = 16<<1; +pub const MPU_RGN_SIZE_256K: u32 = 17<<1; +pub const MPU_RGN_SIZE_512K: u32 = 18<<1; +pub const MPU_RGN_SIZE_1M: u32 = 19<<1; +pub const MPU_RGN_SIZE_2M: u32 = 20<<1; +pub const MPU_RGN_SIZE_4M: u32 = 21<<1; +pub const MPU_RGN_SIZE_8M: u32 = 22<<1; +pub const MPU_RGN_SIZE_16M: u32 = 23<<1; +pub const MPU_RGN_SIZE_32M: u32 = 24<<1; +pub const MPU_RGN_SIZE_64M: u32 = 25<<1; +pub const MPU_RGN_SIZE_128M: u32 = 26<<1; +pub const MPU_RGN_SIZE_256M: u32 = 27<<1; +pub const MPU_RGN_SIZE_512M: u32 = 28<<1; +pub const MPU_RGN_SIZE_1G: u32 = 29<<1; +pub const MPU_RGN_SIZE_2G: u32 = 30<<1; +pub const MPU_RGN_SIZE_4G: u32 = 31<<1; +//***************************************************************************** +// +// Flags for the permissions to be passed to MPURegionSet. +// +//***************************************************************************** +pub const MPU_RGN_PERM_EXEC: u32 = 0x00000000; +pub const MPU_RGN_PERM_NOEXEC: u32 = 0x10000000; +pub const MPU_RGN_PERM_PRV_NO_USR_NO: u32 = 0x00000000; +pub const MPU_RGN_PERM_PRV_RW_USR_NO: u32 = 0x01000000; +pub const MPU_RGN_PERM_PRV_RW_USR_RO: u32 = 0x02000000; +pub const MPU_RGN_PERM_PRV_RW_USR_RW: u32 = 0x03000000; +pub const MPU_RGN_PERM_PRV_RO_USR_NO: u32 = 0x05000000; +pub const MPU_RGN_PERM_PRV_RO_USR_RO: u32 = 0x06000000; +//***************************************************************************** +// +// Flags for the sub-region to be passed to MPURegionSet. +// +//***************************************************************************** +pub const MPU_SUB_RGN_DISABLE_0: u32 = 0x00000100; +pub const MPU_SUB_RGN_DISABLE_1: u32 = 0x00000200; +pub const MPU_SUB_RGN_DISABLE_2: u32 = 0x00000400; +pub const MPU_SUB_RGN_DISABLE_3: u32 = 0x00000800; +pub const MPU_SUB_RGN_DISABLE_4: u32 = 0x00001000; +pub const MPU_SUB_RGN_DISABLE_5: u32 = 0x00002000; +pub const MPU_SUB_RGN_DISABLE_6: u32 = 0x00004000; +pub const MPU_SUB_RGN_DISABLE_7: u32 = 0x00008000; +//***************************************************************************** +// +// Flags to enable or disable a region, to be passed to MPURegionSet. +// +//***************************************************************************** +pub const MPU_RGN_ENABLE: u32 = 1; +pub const MPU_RGN_DISABLE: u32 = 0; +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// onewire.h - Prototypes for the OneWire Driver. +// +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// \addtogroup onewire_api +// @{ +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Defines used in the OneWireInit() function call. +// +//***************************************************************************** +// +// This define is used in initialization to request standard speed bus +// timings. This is the default. +// +pub const ONEWIRE_INIT_SPD_STD: u32 = 0x00000000; +// +// This define is used in initialization to request overdrive speed bus +// timings. +// +pub const ONEWIRE_INIT_SPD_OD: u32 = 0x00000020; +// +// This define is used in initialization to request standard read sampling +// timing (2us for ONEWIRE_INIT_SPD_OD and 16us for ONEWIRE_INIT_SPD_STD). +// This is the default. +// +pub const ONEWIRE_INIT_READ_STD: u32 = 0x00000000; +// +// This define is used in initialization to request late read sampling +// timing (7us for ONEWIRE_INIT_SPD_OD and 50us for ONEWIRE_INIT_SPD_STD). +// +pub const ONEWIRE_INIT_READ_LATE: u32 = 0x00000040; +// +// This define is used in initialization to request a standard +// Answer-to-Reset (presence detect) monitor. This is the default. +// +pub const ONEWIRE_INIT_ATR: u32 = 0x00000000; +// +// This define is used in initialization to request no Answer-to-Reset +// (presence detect) monitor. The module will delay operations after a bus +// reset for the expected presence detect period in this case. +// +pub const ONEWIRE_INIT_NO_ATR: u32 = 0x00000080; +// +// This define is used in initialization to request standard signal polarity +// on the 1-Wire bus (pin is driven low to drive bus low). This is the +// default. +// +pub const ONEWIRE_INIT_STD_POL: u32 = 0x00000000; +// +// This define is used in initialization to request alternate signal polarity +// on the 1-Wire bus (pin is driven high to drive bus low). +// +pub const ONEWIRE_INIT_ALT_POL: u32 = 0x40000000; +// +// This define is used in initialization to request normal 1-Wire operational +// mode. This is the default. +// +pub const ONEWIRE_INIT_1_WIRE_CFG: u32 = 0x00000000; +// +// This define is used in initialization to request a 2 pin operational +// mode where one pin is used exclusively for TX operations and the other +// for RX. +// +pub const ONEWIRE_INIT_2_WIRE_CFG: u32 = 0x80000000; +//***************************************************************************** +// +// Defines for bus status conditions. These values can be returned by +// OneWireBusStatus(). +// +//***************************************************************************** +// +// This will be set if the bus is busy handling a Read, Write or +// Reset activity. +// +pub const ONEWIRE_BUS_STATUS_BUSY: u32 = 0x00000100; +// +// This will be set if the module did not detect any slave presence pulses +// after a bus reset. +// +pub const ONEWIRE_BUS_STATUS_NO_SLAVE: u32 = 0x00000200; +// +// This will be set if the bus is being held low outside of a normal Read, +// Write or Reset activity. +// +pub const ONEWIRE_BUS_STATUS_STUCK: u32 = 0x00000400; +//***************************************************************************** +// +// OneWire operation modes used with OneWireTransaction(). +// +//***************************************************************************** +// +// This mode flag indicates a single reset should be issued prior to a write +// and/or read operation. +// +pub const ONEWIRE_OP_RESET: u32 = 0x00000001; +// +// This mode flag indicates a read operation. +// +pub const ONEWIRE_OP_READ: u32 = 0x00000002; +// +// This mode flag indicates a write operation. +// +pub const ONEWIRE_OP_WRITE: u32 = 0x00000004; +//***************************************************************************** +// +// OneWire DMA used with OneWireDMAEnable(). +// +//***************************************************************************** +// +// This indicates the DMA should issue a 1-Wire bus reset before starting. +// +pub const ONEWIRE_DMA_BUS_RESET: u32 = 0x00000001; +// +// The DMA operation will be a single Read after each module transaction. +// +pub const ONEWIRE_DMA_OP_READ: u32 = 0x00000002; +// +// The DMA will write values to the 1-Wire interface as each previous DMA +// write operation completes. +// +pub const ONEWIRE_DMA_OP_MULTI_WRITE: u32 = 0x00000004; +// +// The DMA will read values from the 1-Wire interface as each previous DMA +// read operation completes. +// +pub const ONEWIRE_DMA_OP_MULTI_READ: u32 = 0x00000006; +// +// This Scatter Gather DMA mode is paired with ONEWIRE_DMA_OP_READ to instruct +// the 1-Wire DMA to initiate an operation at the start of and then on each +// transition completion thereafter. +// +pub const ONEWIRE_DMA_MODE_SG: u32 = 0x00000008; +// +// DMA expects a Read/Write bus operation size of 8 bits. This should match +// the uDMA channel setup. +// +pub const ONEWIRE_DMA_OP_SZ_8: u32 = 0x00000000; +// +// DMA expects a Read/Write bus operation size of 16 bits. This should match +// the uDMA channel setup. +// +pub const ONEWIRE_DMA_OP_SZ_16: u32 = 0x00000800; +// +// DMA expects a Read/Write bus operation size of 32 bits. This should match +// the uDMA channel setup. +// +pub const ONEWIRE_DMA_OP_SZ_32: u32 = 0x00001800; +//***************************************************************************** +// +// OneWire interrupt defines. Use in calls to OneWireIntEnable(), +// OneWireIntDisable(), OneWireIntClear() and returned by OneWireIntStatus(). +// +//***************************************************************************** +// +// This interrupt indicates a bus reset has just completed. +// +pub const ONEWIRE_INT_RESET_DONE: u32 = 0x00000001; +// +// The interrupt indicates a Read or Write master initiated operation +// has just completed. +// +pub const ONEWIRE_INT_OP_DONE: u32 = 0x00000002; +// +// This interrupt indicates that no presence detect was signaled by a slave +// on the bus after a reset. +// +pub const ONEWIRE_INT_NO_SLAVE: u32 = 0x00000004; +// +// This interrupt indicates the bus is being held low outside of normal +// operations. +// +pub const ONEWIRE_INT_STUCK: u32 = 0x00000008; +// +// This interrupt indicates a OneWire DMA operation has completed. +// +pub const ONEWIRE_INT_DMA_DONE: u32 = 0x00000010; +//***************************************************************************** +// +// Close the Doxygen group. +// @} +// +//***************************************************************************** +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// pin_map.h - Mapping of peripherals to pins for all parts. +// +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +// TM4C123GH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +pub const GPIO_PA0_U0RX: u32 = 0x00000001; +pub const GPIO_PA0_CAN1RX: u32 = 0x00000008; +pub const GPIO_PA1_U0TX: u32 = 0x00000401; +pub const GPIO_PA1_CAN1TX: u32 = 0x00000408; +pub const GPIO_PA2_SSI0CLK: u32 = 0x00000802; +pub const GPIO_PA3_SSI0FSS: u32 = 0x00000C02; +pub const GPIO_PA4_SSI0RX: u32 = 0x00001002; +pub const GPIO_PA5_SSI0TX: u32 = 0x00001402; +pub const GPIO_PA6_I2C1SCL: u32 = 0x00001803; +pub const GPIO_PA6_M1PWM2: u32 = 0x00001805; +pub const GPIO_PA7_I2C1SDA: u32 = 0x00001C03; +pub const GPIO_PA7_M1PWM3: u32 = 0x00001C05; +pub const GPIO_PB0_U1RX: u32 = 0x00010001; +pub const GPIO_PB0_T2CCP0: u32 = 0x00010007; +pub const GPIO_PB1_U1TX: u32 = 0x00010401; +pub const GPIO_PB1_T2CCP1: u32 = 0x00010407; +pub const GPIO_PB2_I2C0SCL: u32 = 0x00010803; +pub const GPIO_PB2_T3CCP0: u32 = 0x00010807; +pub const GPIO_PB3_I2C0SDA: u32 = 0x00010C03; +pub const GPIO_PB3_T3CCP1: u32 = 0x00010C07; +pub const GPIO_PB4_SSI2CLK: u32 = 0x00011002; +pub const GPIO_PB4_M0PWM2: u32 = 0x00011004; +pub const GPIO_PB4_T1CCP0: u32 = 0x00011007; +pub const GPIO_PB4_CAN0RX: u32 = 0x00011008; +pub const GPIO_PB5_SSI2FSS: u32 = 0x00011402; +pub const GPIO_PB5_M0PWM3: u32 = 0x00011404; +pub const GPIO_PB5_T1CCP1: u32 = 0x00011407; +pub const GPIO_PB5_CAN0TX: u32 = 0x00011408; +pub const GPIO_PB6_SSI2RX: u32 = 0x00011802; +pub const GPIO_PB6_M0PWM0: u32 = 0x00011804; +pub const GPIO_PB6_T0CCP0: u32 = 0x00011807; +pub const GPIO_PB7_SSI2TX: u32 = 0x00011C02; +pub const GPIO_PB7_M0PWM1: u32 = 0x00011C04; +pub const GPIO_PB7_T0CCP1: u32 = 0x00011C07; +pub const GPIO_PC0_TCK: u32 = 0x00020001; +pub const GPIO_PC0_SWCLK: u32 = 0x00020001; +pub const GPIO_PC0_T4CCP0: u32 = 0x00020007; +pub const GPIO_PC1_TMS: u32 = 0x00020401; +pub const GPIO_PC1_SWDIO: u32 = 0x00020401; +pub const GPIO_PC1_T4CCP1: u32 = 0x00020407; +pub const GPIO_PC2_TDI: u32 = 0x00020801; +pub const GPIO_PC2_T5CCP0: u32 = 0x00020807; +pub const GPIO_PC3_SWO: u32 = 0x00020C01; +pub const GPIO_PC3_TDO: u32 = 0x00020C01; +pub const GPIO_PC3_T5CCP1: u32 = 0x00020C07; +pub const GPIO_PC4_U4RX: u32 = 0x00021001; +pub const GPIO_PC4_U1RX: u32 = 0x00021002; +pub const GPIO_PC4_M0PWM6: u32 = 0x00021004; +pub const GPIO_PC4_IDX1: u32 = 0x00021006; +pub const GPIO_PC4_WT0CCP0: u32 = 0x00021007; +pub const GPIO_PC4_U1RTS: u32 = 0x00021008; +pub const GPIO_PC5_U4TX: u32 = 0x00021401; +pub const GPIO_PC5_U1TX: u32 = 0x00021402; +pub const GPIO_PC5_M0PWM7: u32 = 0x00021404; +pub const GPIO_PC5_PHA1: u32 = 0x00021406; +pub const GPIO_PC5_WT0CCP1: u32 = 0x00021407; +pub const GPIO_PC5_U1CTS: u32 = 0x00021408; +pub const GPIO_PC6_U3RX: u32 = 0x00021801; +pub const GPIO_PC6_PHB1: u32 = 0x00021806; +pub const GPIO_PC6_WT1CCP0: u32 = 0x00021807; +pub const GPIO_PC6_USB0EPEN: u32 = 0x00021808; +pub const GPIO_PC7_U3TX: u32 = 0x00021C01; +pub const GPIO_PC7_WT1CCP1: u32 = 0x00021C07; +pub const GPIO_PC7_USB0PFLT: u32 = 0x00021C08; +pub const GPIO_PD0_SSI3CLK: u32 = 0x00030001; +pub const GPIO_PD0_SSI1CLK: u32 = 0x00030002; +pub const GPIO_PD0_I2C3SCL: u32 = 0x00030003; +pub const GPIO_PD0_M0PWM6: u32 = 0x00030004; +pub const GPIO_PD0_M1PWM0: u32 = 0x00030005; +pub const GPIO_PD0_WT2CCP0: u32 = 0x00030007; +pub const GPIO_PD1_SSI3FSS: u32 = 0x00030401; +pub const GPIO_PD1_SSI1FSS: u32 = 0x00030402; +pub const GPIO_PD1_I2C3SDA: u32 = 0x00030403; +pub const GPIO_PD1_M0PWM7: u32 = 0x00030404; +pub const GPIO_PD1_M1PWM1: u32 = 0x00030405; +pub const GPIO_PD1_WT2CCP1: u32 = 0x00030407; +pub const GPIO_PD2_SSI3RX: u32 = 0x00030801; +pub const GPIO_PD2_SSI1RX: u32 = 0x00030802; +pub const GPIO_PD2_M0FAULT0: u32 = 0x00030804; +pub const GPIO_PD2_WT3CCP0: u32 = 0x00030807; +pub const GPIO_PD2_USB0EPEN: u32 = 0x00030808; +pub const GPIO_PD3_SSI3TX: u32 = 0x00030C01; +pub const GPIO_PD3_SSI1TX: u32 = 0x00030C02; +pub const GPIO_PD3_IDX0: u32 = 0x00030C06; +pub const GPIO_PD3_WT3CCP1: u32 = 0x00030C07; +pub const GPIO_PD3_USB0PFLT: u32 = 0x00030C08; +pub const GPIO_PD4_U6RX: u32 = 0x00031001; +pub const GPIO_PD4_WT4CCP0: u32 = 0x00031007; +pub const GPIO_PD5_U6TX: u32 = 0x00031401; +pub const GPIO_PD5_WT4CCP1: u32 = 0x00031407; +pub const GPIO_PD6_U2RX: u32 = 0x00031801; +pub const GPIO_PD6_M0FAULT0: u32 = 0x00031804; +pub const GPIO_PD6_PHA0: u32 = 0x00031806; +pub const GPIO_PD6_WT5CCP0: u32 = 0x00031807; +pub const GPIO_PD7_U2TX: u32 = 0x00031C01; +pub const GPIO_PD7_PHB0: u32 = 0x00031C06; +pub const GPIO_PD7_WT5CCP1: u32 = 0x00031C07; +pub const GPIO_PD7_NMI: u32 = 0x00031C08; +pub const GPIO_PE0_U7RX: u32 = 0x00040001; +pub const GPIO_PE1_U7TX: u32 = 0x00040401; +pub const GPIO_PE4_U5RX: u32 = 0x00041001; +pub const GPIO_PE4_I2C2SCL: u32 = 0x00041003; +pub const GPIO_PE4_M0PWM4: u32 = 0x00041004; +pub const GPIO_PE4_M1PWM2: u32 = 0x00041005; +pub const GPIO_PE4_CAN0RX: u32 = 0x00041008; +pub const GPIO_PE5_U5TX: u32 = 0x00041401; +pub const GPIO_PE5_I2C2SDA: u32 = 0x00041403; +pub const GPIO_PE5_M0PWM5: u32 = 0x00041404; +pub const GPIO_PE5_M1PWM3: u32 = 0x00041405; +pub const GPIO_PE5_CAN0TX: u32 = 0x00041408; +pub const GPIO_PF0_U1RTS: u32 = 0x00050001; +pub const GPIO_PF0_SSI1RX: u32 = 0x00050002; +pub const GPIO_PF0_CAN0RX: u32 = 0x00050003; +pub const GPIO_PF0_M1PWM4: u32 = 0x00050005; +pub const GPIO_PF0_PHA0: u32 = 0x00050006; +pub const GPIO_PF0_T0CCP0: u32 = 0x00050007; +pub const GPIO_PF0_NMI: u32 = 0x00050008; +pub const GPIO_PF0_C0O: u32 = 0x00050009; +pub const GPIO_PF1_U1CTS: u32 = 0x00050401; +pub const GPIO_PF1_SSI1TX: u32 = 0x00050402; +pub const GPIO_PF1_M1PWM5: u32 = 0x00050405; +pub const GPIO_PF1_PHB0: u32 = 0x00050406; +pub const GPIO_PF1_T0CCP1: u32 = 0x00050407; +pub const GPIO_PF1_C1O: u32 = 0x00050409; +pub const GPIO_PF1_TRD1: u32 = 0x0005040E; +pub const GPIO_PF2_SSI1CLK: u32 = 0x00050802; +pub const GPIO_PF2_M0FAULT0: u32 = 0x00050804; +pub const GPIO_PF2_M1PWM6: u32 = 0x00050805; +pub const GPIO_PF2_T1CCP0: u32 = 0x00050807; +pub const GPIO_PF2_TRD0: u32 = 0x0005080E; +pub const GPIO_PF3_SSI1FSS: u32 = 0x00050C02; +pub const GPIO_PF3_CAN0TX: u32 = 0x00050C03; +pub const GPIO_PF3_M1PWM7: u32 = 0x00050C05; +pub const GPIO_PF3_T1CCP1: u32 = 0x00050C07; +pub const GPIO_PF3_TRCLK: u32 = 0x00050C0E; +pub const GPIO_PF4_M1FAULT0: u32 = 0x00051005; +pub const GPIO_PF4_IDX0: u32 = 0x00051006; +pub const GPIO_PF4_T2CCP0: u32 = 0x00051007; +pub const GPIO_PF4_USB0EPEN: u32 = 0x00051008; +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ui32Config +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +pub const PWM_GEN_MODE_DOWN: u32 = 0x00000000; // Down count mode +pub const PWM_GEN_MODE_UP_DOWN: u32 = 0x00000002; // Up/Down count mode +pub const PWM_GEN_MODE_SYNC: u32 = 0x00000038; // Synchronous updates +pub const PWM_GEN_MODE_NO_SYNC: u32 = 0x00000000; // Immediate updates +pub const PWM_GEN_MODE_DBG_RUN: u32 = 0x00000004; // Continue running in debug mode +pub const PWM_GEN_MODE_DBG_STOP: u32 = 0x00000000; // Stop running in debug mode +pub const PWM_GEN_MODE_FAULT_LATCHED: u32 = 0x00040000; // Fault is latched +pub const PWM_GEN_MODE_FAULT_UNLATCHED: u32 = 0x00000000; // Fault is not latched +pub const PWM_GEN_MODE_FAULT_MINPER: u32 = 0x00020000; // Enable min fault period +pub const PWM_GEN_MODE_FAULT_NO_MINPER: u32 = 0x00000000; // Disable min fault period +pub const PWM_GEN_MODE_FAULT_EXT: u32 = 0x00010000; // Enable extended fault support +pub const PWM_GEN_MODE_FAULT_LEGACY: u32 = 0x00000000; // Disable extended fault support +pub const PWM_GEN_MODE_DB_NO_SYNC: u32 = 0x00000000; // Deadband updates occur + // immediately +pub const PWM_GEN_MODE_DB_SYNC_LOCAL: u32 = 0x0000A800; // Deadband updates locally + // synchronized +pub const PWM_GEN_MODE_DB_SYNC_GLOBAL: u32 = 0x0000FC00; // Deadband updates globally + // synchronized +pub const PWM_GEN_MODE_GEN_NO_SYNC: u32 = 0x00000000; // Generator mode updates occur + // immediately +pub const PWM_GEN_MODE_GEN_SYNC_LOCAL: u32 = 0x00000280; // Generator mode updates locally + // synchronized +pub const PWM_GEN_MODE_GEN_SYNC_GLOBAL: u32 = 0x000003C0; // Generator mode updates globally + // synchronized +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +pub const PWM_INT_CNT_ZERO: u32 = 0x00000001; // Int if COUNT = 0 +pub const PWM_INT_CNT_LOAD: u32 = 0x00000002; // Int if COUNT = LOAD +pub const PWM_INT_CNT_AU: u32 = 0x00000004; // Int if COUNT = CMPA U +pub const PWM_INT_CNT_AD: u32 = 0x00000008; // Int if COUNT = CMPA D +pub const PWM_INT_CNT_BU: u32 = 0x00000010; // Int if COUNT = CMPA U +pub const PWM_INT_CNT_BD: u32 = 0x00000020; // Int if COUNT = CMPA D +pub const PWM_TR_CNT_ZERO: u32 = 0x00000100; // Trig if COUNT = 0 +pub const PWM_TR_CNT_LOAD: u32 = 0x00000200; // Trig if COUNT = LOAD +pub const PWM_TR_CNT_AU: u32 = 0x00000400; // Trig if COUNT = CMPA U +pub const PWM_TR_CNT_AD: u32 = 0x00000800; // Trig if COUNT = CMPA D +pub const PWM_TR_CNT_BU: u32 = 0x00001000; // Trig if COUNT = CMPA U +pub const PWM_TR_CNT_BD: u32 = 0x00002000; // Trig if COUNT = CMPA D +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +pub const PWM_INT_GEN_0: u32 = 0x00000001; // Generator 0 interrupt +pub const PWM_INT_GEN_1: u32 = 0x00000002; // Generator 1 interrupt +pub const PWM_INT_GEN_2: u32 = 0x00000004; // Generator 2 interrupt +pub const PWM_INT_GEN_3: u32 = 0x00000008; // Generator 3 interrupt +pub const PWM_INT_FAULT0: u32 = 0x00010000; // Fault0 interrupt +pub const PWM_INT_FAULT1: u32 = 0x00020000; // Fault1 interrupt +pub const PWM_INT_FAULT2: u32 = 0x00040000; // Fault2 interrupt +pub const PWM_INT_FAULT3: u32 = 0x00080000; // Fault3 interrupt +pub const PWM_INT_FAULT_M: u32 = 0x000F0000; // Fault interrupt source mask +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +pub const PWM_GEN_0: u32 = 0x00000040; // Offset address of Gen0 +pub const PWM_GEN_1: u32 = 0x00000080; // Offset address of Gen1 +pub const PWM_GEN_2: u32 = 0x000000C0; // Offset address of Gen2 +pub const PWM_GEN_3: u32 = 0x00000100; // Offset address of Gen3 +pub const PWM_GEN_0_BIT: u32 = 0x00000001; // Bit-wise ID for Gen0 +pub const PWM_GEN_1_BIT: u32 = 0x00000002; // Bit-wise ID for Gen1 +pub const PWM_GEN_2_BIT: u32 = 0x00000004; // Bit-wise ID for Gen2 +pub const PWM_GEN_3_BIT: u32 = 0x00000008; // Bit-wise ID for Gen3 +pub const PWM_GEN_EXT_0: u32 = 0x00000800; // Offset of Gen0 ext address range +pub const PWM_GEN_EXT_1: u32 = 0x00000880; // Offset of Gen1 ext address range +pub const PWM_GEN_EXT_2: u32 = 0x00000900; // Offset of Gen2 ext address range +pub const PWM_GEN_EXT_3: u32 = 0x00000980; // Offset of Gen3 ext address range +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +pub const PWM_OUT_0: u32 = 0x00000040; // Encoded offset address of PWM0 +pub const PWM_OUT_1: u32 = 0x00000041; // Encoded offset address of PWM1 +pub const PWM_OUT_2: u32 = 0x00000082; // Encoded offset address of PWM2 +pub const PWM_OUT_3: u32 = 0x00000083; // Encoded offset address of PWM3 +pub const PWM_OUT_4: u32 = 0x000000C4; // Encoded offset address of PWM4 +pub const PWM_OUT_5: u32 = 0x000000C5; // Encoded offset address of PWM5 +pub const PWM_OUT_6: u32 = 0x00000106; // Encoded offset address of PWM6 +pub const PWM_OUT_7: u32 = 0x00000107; // Encoded offset address of PWM7 +pub const PWM_OUT_0_BIT: u32 = 0x00000001; // Bit-wise ID for PWM0 +pub const PWM_OUT_1_BIT: u32 = 0x00000002; // Bit-wise ID for PWM1 +pub const PWM_OUT_2_BIT: u32 = 0x00000004; // Bit-wise ID for PWM2 +pub const PWM_OUT_3_BIT: u32 = 0x00000008; // Bit-wise ID for PWM3 +pub const PWM_OUT_4_BIT: u32 = 0x00000010; // Bit-wise ID for PWM4 +pub const PWM_OUT_5_BIT: u32 = 0x00000020; // Bit-wise ID for PWM5 +pub const PWM_OUT_6_BIT: u32 = 0x00000040; // Bit-wise ID for PWM6 +pub const PWM_OUT_7_BIT: u32 = 0x00000080; // Bit-wise ID for PWM7 +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_0. +// +//***************************************************************************** +pub const PWM_FAULT_GROUP_0: u32 = 0; +pub const PWM_FAULT_FAULT0: u32 = 0x00000001; +pub const PWM_FAULT_FAULT1: u32 = 0x00000002; +pub const PWM_FAULT_FAULT2: u32 = 0x00000004; +pub const PWM_FAULT_FAULT3: u32 = 0x00000008; +pub const PWM_FAULT_ACMP0: u32 = 0x00010000; +pub const PWM_FAULT_ACMP1: u32 = 0x00020000; +pub const PWM_FAULT_ACMP2: u32 = 0x00040000; +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_1. +// +//***************************************************************************** +pub const PWM_FAULT_GROUP_1: u32 = 1; +pub const PWM_FAULT_DCMP0: u32 = 0x00000001; +pub const PWM_FAULT_DCMP1: u32 = 0x00000002; +pub const PWM_FAULT_DCMP2: u32 = 0x00000004; +pub const PWM_FAULT_DCMP3: u32 = 0x00000008; +pub const PWM_FAULT_DCMP4: u32 = 0x00000010; +pub const PWM_FAULT_DCMP5: u32 = 0x00000020; +pub const PWM_FAULT_DCMP6: u32 = 0x00000040; +pub const PWM_FAULT_DCMP7: u32 = 0x00000080; +//***************************************************************************** +// +// Defines to identify the sense of each of the external FAULTn signals +// +//***************************************************************************** +pub const PWM_FAULT0_SENSE_HIGH: u32 = 0x00000000; +pub const PWM_FAULT0_SENSE_LOW: u32 = 0x00000001; +pub const PWM_FAULT1_SENSE_HIGH: u32 = 0x00000000; +pub const PWM_FAULT1_SENSE_LOW: u32 = 0x00000002; +pub const PWM_FAULT2_SENSE_HIGH: u32 = 0x00000000; +pub const PWM_FAULT2_SENSE_LOW: u32 = 0x00000004; +pub const PWM_FAULT3_SENSE_HIGH: u32 = 0x00000000; +pub const PWM_FAULT3_SENSE_LOW: u32 = 0x00000008; +//***************************************************************************** +// +// Defines that can be passed to the PWMClockSet() API as the ui32Config +// parameter, and can be returned by the PWMClockGet() API. +// +//***************************************************************************** +pub const PWM_SYSCLK_DIV_1: u32 = 0x00000000; // PWM clock is system clock +pub const PWM_SYSCLK_DIV_2: u32 = 0x00000100; // PWM clock is system clock /2 +pub const PWM_SYSCLK_DIV_4: u32 = 0x00000101; // PWM clock is system clock /4 +pub const PWM_SYSCLK_DIV_8: u32 = 0x00000102; // PWM clock is system clock /8 +pub const PWM_SYSCLK_DIV_16: u32 = 0x00000103; // PWM clock is system clock /16 +pub const PWM_SYSCLK_DIV_32: u32 = 0x00000104; // PWM clock is system clock /32 +pub const PWM_SYSCLK_DIV_64: u32 = 0x00000105; // PWM clock is system clock /64 +//***************************************************************************** +// +// Defines passed to PWMOutputUpdateMode() to identify the synchronization mode +// to use when enabling or disabling outputs using PWMOutputState(). +// +//***************************************************************************** +pub const PWM_OUTPUT_MODE_NO_SYNC: u32 = 0x00000000; // Updates to occur immediately +pub const PWM_OUTPUT_MODE_SYNC_LOCAL: u32 = 0x00000002; // Updates are locally synchronized +pub const PWM_OUTPUT_MODE_SYNC_GLOBAL: u32 = 0x00000003; // Updates are globally synchronized +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ui32Config paramater. +// +//***************************************************************************** +pub const QEI_CONFIG_CAPTURE_A: u32 = 0x00000000; // Count on ChA edges only +pub const QEI_CONFIG_CAPTURE_A_B: u32 = 0x00000008; // Count on ChA and ChB edges +pub const QEI_CONFIG_NO_RESET: u32 = 0x00000000; // Do not reset on index pulse +pub const QEI_CONFIG_RESET_IDX: u32 = 0x00000010; // Reset position on index pulse +pub const QEI_CONFIG_QUADRATURE: u32 = 0x00000000; // ChA and ChB are quadrature +pub const QEI_CONFIG_CLOCK_DIR: u32 = 0x00000004; // ChA and ChB are clock and dir +pub const QEI_CONFIG_NO_SWAP: u32 = 0x00000000; // Do not swap ChA and ChB +pub const QEI_CONFIG_SWAP: u32 = 0x00000002; // Swap ChA and ChB +//***************************************************************************** +// +// Values that can be passed to QEIFilterConfigure as the ui32PreDiv +// parameter. +// +//***************************************************************************** +pub const QEI_FILTCNT_2: u32 = 0x00000000; // Filter Count of 2 System Clocks +pub const QEI_FILTCNT_3: u32 = 0x00010000; // Filter Count of 3 System Clocks +pub const QEI_FILTCNT_4: u32 = 0x00020000; // Filter Count of 4 System Clocks +pub const QEI_FILTCNT_5: u32 = 0x00030000; // Filter Count of 5 System Clocks +pub const QEI_FILTCNT_6: u32 = 0x00040000; // Filter Count of 6 System Clocks +pub const QEI_FILTCNT_7: u32 = 0x00050000; // Filter Count of 7 System Clocks +pub const QEI_FILTCNT_8: u32 = 0x00060000; // Filter Count of 8 System Clocks +pub const QEI_FILTCNT_9: u32 = 0x00070000; // Filter Count of 9 System Clocks +pub const QEI_FILTCNT_10: u32 = 0x00080000; // Filter Count of 10 System Clocks +pub const QEI_FILTCNT_11: u32 = 0x00090000; // Filter Count of 11 System Clocks +pub const QEI_FILTCNT_12: u32 = 0x000A0000; // Filter Count of 12 System Clocks +pub const QEI_FILTCNT_13: u32 = 0x000B0000; // Filter Count of 13 System Clocks +pub const QEI_FILTCNT_14: u32 = 0x000C0000; // Filter Count of 14 System Clocks +pub const QEI_FILTCNT_15: u32 = 0x000D0000; // Filter Count of 15 System Clocks +pub const QEI_FILTCNT_16: u32 = 0x000E0000; // Filter Count of 16 System Clocks +pub const QEI_FILTCNT_17: u32 = 0x000F0000; // Filter Count of 17 System Clocks +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ui32PreDiv +// parameter. +// +//***************************************************************************** +pub const QEI_VELDIV_1: u32 = 0x00000000; // Predivide by 1 +pub const QEI_VELDIV_2: u32 = 0x00000040; // Predivide by 2 +pub const QEI_VELDIV_4: u32 = 0x00000080; // Predivide by 4 +pub const QEI_VELDIV_8: u32 = 0x000000C0; // Predivide by 8 +pub const QEI_VELDIV_16: u32 = 0x00000100; // Predivide by 16 +pub const QEI_VELDIV_32: u32 = 0x00000140; // Predivide by 32 +pub const QEI_VELDIV_64: u32 = 0x00000180; // Predivide by 64 +pub const QEI_VELDIV_128: u32 = 0x000001C0; // Predivide by 128 +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ui32IntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +pub const QEI_INTERROR: u32 = 0x00000008; // Phase error detected +pub const QEI_INTDIR: u32 = 0x00000004; // Direction change +pub const QEI_INTTIMER: u32 = 0x00000002; // Velocity timer expired +pub const QEI_INTINDEX: u32 = 0x00000001; // Index pulse detected +//***************************************************************************** +//***************************************************************************** +// +// shamd5.h - Defines and Macros for the SHA/MD5. +// +// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// The following defines are used to specify the algorithm in use in the +// SHA/MD5 module. +// +//***************************************************************************** +pub const SHAMD5_ALGO_MD5: u32 = 0x00000018; +pub const SHAMD5_ALGO_SHA1: u32 = 0x0000001a; +pub const SHAMD5_ALGO_SHA224: u32 = 0x0000001c; +pub const SHAMD5_ALGO_SHA256: u32 = 0x0000001e; +pub const SHAMD5_ALGO_HMAC_MD5: u32 = 0x00000000; +pub const SHAMD5_ALGO_HMAC_SHA1: u32 = 0x00000002; +pub const SHAMD5_ALGO_HMAC_SHA224: u32 = 0x00000004; +pub const SHAMD5_ALGO_HMAC_SHA256: u32 = 0x00000006; +//***************************************************************************** +// +// The following defines are used to represent the different interrupt sources +// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and +// SHAMD5BlockOnIntStatus() functions. +// +//***************************************************************************** +pub const SHAMD5_INT_CONTEXT_READY: u32 = 0x00000008; +pub const SHAMD5_INT_PARTHASH_READY: u32 = 0x00000004; +pub const SHAMD5_INT_INPUT_READY: u32 = 0x00000002; +pub const SHAMD5_INT_OUTPUT_READY: u32 = 0x00000001; +pub const SHAMD5_INT_DMA_CONTEXT_IN: u32 = 0x00080000; +pub const SHAMD5_INT_DMA_DATA_IN: u32 = 0x00020000; +pub const SHAMD5_INT_DMA_CONTEXT_OUT: u32 = 0x00010000; +//***************************************************************************** +// +// Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ui32IntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +pub const SSI_TXEOT: u32 = 0x00000040; // Transmit FIFO is empty +pub const SSI_DMATX: u32 = 0x00000020; // DMA Transmit complete +pub const SSI_DMARX: u32 = 0x00000010; // DMA Receive complete +pub const SSI_TXFF: u32 = 0x00000008; // TX FIFO half full or less +pub const SSI_RXFF: u32 = 0x00000004; // RX FIFO half full or more +pub const SSI_RXTO: u32 = 0x00000002; // RX timeout +pub const SSI_RXOR: u32 = 0x00000001; // RX overrun +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +pub const SSI_FRF_MOTO_MODE_0: u32 = 0x00000000; // Moto fmt, polarity 0, phase 0 +pub const SSI_FRF_MOTO_MODE_1: u32 = 0x00000002; // Moto fmt, polarity 0, phase 1 +pub const SSI_FRF_MOTO_MODE_2: u32 = 0x00000001; // Moto fmt, polarity 1, phase 0 +pub const SSI_FRF_MOTO_MODE_3: u32 = 0x00000003; // Moto fmt, polarity 1, phase 1 +pub const SSI_FRF_TI: u32 = 0x00000010; // TI frame format +pub const SSI_FRF_NMW: u32 = 0x00000020; // National MicroWire frame format +pub const SSI_MODE_MASTER: u32 = 0x00000000; // SSI master +pub const SSI_MODE_SLAVE: u32 = 0x00000001; // SSI slave +pub const SSI_MODE_SLAVE_OD: u32 = 0x00000002; // SSI slave with output disabled +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +pub const SSI_DMA_TX: u32 = 0x00000002; // Enable DMA for transmit +pub const SSI_DMA_RX: u32 = 0x00000001; // Enable DMA for receive +//***************************************************************************** +// +// Values that can be passed to SSIClockSourceSet() or returned from +// SSIClockSourceGet(). +// +//***************************************************************************** +pub const SSI_CLOCK_SYSTEM: u32 = 0x00000000; +pub const SSI_CLOCK_PIOSC: u32 = 0x00000005; +//***************************************************************************** +// +// Values that can be passed to SSIAdvModeSet(). +// +//***************************************************************************** +pub const SSI_ADV_MODE_LEGACY: u32 = 0x00000000; +pub const SSI_ADV_MODE_READ_WRITE: u32 = 0x000001c0; +pub const SSI_ADV_MODE_WRITE: u32 = 0x000000c0; +pub const SSI_ADV_MODE_BI_READ: u32 = 0x00000140; +pub const SSI_ADV_MODE_BI_WRITE: u32 = 0x00000040; +pub const SSI_ADV_MODE_QUAD_READ: u32 = 0x00000180; +pub const SSI_ADV_MODE_QUAD_WRITE: u32 = 0x00000080; +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// sw_crc.h - Prototypes for the software CRC functions. +// +// Copyright (c) 2010-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Prototypes for the functions. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ui32Peripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +pub const SYSCTL_PERIPH_ADC0: u32 = 0xf0003800; // ADC 0 +pub const SYSCTL_PERIPH_ADC1: u32 = 0xf0003801; // ADC 1 +pub const SYSCTL_PERIPH_CAN0: u32 = 0xf0003400; // CAN 0 +pub const SYSCTL_PERIPH_CAN1: u32 = 0xf0003401; // CAN 1 +pub const SYSCTL_PERIPH_COMP0: u32 = 0xf0003c00; // Analog Comparator Module 0 +pub const SYSCTL_PERIPH_EMAC0: u32 = 0xf0009c00; // Ethernet MAC0 +pub const SYSCTL_PERIPH_EPHY0: u32 = 0xf0003000; // Ethernet PHY0 +pub const SYSCTL_PERIPH_EPI0: u32 = 0xf0001000; // EPI0 +pub const SYSCTL_PERIPH_GPIOA: u32 = 0xf0000800; // GPIO A +pub const SYSCTL_PERIPH_GPIOB: u32 = 0xf0000801; // GPIO B +pub const SYSCTL_PERIPH_GPIOC: u32 = 0xf0000802; // GPIO C +pub const SYSCTL_PERIPH_GPIOD: u32 = 0xf0000803; // GPIO D +pub const SYSCTL_PERIPH_GPIOE: u32 = 0xf0000804; // GPIO E +pub const SYSCTL_PERIPH_GPIOF: u32 = 0xf0000805; // GPIO F +pub const SYSCTL_PERIPH_GPIOG: u32 = 0xf0000806; // GPIO G +pub const SYSCTL_PERIPH_GPIOH: u32 = 0xf0000807; // GPIO H +pub const SYSCTL_PERIPH_GPIOJ: u32 = 0xf0000808; // GPIO J +pub const SYSCTL_PERIPH_HIBERNATE: u32 = 0xf0001400; // Hibernation module +pub const SYSCTL_PERIPH_CCM0: u32 = 0xf0007400; // CCM 0 +pub const SYSCTL_PERIPH_EEPROM0: u32 = 0xf0005800; // EEPROM 0 +pub const SYSCTL_PERIPH_FAN0: u32 = 0xf0005400; // FAN 0 +pub const SYSCTL_PERIPH_FAN1: u32 = 0xf0005401; // FAN 1 +pub const SYSCTL_PERIPH_GPIOK: u32 = 0xf0000809; // GPIO K +pub const SYSCTL_PERIPH_GPIOL: u32 = 0xf000080a; // GPIO L +pub const SYSCTL_PERIPH_GPIOM: u32 = 0xf000080b; // GPIO M +pub const SYSCTL_PERIPH_GPION: u32 = 0xf000080c; // GPIO N +pub const SYSCTL_PERIPH_GPIOP: u32 = 0xf000080d; // GPIO P +pub const SYSCTL_PERIPH_GPIOQ: u32 = 0xf000080e; // GPIO Q +pub const SYSCTL_PERIPH_GPIOR: u32 = 0xf000080f; // GPIO R +pub const SYSCTL_PERIPH_GPIOS: u32 = 0xf0000810; // GPIO S +pub const SYSCTL_PERIPH_GPIOT: u32 = 0xf0000811; // GPIO T +pub const SYSCTL_PERIPH_I2C0: u32 = 0xf0002000; // I2C 0 +pub const SYSCTL_PERIPH_I2C1: u32 = 0xf0002001; // I2C 1 +pub const SYSCTL_PERIPH_I2C2: u32 = 0xf0002002; // I2C 2 +pub const SYSCTL_PERIPH_I2C3: u32 = 0xf0002003; // I2C 3 +pub const SYSCTL_PERIPH_I2C4: u32 = 0xf0002004; // I2C 4 +pub const SYSCTL_PERIPH_I2C5: u32 = 0xf0002005; // I2C 5 +pub const SYSCTL_PERIPH_I2C6: u32 = 0xf0002006; // I2C 6 +pub const SYSCTL_PERIPH_I2C7: u32 = 0xf0002007; // I2C 7 +pub const SYSCTL_PERIPH_I2C8: u32 = 0xf0002008; // I2C 8 +pub const SYSCTL_PERIPH_I2C9: u32 = 0xf0002009; // I2C 9 +pub const SYSCTL_PERIPH_LCD0: u32 = 0xf0009000; // LCD 0 +pub const SYSCTL_PERIPH_ONEWIRE0: u32 = 0xf0009800; // One Wire 0 +pub const SYSCTL_PERIPH_PWM0: u32 = 0xf0004000; // PWM 0 +pub const SYSCTL_PERIPH_PWM1: u32 = 0xf0004001; // PWM 1 +pub const SYSCTL_PERIPH_QEI0: u32 = 0xf0004400; // QEI 0 +pub const SYSCTL_PERIPH_QEI1: u32 = 0xf0004401; // QEI 1 +pub const SYSCTL_PERIPH_SSI0: u32 = 0xf0001c00; // SSI 0 +pub const SYSCTL_PERIPH_SSI1: u32 = 0xf0001c01; // SSI 1 +pub const SYSCTL_PERIPH_SSI2: u32 = 0xf0001c02; // SSI 2 +pub const SYSCTL_PERIPH_SSI3: u32 = 0xf0001c03; // SSI 3 +pub const SYSCTL_PERIPH_TIMER0: u32 = 0xf0000400; // Timer 0 +pub const SYSCTL_PERIPH_TIMER1: u32 = 0xf0000401; // Timer 1 +pub const SYSCTL_PERIPH_TIMER2: u32 = 0xf0000402; // Timer 2 +pub const SYSCTL_PERIPH_TIMER3: u32 = 0xf0000403; // Timer 3 +pub const SYSCTL_PERIPH_TIMER4: u32 = 0xf0000404; // Timer 4 +pub const SYSCTL_PERIPH_TIMER5: u32 = 0xf0000405; // Timer 5 +pub const SYSCTL_PERIPH_TIMER6: u32 = 0xf0000406; // Timer 6 +pub const SYSCTL_PERIPH_TIMER7: u32 = 0xf0000407; // Timer 7 +pub const SYSCTL_PERIPH_UART0: u32 = 0xf0001800; // UART 0 +pub const SYSCTL_PERIPH_UART1: u32 = 0xf0001801; // UART 1 +pub const SYSCTL_PERIPH_UART2: u32 = 0xf0001802; // UART 2 +pub const SYSCTL_PERIPH_UART3: u32 = 0xf0001803; // UART 3 +pub const SYSCTL_PERIPH_UART4: u32 = 0xf0001804; // UART 4 +pub const SYSCTL_PERIPH_UART5: u32 = 0xf0001805; // UART 5 +pub const SYSCTL_PERIPH_UART6: u32 = 0xf0001806; // UART 6 +pub const SYSCTL_PERIPH_UART7: u32 = 0xf0001807; // UART 7 +pub const SYSCTL_PERIPH_UDMA: u32 = 0xf0000c00; // uDMA +pub const SYSCTL_PERIPH_USB0: u32 = 0xf0002800; // USB 0 +pub const SYSCTL_PERIPH_WDOG0: u32 = 0xf0000000; // Watchdog 0 +pub const SYSCTL_PERIPH_WDOG1: u32 = 0xf0000001; // Watchdog 1 +pub const SYSCTL_PERIPH_WTIMER0: u32 = 0xf0005c00; // Wide Timer 0 +pub const SYSCTL_PERIPH_WTIMER1: u32 = 0xf0005c01; // Wide Timer 1 +pub const SYSCTL_PERIPH_WTIMER2: u32 = 0xf0005c02; // Wide Timer 2 +pub const SYSCTL_PERIPH_WTIMER3: u32 = 0xf0005c03; // Wide Timer 3 +pub const SYSCTL_PERIPH_WTIMER4: u32 = 0xf0005c04; // Wide Timer 4 +pub const SYSCTL_PERIPH_WTIMER5: u32 = 0xf0005c05; // Wide Timer 5 +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSleepSet() and +// SysCtlLDODeepSleepSet() APIs as the ui32Voltage value, or returned by the +// SysCtlLDOSleepGet() and SysCtlLDODeepSleepGet() APIs. +// +//***************************************************************************** +pub const SYSCTL_LDO_0_90V: u32 = 0x80000012; // LDO output of 0.90V +pub const SYSCTL_LDO_0_95V: u32 = 0x80000013; // LDO output of 0.95V +pub const SYSCTL_LDO_1_00V: u32 = 0x80000014; // LDO output of 1.00V +pub const SYSCTL_LDO_1_05V: u32 = 0x80000015; // LDO output of 1.05V +pub const SYSCTL_LDO_1_10V: u32 = 0x80000016; // LDO output of 1.10V +pub const SYSCTL_LDO_1_15V: u32 = 0x80000017; // LDO output of 1.15V +pub const SYSCTL_LDO_1_20V: u32 = 0x80000018; // LDO output of 1.20V +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +pub const SYSCTL_INT_BOR0: u32 = 0x00000800; // VDD under BOR0 +pub const SYSCTL_INT_VDDA_OK: u32 = 0x00000400; // VDDA Power OK +pub const SYSCTL_INT_MOSC_PUP: u32 = 0x00000100; // MOSC power-up interrupt +pub const SYSCTL_INT_USBPLL_LOCK: u32 = 0x00000080; // USB PLL lock interrupt +pub const SYSCTL_INT_PLL_LOCK: u32 = 0x00000040; // PLL lock interrupt +pub const SYSCTL_INT_MOSC_FAIL: u32 = 0x00000008; // Main oscillator failure int +pub const SYSCTL_INT_BOR1: u32 = 0x00000002; // VDD under BOR1 +pub const SYSCTL_INT_BOR: u32 = 0x00000002; // Brown out interrupt +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +pub const SYSCTL_CAUSE_HSRVREQ: u32 = 0x00001000; // Hardware System Service Request +pub const SYSCTL_CAUSE_HIB: u32 = 0x00000040; // Hibernate reset +pub const SYSCTL_CAUSE_WDOG1: u32 = 0x00000020; // Watchdog 1 reset +pub const SYSCTL_CAUSE_SW: u32 = 0x00000010; // Software reset +pub const SYSCTL_CAUSE_WDOG0: u32 = 0x00000008; // Watchdog 0 reset +pub const SYSCTL_CAUSE_WDOG: u32 = SYSCTL_CAUSE_WDOG0; + // Watchdog reset(Deprecated) +pub const SYSCTL_CAUSE_BOR: u32 = 0x00000004; // Brown-out reset +pub const SYSCTL_CAUSE_POR: u32 = 0x00000002; // Power on reset +pub const SYSCTL_CAUSE_EXT: u32 = 0x00000001; // External reset +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ui32Config parameter. +// +//***************************************************************************** +pub const SYSCTL_BOR_RESET: u32 = 0x00000002; // Reset instead of interrupting +pub const SYSCTL_BOR_RESAMPLE: u32 = 0x00000001; // Resample BOR before asserting +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ui32Config parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +pub const SYSCTL_PWMDIV_1: u32 = 0x00000000; // PWM clock is processor clock /1 +pub const SYSCTL_PWMDIV_2: u32 = 0x00100000; // PWM clock is processor clock /2 +pub const SYSCTL_PWMDIV_4: u32 = 0x00120000; // PWM clock is processor clock /4 +pub const SYSCTL_PWMDIV_8: u32 = 0x00140000; // PWM clock is processor clock /8 +pub const SYSCTL_PWMDIV_16: u32 = 0x00160000; // PWM clock is processor clock /16 +pub const SYSCTL_PWMDIV_32: u32 = 0x00180000; // PWM clock is processor clock /32 +pub const SYSCTL_PWMDIV_64: u32 = 0x001A0000; // PWM clock is processor clock /64 +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ui32Config parameter. +// +//***************************************************************************** +pub const SYSCTL_SYSDIV_1: u32 = 0x07800000; // Processor clock is osc/pll /1 +pub const SYSCTL_SYSDIV_2: u32 = 0x00C00000; // Processor clock is osc/pll /2 +pub const SYSCTL_SYSDIV_3: u32 = 0x01400000; // Processor clock is osc/pll /3 +pub const SYSCTL_SYSDIV_4: u32 = 0x01C00000; // Processor clock is osc/pll /4 +pub const SYSCTL_SYSDIV_5: u32 = 0x02400000; // Processor clock is osc/pll /5 +pub const SYSCTL_SYSDIV_6: u32 = 0x02C00000; // Processor clock is osc/pll /6 +pub const SYSCTL_SYSDIV_7: u32 = 0x03400000; // Processor clock is osc/pll /7 +pub const SYSCTL_SYSDIV_8: u32 = 0x03C00000; // Processor clock is osc/pll /8 +pub const SYSCTL_SYSDIV_9: u32 = 0x04400000; // Processor clock is osc/pll /9 +pub const SYSCTL_SYSDIV_10: u32 = 0x04C00000; // Processor clock is osc/pll /10 +pub const SYSCTL_SYSDIV_11: u32 = 0x05400000; // Processor clock is osc/pll /11 +pub const SYSCTL_SYSDIV_12: u32 = 0x05C00000; // Processor clock is osc/pll /12 +pub const SYSCTL_SYSDIV_13: u32 = 0x06400000; // Processor clock is osc/pll /13 +pub const SYSCTL_SYSDIV_14: u32 = 0x06C00000; // Processor clock is osc/pll /14 +pub const SYSCTL_SYSDIV_15: u32 = 0x07400000; // Processor clock is osc/pll /15 +pub const SYSCTL_SYSDIV_16: u32 = 0x07C00000; // Processor clock is osc/pll /16 +pub const SYSCTL_SYSDIV_17: u32 = 0x88400000; // Processor clock is osc/pll /17 +pub const SYSCTL_SYSDIV_18: u32 = 0x88C00000; // Processor clock is osc/pll /18 +pub const SYSCTL_SYSDIV_19: u32 = 0x89400000; // Processor clock is osc/pll /19 +pub const SYSCTL_SYSDIV_20: u32 = 0x89C00000; // Processor clock is osc/pll /20 +pub const SYSCTL_SYSDIV_21: u32 = 0x8A400000; // Processor clock is osc/pll /21 +pub const SYSCTL_SYSDIV_22: u32 = 0x8AC00000; // Processor clock is osc/pll /22 +pub const SYSCTL_SYSDIV_23: u32 = 0x8B400000; // Processor clock is osc/pll /23 +pub const SYSCTL_SYSDIV_24: u32 = 0x8BC00000; // Processor clock is osc/pll /24 +pub const SYSCTL_SYSDIV_25: u32 = 0x8C400000; // Processor clock is osc/pll /25 +pub const SYSCTL_SYSDIV_26: u32 = 0x8CC00000; // Processor clock is osc/pll /26 +pub const SYSCTL_SYSDIV_27: u32 = 0x8D400000; // Processor clock is osc/pll /27 +pub const SYSCTL_SYSDIV_28: u32 = 0x8DC00000; // Processor clock is osc/pll /28 +pub const SYSCTL_SYSDIV_29: u32 = 0x8E400000; // Processor clock is osc/pll /29 +pub const SYSCTL_SYSDIV_30: u32 = 0x8EC00000; // Processor clock is osc/pll /30 +pub const SYSCTL_SYSDIV_31: u32 = 0x8F400000; // Processor clock is osc/pll /31 +pub const SYSCTL_SYSDIV_32: u32 = 0x8FC00000; // Processor clock is osc/pll /32 +pub const SYSCTL_SYSDIV_33: u32 = 0x90400000; // Processor clock is osc/pll /33 +pub const SYSCTL_SYSDIV_34: u32 = 0x90C00000; // Processor clock is osc/pll /34 +pub const SYSCTL_SYSDIV_35: u32 = 0x91400000; // Processor clock is osc/pll /35 +pub const SYSCTL_SYSDIV_36: u32 = 0x91C00000; // Processor clock is osc/pll /36 +pub const SYSCTL_SYSDIV_37: u32 = 0x92400000; // Processor clock is osc/pll /37 +pub const SYSCTL_SYSDIV_38: u32 = 0x92C00000; // Processor clock is osc/pll /38 +pub const SYSCTL_SYSDIV_39: u32 = 0x93400000; // Processor clock is osc/pll /39 +pub const SYSCTL_SYSDIV_40: u32 = 0x93C00000; // Processor clock is osc/pll /40 +pub const SYSCTL_SYSDIV_41: u32 = 0x94400000; // Processor clock is osc/pll /41 +pub const SYSCTL_SYSDIV_42: u32 = 0x94C00000; // Processor clock is osc/pll /42 +pub const SYSCTL_SYSDIV_43: u32 = 0x95400000; // Processor clock is osc/pll /43 +pub const SYSCTL_SYSDIV_44: u32 = 0x95C00000; // Processor clock is osc/pll /44 +pub const SYSCTL_SYSDIV_45: u32 = 0x96400000; // Processor clock is osc/pll /45 +pub const SYSCTL_SYSDIV_46: u32 = 0x96C00000; // Processor clock is osc/pll /46 +pub const SYSCTL_SYSDIV_47: u32 = 0x97400000; // Processor clock is osc/pll /47 +pub const SYSCTL_SYSDIV_48: u32 = 0x97C00000; // Processor clock is osc/pll /48 +pub const SYSCTL_SYSDIV_49: u32 = 0x98400000; // Processor clock is osc/pll /49 +pub const SYSCTL_SYSDIV_50: u32 = 0x98C00000; // Processor clock is osc/pll /50 +pub const SYSCTL_SYSDIV_51: u32 = 0x99400000; // Processor clock is osc/pll /51 +pub const SYSCTL_SYSDIV_52: u32 = 0x99C00000; // Processor clock is osc/pll /52 +pub const SYSCTL_SYSDIV_53: u32 = 0x9A400000; // Processor clock is osc/pll /53 +pub const SYSCTL_SYSDIV_54: u32 = 0x9AC00000; // Processor clock is osc/pll /54 +pub const SYSCTL_SYSDIV_55: u32 = 0x9B400000; // Processor clock is osc/pll /55 +pub const SYSCTL_SYSDIV_56: u32 = 0x9BC00000; // Processor clock is osc/pll /56 +pub const SYSCTL_SYSDIV_57: u32 = 0x9C400000; // Processor clock is osc/pll /57 +pub const SYSCTL_SYSDIV_58: u32 = 0x9CC00000; // Processor clock is osc/pll /58 +pub const SYSCTL_SYSDIV_59: u32 = 0x9D400000; // Processor clock is osc/pll /59 +pub const SYSCTL_SYSDIV_60: u32 = 0x9DC00000; // Processor clock is osc/pll /60 +pub const SYSCTL_SYSDIV_61: u32 = 0x9E400000; // Processor clock is osc/pll /61 +pub const SYSCTL_SYSDIV_62: u32 = 0x9EC00000; // Processor clock is osc/pll /62 +pub const SYSCTL_SYSDIV_63: u32 = 0x9F400000; // Processor clock is osc/pll /63 +pub const SYSCTL_SYSDIV_64: u32 = 0x9FC00000; // Processor clock is osc/pll /64 +pub const SYSCTL_SYSDIV_2_5: u32 = 0xC1000000; // Processor clock is pll / 2.5 +pub const SYSCTL_SYSDIV_3_5: u32 = 0xC1800000; // Processor clock is pll / 3.5 +pub const SYSCTL_SYSDIV_4_5: u32 = 0xC2000000; // Processor clock is pll / 4.5 +pub const SYSCTL_SYSDIV_5_5: u32 = 0xC2800000; // Processor clock is pll / 5.5 +pub const SYSCTL_SYSDIV_6_5: u32 = 0xC3000000; // Processor clock is pll / 6.5 +pub const SYSCTL_SYSDIV_7_5: u32 = 0xC3800000; // Processor clock is pll / 7.5 +pub const SYSCTL_SYSDIV_8_5: u32 = 0xC4000000; // Processor clock is pll / 8.5 +pub const SYSCTL_SYSDIV_9_5: u32 = 0xC4800000; // Processor clock is pll / 9.5 +pub const SYSCTL_SYSDIV_10_5: u32 = 0xC5000000; // Processor clock is pll / 10.5 +pub const SYSCTL_SYSDIV_11_5: u32 = 0xC5800000; // Processor clock is pll / 11.5 +pub const SYSCTL_SYSDIV_12_5: u32 = 0xC6000000; // Processor clock is pll / 12.5 +pub const SYSCTL_SYSDIV_13_5: u32 = 0xC6800000; // Processor clock is pll / 13.5 +pub const SYSCTL_SYSDIV_14_5: u32 = 0xC7000000; // Processor clock is pll / 14.5 +pub const SYSCTL_SYSDIV_15_5: u32 = 0xC7800000; // Processor clock is pll / 15.5 +pub const SYSCTL_SYSDIV_16_5: u32 = 0xC8000000; // Processor clock is pll / 16.5 +pub const SYSCTL_SYSDIV_17_5: u32 = 0xC8800000; // Processor clock is pll / 17.5 +pub const SYSCTL_SYSDIV_18_5: u32 = 0xC9000000; // Processor clock is pll / 18.5 +pub const SYSCTL_SYSDIV_19_5: u32 = 0xC9800000; // Processor clock is pll / 19.5 +pub const SYSCTL_SYSDIV_20_5: u32 = 0xCA000000; // Processor clock is pll / 20.5 +pub const SYSCTL_SYSDIV_21_5: u32 = 0xCA800000; // Processor clock is pll / 21.5 +pub const SYSCTL_SYSDIV_22_5: u32 = 0xCB000000; // Processor clock is pll / 22.5 +pub const SYSCTL_SYSDIV_23_5: u32 = 0xCB800000; // Processor clock is pll / 23.5 +pub const SYSCTL_SYSDIV_24_5: u32 = 0xCC000000; // Processor clock is pll / 24.5 +pub const SYSCTL_SYSDIV_25_5: u32 = 0xCC800000; // Processor clock is pll / 25.5 +pub const SYSCTL_SYSDIV_26_5: u32 = 0xCD000000; // Processor clock is pll / 26.5 +pub const SYSCTL_SYSDIV_27_5: u32 = 0xCD800000; // Processor clock is pll / 27.5 +pub const SYSCTL_SYSDIV_28_5: u32 = 0xCE000000; // Processor clock is pll / 28.5 +pub const SYSCTL_SYSDIV_29_5: u32 = 0xCE800000; // Processor clock is pll / 29.5 +pub const SYSCTL_SYSDIV_30_5: u32 = 0xCF000000; // Processor clock is pll / 30.5 +pub const SYSCTL_SYSDIV_31_5: u32 = 0xCF800000; // Processor clock is pll / 31.5 +pub const SYSCTL_SYSDIV_32_5: u32 = 0xD0000000; // Processor clock is pll / 32.5 +pub const SYSCTL_SYSDIV_33_5: u32 = 0xD0800000; // Processor clock is pll / 33.5 +pub const SYSCTL_SYSDIV_34_5: u32 = 0xD1000000; // Processor clock is pll / 34.5 +pub const SYSCTL_SYSDIV_35_5: u32 = 0xD1800000; // Processor clock is pll / 35.5 +pub const SYSCTL_SYSDIV_36_5: u32 = 0xD2000000; // Processor clock is pll / 36.5 +pub const SYSCTL_SYSDIV_37_5: u32 = 0xD2800000; // Processor clock is pll / 37.5 +pub const SYSCTL_SYSDIV_38_5: u32 = 0xD3000000; // Processor clock is pll / 38.5 +pub const SYSCTL_SYSDIV_39_5: u32 = 0xD3800000; // Processor clock is pll / 39.5 +pub const SYSCTL_SYSDIV_40_5: u32 = 0xD4000000; // Processor clock is pll / 40.5 +pub const SYSCTL_SYSDIV_41_5: u32 = 0xD4800000; // Processor clock is pll / 41.5 +pub const SYSCTL_SYSDIV_42_5: u32 = 0xD5000000; // Processor clock is pll / 42.5 +pub const SYSCTL_SYSDIV_43_5: u32 = 0xD5800000; // Processor clock is pll / 43.5 +pub const SYSCTL_SYSDIV_44_5: u32 = 0xD6000000; // Processor clock is pll / 44.5 +pub const SYSCTL_SYSDIV_45_5: u32 = 0xD6800000; // Processor clock is pll / 45.5 +pub const SYSCTL_SYSDIV_46_5: u32 = 0xD7000000; // Processor clock is pll / 46.5 +pub const SYSCTL_SYSDIV_47_5: u32 = 0xD7800000; // Processor clock is pll / 47.5 +pub const SYSCTL_SYSDIV_48_5: u32 = 0xD8000000; // Processor clock is pll / 48.5 +pub const SYSCTL_SYSDIV_49_5: u32 = 0xD8800000; // Processor clock is pll / 49.5 +pub const SYSCTL_SYSDIV_50_5: u32 = 0xD9000000; // Processor clock is pll / 50.5 +pub const SYSCTL_SYSDIV_51_5: u32 = 0xD9800000; // Processor clock is pll / 51.5 +pub const SYSCTL_SYSDIV_52_5: u32 = 0xDA000000; // Processor clock is pll / 52.5 +pub const SYSCTL_SYSDIV_53_5: u32 = 0xDA800000; // Processor clock is pll / 53.5 +pub const SYSCTL_SYSDIV_54_5: u32 = 0xDB000000; // Processor clock is pll / 54.5 +pub const SYSCTL_SYSDIV_55_5: u32 = 0xDB800000; // Processor clock is pll / 55.5 +pub const SYSCTL_SYSDIV_56_5: u32 = 0xDC000000; // Processor clock is pll / 56.5 +pub const SYSCTL_SYSDIV_57_5: u32 = 0xDC800000; // Processor clock is pll / 57.5 +pub const SYSCTL_SYSDIV_58_5: u32 = 0xDD000000; // Processor clock is pll / 58.5 +pub const SYSCTL_SYSDIV_59_5: u32 = 0xDD800000; // Processor clock is pll / 59.5 +pub const SYSCTL_SYSDIV_60_5: u32 = 0xDE000000; // Processor clock is pll / 60.5 +pub const SYSCTL_SYSDIV_61_5: u32 = 0xDE800000; // Processor clock is pll / 61.5 +pub const SYSCTL_SYSDIV_62_5: u32 = 0xDF000000; // Processor clock is pll / 62.5 +pub const SYSCTL_SYSDIV_63_5: u32 = 0xDF800000; // Processor clock is pll / 63.5 +// +// TivaWare 2.2.0.xxx Update +// Due to TM4C129x Errata Item SYSCTL#22, the SYSCTL_CFG_VCO_xxx configurations +// have misleading *names* as currently defined as the VCO does not run at the +// stated frequencies. To amend this, new *name* defintions are being used, +// however the register configuration remains the same. +// The old definitions will remain for compatibility with code ported from +// older versions of TivaWare. +// +pub const SYSCTL_CFG_VCO_480: u32 = 0xF1000000; // VCO is 480 MHz - Legacy + // Does not work @ 480, use + // SYSCTL_CFG_VCO_240 instead +pub const SYSCTL_CFG_VCO_320: u32 = 0xF0000000; // VCO is 320 MHz - Legacy + // Does not work @ 320, use + // SYSCTL_CFG_VCO_160 instead +pub const SYSCTL_CFG_VCO_240: u32 = 0xF1000000; // VCO is 240 MHz +pub const SYSCTL_CFG_VCO_160: u32 = 0xF0000000; // VCO is 160 MHz +pub const SYSCTL_USE_PLL: u32 = 0x00000000; // System clock is the PLL clock +pub const SYSCTL_USE_OSC: u32 = 0x00003800; // System clock is the osc clock +pub const SYSCTL_XTAL_1MHZ: u32 = 0x00000000; // External crystal is 1MHz +pub const SYSCTL_XTAL_1_84MHZ: u32 = 0x00000040; // External crystal is 1.8432MHz +pub const SYSCTL_XTAL_2MHZ: u32 = 0x00000080; // External crystal is 2MHz +pub const SYSCTL_XTAL_2_45MHZ: u32 = 0x000000C0; // External crystal is 2.4576MHz +pub const SYSCTL_XTAL_3_57MHZ: u32 = 0x00000100; // External crystal is 3.579545MHz +pub const SYSCTL_XTAL_3_68MHZ: u32 = 0x00000140; // External crystal is 3.6864MHz +pub const SYSCTL_XTAL_4MHZ: u32 = 0x00000180; // External crystal is 4MHz +pub const SYSCTL_XTAL_4_09MHZ: u32 = 0x000001C0; // External crystal is 4.096MHz +pub const SYSCTL_XTAL_4_91MHZ: u32 = 0x00000200; // External crystal is 4.9152MHz +pub const SYSCTL_XTAL_5MHZ: u32 = 0x00000240; // External crystal is 5MHz +pub const SYSCTL_XTAL_5_12MHZ: u32 = 0x00000280; // External crystal is 5.12MHz +pub const SYSCTL_XTAL_6MHZ: u32 = 0x000002C0; // External crystal is 6MHz +pub const SYSCTL_XTAL_6_14MHZ: u32 = 0x00000300; // External crystal is 6.144MHz +pub const SYSCTL_XTAL_7_37MHZ: u32 = 0x00000340; // External crystal is 7.3728MHz +pub const SYSCTL_XTAL_8MHZ: u32 = 0x00000380; // External crystal is 8MHz +pub const SYSCTL_XTAL_8_19MHZ: u32 = 0x000003C0; // External crystal is 8.192MHz +pub const SYSCTL_XTAL_10MHZ: u32 = 0x00000400; // External crystal is 10 MHz +pub const SYSCTL_XTAL_12MHZ: u32 = 0x00000440; // External crystal is 12 MHz +pub const SYSCTL_XTAL_12_2MHZ: u32 = 0x00000480; // External crystal is 12.288 MHz +pub const SYSCTL_XTAL_13_5MHZ: u32 = 0x000004C0; // External crystal is 13.56 MHz +pub const SYSCTL_XTAL_14_3MHZ: u32 = 0x00000500; // External crystal is 14.31818 MHz +pub const SYSCTL_XTAL_16MHZ: u32 = 0x00000540; // External crystal is 16 MHz +pub const SYSCTL_XTAL_16_3MHZ: u32 = 0x00000580; // External crystal is 16.384 MHz +pub const SYSCTL_XTAL_18MHZ: u32 = 0x000005C0; // External crystal is 18.0 MHz +pub const SYSCTL_XTAL_20MHZ: u32 = 0x00000600; // External crystal is 20.0 MHz +pub const SYSCTL_XTAL_24MHZ: u32 = 0x00000640; // External crystal is 24.0 MHz +pub const SYSCTL_XTAL_25MHZ: u32 = 0x00000680; // External crystal is 25.0 MHz +pub const SYSCTL_OSC_MAIN: u32 = 0x00000000; // Osc source is main osc +pub const SYSCTL_OSC_INT: u32 = 0x00000010; // Osc source is int. osc +pub const SYSCTL_OSC_INT4: u32 = 0x00000020; // Osc source is int. osc /4 +pub const SYSCTL_OSC_INT30: u32 = 0x00000030; // Osc source is int. 30 KHz +pub const SYSCTL_OSC_EXT32: u32 = 0x80000038; // Osc source is ext. 32 KHz +pub const SYSCTL_INT_OSC_DIS: u32 = 0x00000002; // Disable internal oscillator +pub const SYSCTL_MAIN_OSC_DIS: u32 = 0x00000001; // Disable main oscillator +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlDeepSleepClockSet() +// API as the ui32Config parameter. +// +//***************************************************************************** +pub const SYSCTL_DSLP_DIV_1: u32 = 0x00000000; // Deep-sleep clock is osc /1 +pub const SYSCTL_DSLP_DIV_2: u32 = 0x00800000; // Deep-sleep clock is osc /2 +pub const SYSCTL_DSLP_DIV_3: u32 = 0x01000000; // Deep-sleep clock is osc /3 +pub const SYSCTL_DSLP_DIV_4: u32 = 0x01800000; // Deep-sleep clock is osc /4 +pub const SYSCTL_DSLP_DIV_5: u32 = 0x02000000; // Deep-sleep clock is osc /5 +pub const SYSCTL_DSLP_DIV_6: u32 = 0x02800000; // Deep-sleep clock is osc /6 +pub const SYSCTL_DSLP_DIV_7: u32 = 0x03000000; // Deep-sleep clock is osc /7 +pub const SYSCTL_DSLP_DIV_8: u32 = 0x03800000; // Deep-sleep clock is osc /8 +pub const SYSCTL_DSLP_DIV_9: u32 = 0x04000000; // Deep-sleep clock is osc /9 +pub const SYSCTL_DSLP_DIV_10: u32 = 0x04800000; // Deep-sleep clock is osc /10 +pub const SYSCTL_DSLP_DIV_11: u32 = 0x05000000; // Deep-sleep clock is osc /11 +pub const SYSCTL_DSLP_DIV_12: u32 = 0x05800000; // Deep-sleep clock is osc /12 +pub const SYSCTL_DSLP_DIV_13: u32 = 0x06000000; // Deep-sleep clock is osc /13 +pub const SYSCTL_DSLP_DIV_14: u32 = 0x06800000; // Deep-sleep clock is osc /14 +pub const SYSCTL_DSLP_DIV_15: u32 = 0x07000000; // Deep-sleep clock is osc /15 +pub const SYSCTL_DSLP_DIV_16: u32 = 0x07800000; // Deep-sleep clock is osc /16 +pub const SYSCTL_DSLP_DIV_17: u32 = 0x08000000; // Deep-sleep clock is osc /17 +pub const SYSCTL_DSLP_DIV_18: u32 = 0x08800000; // Deep-sleep clock is osc /18 +pub const SYSCTL_DSLP_DIV_19: u32 = 0x09000000; // Deep-sleep clock is osc /19 +pub const SYSCTL_DSLP_DIV_20: u32 = 0x09800000; // Deep-sleep clock is osc /20 +pub const SYSCTL_DSLP_DIV_21: u32 = 0x0A000000; // Deep-sleep clock is osc /21 +pub const SYSCTL_DSLP_DIV_22: u32 = 0x0A800000; // Deep-sleep clock is osc /22 +pub const SYSCTL_DSLP_DIV_23: u32 = 0x0B000000; // Deep-sleep clock is osc /23 +pub const SYSCTL_DSLP_DIV_24: u32 = 0x0B800000; // Deep-sleep clock is osc /24 +pub const SYSCTL_DSLP_DIV_25: u32 = 0x0C000000; // Deep-sleep clock is osc /25 +pub const SYSCTL_DSLP_DIV_26: u32 = 0x0C800000; // Deep-sleep clock is osc /26 +pub const SYSCTL_DSLP_DIV_27: u32 = 0x0D000000; // Deep-sleep clock is osc /27 +pub const SYSCTL_DSLP_DIV_28: u32 = 0x0D800000; // Deep-sleep clock is osc /28 +pub const SYSCTL_DSLP_DIV_29: u32 = 0x0E000000; // Deep-sleep clock is osc /29 +pub const SYSCTL_DSLP_DIV_30: u32 = 0x0E800000; // Deep-sleep clock is osc /30 +pub const SYSCTL_DSLP_DIV_31: u32 = 0x0F000000; // Deep-sleep clock is osc /31 +pub const SYSCTL_DSLP_DIV_32: u32 = 0x0F800000; // Deep-sleep clock is osc /32 +pub const SYSCTL_DSLP_DIV_33: u32 = 0x10000000; // Deep-sleep clock is osc /33 +pub const SYSCTL_DSLP_DIV_34: u32 = 0x10800000; // Deep-sleep clock is osc /34 +pub const SYSCTL_DSLP_DIV_35: u32 = 0x11000000; // Deep-sleep clock is osc /35 +pub const SYSCTL_DSLP_DIV_36: u32 = 0x11800000; // Deep-sleep clock is osc /36 +pub const SYSCTL_DSLP_DIV_37: u32 = 0x12000000; // Deep-sleep clock is osc /37 +pub const SYSCTL_DSLP_DIV_38: u32 = 0x12800000; // Deep-sleep clock is osc /38 +pub const SYSCTL_DSLP_DIV_39: u32 = 0x13000000; // Deep-sleep clock is osc /39 +pub const SYSCTL_DSLP_DIV_40: u32 = 0x13800000; // Deep-sleep clock is osc /40 +pub const SYSCTL_DSLP_DIV_41: u32 = 0x14000000; // Deep-sleep clock is osc /41 +pub const SYSCTL_DSLP_DIV_42: u32 = 0x14800000; // Deep-sleep clock is osc /42 +pub const SYSCTL_DSLP_DIV_43: u32 = 0x15000000; // Deep-sleep clock is osc /43 +pub const SYSCTL_DSLP_DIV_44: u32 = 0x15800000; // Deep-sleep clock is osc /44 +pub const SYSCTL_DSLP_DIV_45: u32 = 0x16000000; // Deep-sleep clock is osc /45 +pub const SYSCTL_DSLP_DIV_46: u32 = 0x16800000; // Deep-sleep clock is osc /46 +pub const SYSCTL_DSLP_DIV_47: u32 = 0x17000000; // Deep-sleep clock is osc /47 +pub const SYSCTL_DSLP_DIV_48: u32 = 0x17800000; // Deep-sleep clock is osc /48 +pub const SYSCTL_DSLP_DIV_49: u32 = 0x18000000; // Deep-sleep clock is osc /49 +pub const SYSCTL_DSLP_DIV_50: u32 = 0x18800000; // Deep-sleep clock is osc /50 +pub const SYSCTL_DSLP_DIV_51: u32 = 0x19000000; // Deep-sleep clock is osc /51 +pub const SYSCTL_DSLP_DIV_52: u32 = 0x19800000; // Deep-sleep clock is osc /52 +pub const SYSCTL_DSLP_DIV_53: u32 = 0x1A000000; // Deep-sleep clock is osc /53 +pub const SYSCTL_DSLP_DIV_54: u32 = 0x1A800000; // Deep-sleep clock is osc /54 +pub const SYSCTL_DSLP_DIV_55: u32 = 0x1B000000; // Deep-sleep clock is osc /55 +pub const SYSCTL_DSLP_DIV_56: u32 = 0x1B800000; // Deep-sleep clock is osc /56 +pub const SYSCTL_DSLP_DIV_57: u32 = 0x1C000000; // Deep-sleep clock is osc /57 +pub const SYSCTL_DSLP_DIV_58: u32 = 0x1C800000; // Deep-sleep clock is osc /58 +pub const SYSCTL_DSLP_DIV_59: u32 = 0x1D000000; // Deep-sleep clock is osc /59 +pub const SYSCTL_DSLP_DIV_60: u32 = 0x1D800000; // Deep-sleep clock is osc /60 +pub const SYSCTL_DSLP_DIV_61: u32 = 0x1E000000; // Deep-sleep clock is osc /61 +pub const SYSCTL_DSLP_DIV_62: u32 = 0x1E800000; // Deep-sleep clock is osc /62 +pub const SYSCTL_DSLP_DIV_63: u32 = 0x1F000000; // Deep-sleep clock is osc /63 +pub const SYSCTL_DSLP_DIV_64: u32 = 0x1F800000; // Deep-sleep clock is osc /64 +pub const SYSCTL_DSLP_OSC_MAIN: u32 = 0x00000000; // Osc source is main osc +pub const SYSCTL_DSLP_OSC_INT: u32 = 0x00000010; // Osc source is int. osc +pub const SYSCTL_DSLP_OSC_INT30: u32 = 0x00000030; // Osc source is int. 30 KHz +pub const SYSCTL_DSLP_OSC_EXT32: u32 = 0x00000070; // Osc source is ext. 32 KHz +pub const SYSCTL_DSLP_PIOSC_PD: u32 = 0x00000002; // Power down PIOSC in deep-sleep +pub const SYSCTL_DSLP_MOSC_PD: u32 = 0x40000000; // Power down MOSC in deep-sleep +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPIOSCCalibrate() +// API as the ui32Type parameter. +// +//***************************************************************************** +pub const SYSCTL_PIOSC_CAL_AUTO: u32 = 0x00000200; // Automatic calibration +pub const SYSCTL_PIOSC_CAL_FACT: u32 = 0x00000100; // Factory calibration +pub const SYSCTL_PIOSC_CAL_USER: u32 = 0x80000100; // User-supplied calibration +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlMOSCConfigSet() API +// as the ui32Config parameter. +// +//***************************************************************************** +pub const SYSCTL_MOSC_VALIDATE: u32 = 0x00000001; // Enable MOSC validation +pub const SYSCTL_MOSC_INTERRUPT: u32 = 0x00000002; // Generate interrupt on MOSC fail +pub const SYSCTL_MOSC_NO_XTAL: u32 = 0x00000004; // No crystal is attached to MOSC +pub const SYSCTL_MOSC_PWR_DIS: u32 = 0x00000008; // Power down the MOSC. +pub const SYSCTL_MOSC_LOWFREQ: u32 = 0x00000000; // MOSC is less than 10MHz +pub const SYSCTL_MOSC_HIGHFREQ: u32 = 0x00000010; // MOSC is greater than 10MHz +pub const SYSCTL_MOSC_SESRC: u32 = 0x00000020; // Singled ended oscillator source. +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlSleepPowerSet() and +// SysCtlDeepSleepPowerSet() APIs as the ui32Config parameter. +// +//***************************************************************************** +pub const SYSCTL_LDO_SLEEP: u32 = 0x00000200; // LDO in sleep mode + // (Deep Sleep Only) +pub const SYSCTL_TEMP_LOW_POWER: u32 = 0x00000100; // Temp sensor in low power mode + // (Deep Sleep Only) +pub const SYSCTL_FLASH_NORMAL: u32 = 0x00000000; // Flash in normal mode +pub const SYSCTL_FLASH_LOW_POWER: u32 = 0x00000020; // Flash in low power mode +pub const SYSCTL_SRAM_NORMAL: u32 = 0x00000000; // SRAM in normal mode +pub const SYSCTL_SRAM_STANDBY: u32 = 0x00000001; // SRAM in standby mode +pub const SYSCTL_SRAM_LOW_POWER: u32 = 0x00000003; // SRAM in low power mode +//***************************************************************************** +// +// Defines for the SysCtlResetBehaviorSet() and SysCtlResetBehaviorGet() APIs. +// +//***************************************************************************** +pub const SYSCTL_ONRST_WDOG0_POR: u32 = 0x00000030; +pub const SYSCTL_ONRST_WDOG0_SYS: u32 = 0x00000020; +pub const SYSCTL_ONRST_WDOG1_POR: u32 = 0x000000C0; +pub const SYSCTL_ONRST_WDOG1_SYS: u32 = 0x00000080; +pub const SYSCTL_ONRST_BOR_POR: u32 = 0x0000000C; +pub const SYSCTL_ONRST_BOR_SYS: u32 = 0x00000008; +pub const SYSCTL_ONRST_EXT_POR: u32 = 0x00000003; +pub const SYSCTL_ONRST_EXT_SYS: u32 = 0x00000002; +//***************************************************************************** +// +// Values used with the SysCtlVoltageEventConfig() API. +// +//***************************************************************************** +pub const SYSCTL_VEVENT_VDDABO_NONE: u32 = 0x00000000; +pub const SYSCTL_VEVENT_VDDABO_INT: u32 = 0x00000100; +pub const SYSCTL_VEVENT_VDDABO_NMI: u32 = 0x00000200; +pub const SYSCTL_VEVENT_VDDABO_RST: u32 = 0x00000300; +pub const SYSCTL_VEVENT_VDDBO_NONE: u32 = 0x00000000; +pub const SYSCTL_VEVENT_VDDBO_INT: u32 = 0x00000001; +pub const SYSCTL_VEVENT_VDDBO_NMI: u32 = 0x00000002; +pub const SYSCTL_VEVENT_VDDBO_RST: u32 = 0x00000003; +//***************************************************************************** +// +// Values used with the SysCtlVoltageEventStatus() and +// SysCtlVoltageEventClear() APIs. +// +//***************************************************************************** +pub const SYSCTL_VESTAT_VDDBOR: u32 = 0x00000040; +pub const SYSCTL_VESTAT_VDDABOR: u32 = 0x00000010; +//***************************************************************************** +// +// Values used with the SysCtlNMIStatus() API. +// +//***************************************************************************** +pub const SYSCTL_NMI_MOSCFAIL: u32 = 0x00010000; +pub const SYSCTL_NMI_TAMPER: u32 = 0x00000200; +pub const SYSCTL_NMI_WDT1: u32 = 0x00000020; +pub const SYSCTL_NMI_WDT0: u32 = 0x00000008; +pub const SYSCTL_NMI_POWER: u32 = 0x00000004; +pub const SYSCTL_NMI_EXTERNAL: u32 = 0x00000001; +//***************************************************************************** +// +// The defines for the SysCtlClockOutConfig() API. +// +//***************************************************************************** +pub const SYSCTL_CLKOUT_EN: u32 = 0x80000000; +pub const SYSCTL_CLKOUT_DIS: u32 = 0x00000000; +pub const SYSCTL_CLKOUT_SYSCLK: u32 = 0x00000000; +pub const SYSCTL_CLKOUT_PIOSC: u32 = 0x00010000; +pub const SYSCTL_CLKOUT_MOSC: u32 = 0x00020000; +//***************************************************************************** +// +// The following defines are used with the SysCtlAltClkConfig() function. +// +//***************************************************************************** +pub const SYSCTL_ALTCLK_PIOSC: u32 = 0x00000000; +pub const SYSCTL_ALTCLK_RTCOSC: u32 = 0x00000003; +pub const SYSCTL_ALTCLK_LFIOSC: u32 = 0x00000004; +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// sysexc.h - Prototypes for the System Exception Module routines. +// +// Copyright (c) 2011-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and +// SysExcIntClear as the ui32IntFlags parameter, and returned from +// SysExcIntStatus. +// +//***************************************************************************** +pub const SYSEXC_INT_FP_IXC: u32 = 0x00000020; // FP Inexact exception interrupt +pub const SYSEXC_INT_FP_OFC: u32 = 0x00000010; // FP Overflow exception interrupt +pub const SYSEXC_INT_FP_UFC: u32 = 0x00000008; // FP Underflow exception interrupt +pub const SYSEXC_INT_FP_IOC: u32 = 0x00000004; // FP Invalid operation interrupt +pub const SYSEXC_INT_FP_DZC: u32 = 0x00000002; // FP Divide by zero exception int +pub const SYSEXC_INT_FP_IDC: u32 = 0x00000001; // FP Input denormal exception int +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ui32Config parameter. +// +//***************************************************************************** +pub const TIMER_CFG_ONE_SHOT: u32 = 0x00000021; // Full-width one-shot timer +pub const TIMER_CFG_ONE_SHOT_UP: u32 = 0x00000031; // Full-width one-shot up-count + // timer +pub const TIMER_CFG_PERIODIC: u32 = 0x00000022; // Full-width periodic timer +pub const TIMER_CFG_PERIODIC_UP: u32 = 0x00000032; // Full-width periodic up-count + // timer +pub const TIMER_CFG_RTC: u32 = 0x01000000; // Full-width RTC timer +pub const TIMER_CFG_SPLIT_PAIR: u32 = 0x04000000; // Two half-width timers +pub const TIMER_CFG_A_ONE_SHOT: u32 = 0x00000021; // Timer A one-shot timer +pub const TIMER_CFG_A_ONE_SHOT_UP: u32 = 0x00000031; // Timer A one-shot up-count timer +pub const TIMER_CFG_A_PERIODIC: u32 = 0x00000022; // Timer A periodic timer +pub const TIMER_CFG_A_PERIODIC_UP: u32 = 0x00000032; // Timer A periodic up-count timer +pub const TIMER_CFG_A_CAP_COUNT: u32 = 0x00000003; // Timer A event counter +pub const TIMER_CFG_A_CAP_COUNT_UP: u32 = 0x00000013; // Timer A event up-counter +pub const TIMER_CFG_A_CAP_TIME: u32 = 0x00000007; // Timer A event timer +pub const TIMER_CFG_A_CAP_TIME_UP: u32 = 0x00000017; // Timer A event up-count timer +pub const TIMER_CFG_A_ONE_SHOT_PWM: u32 = 0x00000009; // Timer A one-shot PWM output +pub const TIMER_CFG_A_PWM: u32 = 0x0000000A; // Timer A PWM output +pub const TIMER_CFG_B_ONE_SHOT: u32 = 0x00002100; // Timer B one-shot timer +pub const TIMER_CFG_B_ONE_SHOT_UP: u32 = 0x00003100; // Timer B one-shot up-count timer +pub const TIMER_CFG_B_PERIODIC: u32 = 0x00002200; // Timer B periodic timer +pub const TIMER_CFG_B_PERIODIC_UP: u32 = 0x00003200; // Timer B periodic up-count timer +pub const TIMER_CFG_B_CAP_COUNT: u32 = 0x00000300; // Timer B event counter +pub const TIMER_CFG_B_CAP_COUNT_UP: u32 = 0x00001300; // Timer B event up-counter +pub const TIMER_CFG_B_CAP_TIME: u32 = 0x00000700; // Timer B event timer +pub const TIMER_CFG_B_CAP_TIME_UP: u32 = 0x00001700; // Timer B event up-count timer +pub const TIMER_CFG_B_ONE_SHOT_PWM: u32 = 0x00000900; // Timer B one-shot PWM output +pub const TIMER_CFG_B_PWM: u32 = 0x00000A00; // Timer B PWM output +pub const TIMER_CFG_A_ACT_TOINTD: u32 = 0x00010000; // Timer A compare action disable + // time-out interrupt. +pub const TIMER_CFG_A_ACT_NONE: u32 = 0x00000000; // Timer A compare action none. +pub const TIMER_CFG_A_ACT_TOGGLE: u32 = 0x00020000; // Timer A compare action toggle. +pub const TIMER_CFG_A_ACT_CLRTO: u32 = 0x00040000; // Timer A compare action CCP + // clear on time-out. +pub const TIMER_CFG_A_ACT_SETTO: u32 = 0x00060000; // Timer A compare action CCP set + // on time-out. +pub const TIMER_CFG_A_ACT_SETTOGTO: u32 = 0x00080000; // Timer A compare action set CCP + // toggle on time-out. +pub const TIMER_CFG_A_ACT_CLRTOGTO: u32 = 0x000A0000; // Timer A compare action clear + // CCP toggle on time-out. +pub const TIMER_CFG_A_ACT_SETCLRTO: u32 = 0x000C0000; // Timer A compare action set CCP + // clear on time-out. +pub const TIMER_CFG_A_ACT_CLRSETTO: u32 = 0x000E0000; // Timer A compare action clear + // CCP set on time-out. +pub const TIMER_CFG_B_ACT_TOINTD: u32 = 0x00100000; // Timer B compare action disable + // time-out interrupt. +pub const TIMER_CFG_B_ACT_NONE: u32 = 0x00000000; // Timer A compare action none. +pub const TIMER_CFG_B_ACT_TOGGLE: u32 = 0x00200000; // Timer A compare action toggle. +pub const TIMER_CFG_B_ACT_CLRTO: u32 = 0x00400000; // Timer A compare action CCP + // clear on time-out. +pub const TIMER_CFG_B_ACT_SETTO: u32 = 0x00600000; // Timer A compare action CCP set + // on time-out. +pub const TIMER_CFG_B_ACT_SETTOGTO: u32 = 0x00800000; // Timer A compare action set CCP + // toggle on time-out. +pub const TIMER_CFG_B_ACT_CLRTOGTO: u32 = 0x00A00000; // Timer A compare action clear + // CCP toggle on time-out. +pub const TIMER_CFG_B_ACT_SETCLRTO: u32 = 0x00C00000; // Timer A compare action set CCP + // clear on time-out. +pub const TIMER_CFG_B_ACT_CLRSETTO: u32 = 0x0000E000; // Timer A compare action clear + // CCP set on time-out. +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ui32IntFlags parameter, and returned from +// TimerIntStatus. +// +//***************************************************************************** +pub const TIMER_TIMB_DMA: u32 = 0x00002000; // TimerB DMA Complete Interrupt. +pub const TIMER_TIMB_MATCH: u32 = 0x00000800; // TimerB match interrupt +pub const TIMER_CAPB_EVENT: u32 = 0x00000400; // CaptureB event interrupt +pub const TIMER_CAPB_MATCH: u32 = 0x00000200; // CaptureB match interrupt +pub const TIMER_TIMB_TIMEOUT: u32 = 0x00000100; // TimerB time out interrupt +pub const TIMER_TIMA_DMA: u32 = 0x00000020; // TimerA DMA Complete Interrupt. +pub const TIMER_TIMA_MATCH: u32 = 0x00000010; // TimerA match interrupt +pub const TIMER_RTC_MATCH: u32 = 0x00000008; // RTC interrupt mask +pub const TIMER_CAPA_EVENT: u32 = 0x00000004; // CaptureA event interrupt +pub const TIMER_CAPA_MATCH: u32 = 0x00000002; // CaptureA match interrupt +pub const TIMER_TIMA_TIMEOUT: u32 = 0x00000001; // TimerA time out interrupt +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ui32Event parameter. +// +//***************************************************************************** +pub const TIMER_EVENT_POS_EDGE: u32 = 0x00000000; // Count positive edges +pub const TIMER_EVENT_NEG_EDGE: u32 = 0x00000404; // Count negative edges +pub const TIMER_EVENT_BOTH_EDGES: u32 = 0x00000C0C; // Count both edges +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ui32Timer +// parameter. +// +//***************************************************************************** +pub const TIMER_A: u32 = 0x000000ff; // Timer A +pub const TIMER_B: u32 = 0x0000ff00; // Timer B +pub const TIMER_BOTH: u32 = 0x0000ffff; // Timer Both +//***************************************************************************** +// +// Values that can be passed to TimerSynchronize as the ui32Timers parameter. +// +//***************************************************************************** +pub const TIMER_0A_SYNC: u32 = 0x00000001; // Synchronize Timer 0A +pub const TIMER_0B_SYNC: u32 = 0x00000002; // Synchronize Timer 0B +pub const TIMER_1A_SYNC: u32 = 0x00000004; // Synchronize Timer 1A +pub const TIMER_1B_SYNC: u32 = 0x00000008; // Synchronize Timer 1B +pub const TIMER_2A_SYNC: u32 = 0x00000010; // Synchronize Timer 2A +pub const TIMER_2B_SYNC: u32 = 0x00000020; // Synchronize Timer 2B +pub const TIMER_3A_SYNC: u32 = 0x00000040; // Synchronize Timer 3A +pub const TIMER_3B_SYNC: u32 = 0x00000080; // Synchronize Timer 3B +pub const TIMER_4A_SYNC: u32 = 0x00000100; // Synchronize Timer 4A +pub const TIMER_4B_SYNC: u32 = 0x00000200; // Synchronize Timer 4B +pub const TIMER_5A_SYNC: u32 = 0x00000400; // Synchronize Timer 5A +pub const TIMER_5B_SYNC: u32 = 0x00000800; // Synchronize Timer 5B +pub const WTIMER_0A_SYNC: u32 = 0x00001000; // Synchronize Wide Timer 0A +pub const WTIMER_0B_SYNC: u32 = 0x00002000; // Synchronize Wide Timer 0B +pub const WTIMER_1A_SYNC: u32 = 0x00004000; // Synchronize Wide Timer 1A +pub const WTIMER_1B_SYNC: u32 = 0x00008000; // Synchronize Wide Timer 1B +pub const WTIMER_2A_SYNC: u32 = 0x00010000; // Synchronize Wide Timer 2A +pub const WTIMER_2B_SYNC: u32 = 0x00020000; // Synchronize Wide Timer 2B +pub const WTIMER_3A_SYNC: u32 = 0x00040000; // Synchronize Wide Timer 3A +pub const WTIMER_3B_SYNC: u32 = 0x00080000; // Synchronize Wide Timer 3B +pub const WTIMER_4A_SYNC: u32 = 0x00100000; // Synchronize Wide Timer 4A +pub const WTIMER_4B_SYNC: u32 = 0x00200000; // Synchronize Wide Timer 4B +pub const WTIMER_5A_SYNC: u32 = 0x00400000; // Synchronize Wide Timer 5A +pub const WTIMER_5B_SYNC: u32 = 0x00800000; // Synchronize Wide Timer 5B +//***************************************************************************** +// +// Values that can be passed to TimerClockSourceSet() or returned from +// TimerClockSourceGet(). +// +//***************************************************************************** +pub const TIMER_CLOCK_SYSTEM: u32 = 0x00000000; +pub const TIMER_CLOCK_PIOSC: u32 = 0x00000001; +//***************************************************************************** +// +// Values that can be passed to TimerDMAEventSet() or returned from +// TimerDMAEventGet(). +// +//***************************************************************************** +pub const TIMER_DMA_MODEMATCH_B: u32 = 0x00000800; +pub const TIMER_DMA_CAPEVENT_B: u32 = 0x00000400; +pub const TIMER_DMA_CAPMATCH_B: u32 = 0x00000200; +pub const TIMER_DMA_TIMEOUT_B: u32 = 0x00000100; +pub const TIMER_DMA_MODEMATCH_A: u32 = 0x00000010; +pub const TIMER_DMA_RTC_A: u32 = 0x00000008; +pub const TIMER_DMA_CAPEVENT_A: u32 = 0x00000004; +pub const TIMER_DMA_CAPMATCH_A: u32 = 0x00000002; +pub const TIMER_DMA_TIMEOUT_A: u32 = 0x00000001; +//***************************************************************************** +// +// Values that can be passed to TimerADCEventSet() or returned from +// TimerADCEventGet(). +// +//***************************************************************************** +pub const TIMER_ADC_MODEMATCH_B: u32 = 0x00000800; +pub const TIMER_ADC_CAPEVENT_B: u32 = 0x00000400; +pub const TIMER_ADC_CAPMATCH_B: u32 = 0x00000200; +pub const TIMER_ADC_TIMEOUT_B: u32 = 0x00000100; +pub const TIMER_ADC_MODEMATCH_A: u32 = 0x00000010; +pub const TIMER_ADC_RTC_A: u32 = 0x00000008; +pub const TIMER_ADC_CAPEVENT_A: u32 = 0x00000004; +pub const TIMER_ADC_CAPMATCH_A: u32 = 0x00000002; +pub const TIMER_ADC_TIMEOUT_A: u32 = 0x00000001; +//***************************************************************************** +// +// Values that can be passed to TimerUpdateMode(). +// +//***************************************************************************** +pub const TIMER_UP_LOAD_IMMEDIATE: u32 = 0x00000000; +pub const TIMER_UP_LOAD_TIMEOUT: u32 = 0x00000100; +pub const TIMER_UP_MATCH_IMMEDIATE: u32 = 0x00000000; +pub const TIMER_UP_MATCH_TIMEOUT: u32 = 0x00000400; +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// tm4c123gh6pm.h - TM4C123GH6PM Register Definitions +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt assignments +// +//***************************************************************************** +pub const INT_GPIOA: u32 = 16; // GPIO Port A +pub const INT_GPIOB: u32 = 17; // GPIO Port B +pub const INT_GPIOC: u32 = 18; // GPIO Port C +pub const INT_GPIOD: u32 = 19; // GPIO Port D +pub const INT_GPIOE: u32 = 20; // GPIO Port E +pub const INT_UART0: u32 = 21; // UART0 +pub const INT_UART1: u32 = 22; // UART1 +pub const INT_SSI0: u32 = 23; // SSI0 +pub const INT_I2C0: u32 = 24; // I2C0 +pub const INT_PWM0_FAULT: u32 = 25; // PWM0 Fault +pub const INT_PWM0_0: u32 = 26; // PWM0 Generator 0 +pub const INT_PWM0_1: u32 = 27; // PWM0 Generator 1 +pub const INT_PWM0_2: u32 = 28; // PWM0 Generator 2 +pub const INT_QEI0: u32 = 29; // QEI0 +pub const INT_ADC0SS0: u32 = 30; // ADC0 Sequence 0 +pub const INT_ADC0SS1: u32 = 31; // ADC0 Sequence 1 +pub const INT_ADC0SS2: u32 = 32; // ADC0 Sequence 2 +pub const INT_ADC0SS3: u32 = 33; // ADC0 Sequence 3 +pub const INT_WATCHDOG: u32 = 34; // Watchdog Timers 0 and 1 +pub const INT_TIMER0A: u32 = 35; // 16/32-Bit Timer 0A +pub const INT_TIMER0B: u32 = 36; // 16/32-Bit Timer 0B +pub const INT_TIMER1A: u32 = 37; // 16/32-Bit Timer 1A +pub const INT_TIMER1B: u32 = 38; // 16/32-Bit Timer 1B +pub const INT_TIMER2A: u32 = 39; // 16/32-Bit Timer 2A +pub const INT_TIMER2B: u32 = 40; // 16/32-Bit Timer 2B +pub const INT_COMP0: u32 = 41; // Analog Comparator 0 +pub const INT_COMP1: u32 = 42; // Analog Comparator 1 +pub const INT_SYSCTL: u32 = 44; // System Control +pub const INT_FLASH: u32 = 45; // Flash Memory Control and EEPROM + // Control +pub const INT_GPIOF: u32 = 46; // GPIO Port F +pub const INT_UART2: u32 = 49; // UART2 +pub const INT_SSI1: u32 = 50; // SSI1 +pub const INT_TIMER3A: u32 = 51; // 16/32-Bit Timer 3A +pub const INT_TIMER3B: u32 = 52; // Timer 3B +pub const INT_I2C1: u32 = 53; // I2C1 +pub const INT_QEI1: u32 = 54; // QEI1 +pub const INT_CAN0: u32 = 55; // CAN0 +pub const INT_CAN1: u32 = 56; // CAN1 +pub const INT_HIBERNATE: u32 = 59; // Hibernation Module +pub const INT_USB0: u32 = 60; // USB +pub const INT_PWM0_3: u32 = 61; // PWM Generator 3 +pub const INT_UDMA: u32 = 62; // uDMA Software +pub const INT_UDMAERR: u32 = 63; // uDMA Error +pub const INT_ADC1SS0: u32 = 64; // ADC1 Sequence 0 +pub const INT_ADC1SS1: u32 = 65; // ADC1 Sequence 1 +pub const INT_ADC1SS2: u32 = 66; // ADC1 Sequence 2 +pub const INT_ADC1SS3: u32 = 67; // ADC1 Sequence 3 +pub const INT_SSI2: u32 = 73; // SSI2 +pub const INT_SSI3: u32 = 74; // SSI3 +pub const INT_UART3: u32 = 75; // UART3 +pub const INT_UART4: u32 = 76; // UART4 +pub const INT_UART5: u32 = 77; // UART5 +pub const INT_UART6: u32 = 78; // UART6 +pub const INT_UART7: u32 = 79; // UART7 +pub const INT_I2C2: u32 = 84; // I2C2 +pub const INT_I2C3: u32 = 85; // I2C3 +pub const INT_TIMER4A: u32 = 86; // 16/32-Bit Timer 4A +pub const INT_TIMER4B: u32 = 87; // 16/32-Bit Timer 4B +pub const INT_TIMER5A: u32 = 108; // 16/32-Bit Timer 5A +pub const INT_TIMER5B: u32 = 109; // 16/32-Bit Timer 5B +pub const INT_WTIMER0A: u32 = 110; // 32/64-Bit Timer 0A +pub const INT_WTIMER0B: u32 = 111; // 32/64-Bit Timer 0B +pub const INT_WTIMER1A: u32 = 112; // 32/64-Bit Timer 1A +pub const INT_WTIMER1B: u32 = 113; // 32/64-Bit Timer 1B +pub const INT_WTIMER2A: u32 = 114; // 32/64-Bit Timer 2A +pub const INT_WTIMER2B: u32 = 115; // 32/64-Bit Timer 2B +pub const INT_WTIMER3A: u32 = 116; // 32/64-Bit Timer 3A +pub const INT_WTIMER3B: u32 = 117; // 32/64-Bit Timer 3B +pub const INT_WTIMER4A: u32 = 118; // 32/64-Bit Timer 4A +pub const INT_WTIMER4B: u32 = 119; // 32/64-Bit Timer 4B +pub const INT_WTIMER5A: u32 = 120; // 32/64-Bit Timer 5A +pub const INT_WTIMER5B: u32 = 121; // 32/64-Bit Timer 5B +pub const INT_SYSEXC: u32 = 122; // System Exception (imprecise) +pub const INT_PWM1_0: u32 = 150; // PWM1 Generator 0 +pub const INT_PWM1_1: u32 = 151; // PWM1 Generator 1 +pub const INT_PWM1_2: u32 = 152; // PWM1 Generator 2 +pub const INT_PWM1_3: u32 = 153; // PWM1 Generator 3 +pub const INT_PWM1_FAULT: u32 = 154; // PWM1 Fault +//***************************************************************************** +// +// Watchdog Timer registers (WATCHDOG0) +// +//***************************************************************************** +pub const WATCHDOG0_LOAD_R: u32 = 0x40000000; +pub const WATCHDOG0_VALUE_R: u32 = 0x40000004; +pub const WATCHDOG0_CTL_R: u32 = 0x40000008; +pub const WATCHDOG0_ICR_R: u32 = 0x4000000C; +pub const WATCHDOG0_RIS_R: u32 = 0x40000010; +pub const WATCHDOG0_MIS_R: u32 = 0x40000014; +pub const WATCHDOG0_TEST_R: u32 = 0x40000418; +pub const WATCHDOG0_LOCK_R: u32 = 0x40000C00; +//***************************************************************************** +// +// Watchdog Timer registers (WATCHDOG1) +// +//***************************************************************************** +pub const WATCHDOG1_LOAD_R: u32 = 0x40001000; +pub const WATCHDOG1_VALUE_R: u32 = 0x40001004; +pub const WATCHDOG1_CTL_R: u32 = 0x40001008; +pub const WATCHDOG1_ICR_R: u32 = 0x4000100C; +pub const WATCHDOG1_RIS_R: u32 = 0x40001010; +pub const WATCHDOG1_MIS_R: u32 = 0x40001014; +pub const WATCHDOG1_TEST_R: u32 = 0x40001418; +pub const WATCHDOG1_LOCK_R: u32 = 0x40001C00; +//***************************************************************************** +// +// GPIO registers (PORTA) +// +//***************************************************************************** +pub const GPIO_PORTA_DATA_BITS_R: u32 = 0x40004000; +pub const GPIO_PORTA_DATA_R: u32 = 0x400043FC; +pub const GPIO_PORTA_DIR_R: u32 = 0x40004400; +pub const GPIO_PORTA_IS_R: u32 = 0x40004404; +pub const GPIO_PORTA_IBE_R: u32 = 0x40004408; +pub const GPIO_PORTA_IEV_R: u32 = 0x4000440C; +pub const GPIO_PORTA_IM_R: u32 = 0x40004410; +pub const GPIO_PORTA_RIS_R: u32 = 0x40004414; +pub const GPIO_PORTA_MIS_R: u32 = 0x40004418; +pub const GPIO_PORTA_ICR_R: u32 = 0x4000441C; +pub const GPIO_PORTA_AFSEL_R: u32 = 0x40004420; +pub const GPIO_PORTA_DR2R_R: u32 = 0x40004500; +pub const GPIO_PORTA_DR4R_R: u32 = 0x40004504; +pub const GPIO_PORTA_DR8R_R: u32 = 0x40004508; +pub const GPIO_PORTA_ODR_R: u32 = 0x4000450C; +pub const GPIO_PORTA_PUR_R: u32 = 0x40004510; +pub const GPIO_PORTA_PDR_R: u32 = 0x40004514; +pub const GPIO_PORTA_SLR_R: u32 = 0x40004518; +pub const GPIO_PORTA_DEN_R: u32 = 0x4000451C; +pub const GPIO_PORTA_LOCK_R: u32 = 0x40004520; +pub const GPIO_PORTA_CR_R: u32 = 0x40004524; +pub const GPIO_PORTA_AMSEL_R: u32 = 0x40004528; +pub const GPIO_PORTA_PCTL_R: u32 = 0x4000452C; +pub const GPIO_PORTA_ADCCTL_R: u32 = 0x40004530; +pub const GPIO_PORTA_DMACTL_R: u32 = 0x40004534; +//***************************************************************************** +// +// GPIO registers (PORTB) +// +//***************************************************************************** +pub const GPIO_PORTB_DATA_BITS_R: u32 = 0x40005000; +pub const GPIO_PORTB_DATA_R: u32 = 0x400053FC; +pub const GPIO_PORTB_DIR_R: u32 = 0x40005400; +pub const GPIO_PORTB_IS_R: u32 = 0x40005404; +pub const GPIO_PORTB_IBE_R: u32 = 0x40005408; +pub const GPIO_PORTB_IEV_R: u32 = 0x4000540C; +pub const GPIO_PORTB_IM_R: u32 = 0x40005410; +pub const GPIO_PORTB_RIS_R: u32 = 0x40005414; +pub const GPIO_PORTB_MIS_R: u32 = 0x40005418; +pub const GPIO_PORTB_ICR_R: u32 = 0x4000541C; +pub const GPIO_PORTB_AFSEL_R: u32 = 0x40005420; +pub const GPIO_PORTB_DR2R_R: u32 = 0x40005500; +pub const GPIO_PORTB_DR4R_R: u32 = 0x40005504; +pub const GPIO_PORTB_DR8R_R: u32 = 0x40005508; +pub const GPIO_PORTB_ODR_R: u32 = 0x4000550C; +pub const GPIO_PORTB_PUR_R: u32 = 0x40005510; +pub const GPIO_PORTB_PDR_R: u32 = 0x40005514; +pub const GPIO_PORTB_SLR_R: u32 = 0x40005518; +pub const GPIO_PORTB_DEN_R: u32 = 0x4000551C; +pub const GPIO_PORTB_LOCK_R: u32 = 0x40005520; +pub const GPIO_PORTB_CR_R: u32 = 0x40005524; +pub const GPIO_PORTB_AMSEL_R: u32 = 0x40005528; +pub const GPIO_PORTB_PCTL_R: u32 = 0x4000552C; +pub const GPIO_PORTB_ADCCTL_R: u32 = 0x40005530; +pub const GPIO_PORTB_DMACTL_R: u32 = 0x40005534; +//***************************************************************************** +// +// GPIO registers (PORTC) +// +//***************************************************************************** +pub const GPIO_PORTC_DATA_BITS_R: u32 = 0x40006000; +pub const GPIO_PORTC_DATA_R: u32 = 0x400063FC; +pub const GPIO_PORTC_DIR_R: u32 = 0x40006400; +pub const GPIO_PORTC_IS_R: u32 = 0x40006404; +pub const GPIO_PORTC_IBE_R: u32 = 0x40006408; +pub const GPIO_PORTC_IEV_R: u32 = 0x4000640C; +pub const GPIO_PORTC_IM_R: u32 = 0x40006410; +pub const GPIO_PORTC_RIS_R: u32 = 0x40006414; +pub const GPIO_PORTC_MIS_R: u32 = 0x40006418; +pub const GPIO_PORTC_ICR_R: u32 = 0x4000641C; +pub const GPIO_PORTC_AFSEL_R: u32 = 0x40006420; +pub const GPIO_PORTC_DR2R_R: u32 = 0x40006500; +pub const GPIO_PORTC_DR4R_R: u32 = 0x40006504; +pub const GPIO_PORTC_DR8R_R: u32 = 0x40006508; +pub const GPIO_PORTC_ODR_R: u32 = 0x4000650C; +pub const GPIO_PORTC_PUR_R: u32 = 0x40006510; +pub const GPIO_PORTC_PDR_R: u32 = 0x40006514; +pub const GPIO_PORTC_SLR_R: u32 = 0x40006518; +pub const GPIO_PORTC_DEN_R: u32 = 0x4000651C; +pub const GPIO_PORTC_LOCK_R: u32 = 0x40006520; +pub const GPIO_PORTC_CR_R: u32 = 0x40006524; +pub const GPIO_PORTC_AMSEL_R: u32 = 0x40006528; +pub const GPIO_PORTC_PCTL_R: u32 = 0x4000652C; +pub const GPIO_PORTC_ADCCTL_R: u32 = 0x40006530; +pub const GPIO_PORTC_DMACTL_R: u32 = 0x40006534; +//***************************************************************************** +// +// GPIO registers (PORTD) +// +//***************************************************************************** +pub const GPIO_PORTD_DATA_BITS_R: u32 = 0x40007000; +pub const GPIO_PORTD_DATA_R: u32 = 0x400073FC; +pub const GPIO_PORTD_DIR_R: u32 = 0x40007400; +pub const GPIO_PORTD_IS_R: u32 = 0x40007404; +pub const GPIO_PORTD_IBE_R: u32 = 0x40007408; +pub const GPIO_PORTD_IEV_R: u32 = 0x4000740C; +pub const GPIO_PORTD_IM_R: u32 = 0x40007410; +pub const GPIO_PORTD_RIS_R: u32 = 0x40007414; +pub const GPIO_PORTD_MIS_R: u32 = 0x40007418; +pub const GPIO_PORTD_ICR_R: u32 = 0x4000741C; +pub const GPIO_PORTD_AFSEL_R: u32 = 0x40007420; +pub const GPIO_PORTD_DR2R_R: u32 = 0x40007500; +pub const GPIO_PORTD_DR4R_R: u32 = 0x40007504; +pub const GPIO_PORTD_DR8R_R: u32 = 0x40007508; +pub const GPIO_PORTD_ODR_R: u32 = 0x4000750C; +pub const GPIO_PORTD_PUR_R: u32 = 0x40007510; +pub const GPIO_PORTD_PDR_R: u32 = 0x40007514; +pub const GPIO_PORTD_SLR_R: u32 = 0x40007518; +pub const GPIO_PORTD_DEN_R: u32 = 0x4000751C; +pub const GPIO_PORTD_LOCK_R: u32 = 0x40007520; +pub const GPIO_PORTD_CR_R: u32 = 0x40007524; +pub const GPIO_PORTD_AMSEL_R: u32 = 0x40007528; +pub const GPIO_PORTD_PCTL_R: u32 = 0x4000752C; +pub const GPIO_PORTD_ADCCTL_R: u32 = 0x40007530; +pub const GPIO_PORTD_DMACTL_R: u32 = 0x40007534; +//***************************************************************************** +// +// SSI registers (SSI0) +// +//***************************************************************************** +pub const SSI0_CR0_R: u32 = 0x40008000; +pub const SSI0_CR1_R: u32 = 0x40008004; +pub const SSI0_DR_R: u32 = 0x40008008; +pub const SSI0_SR_R: u32 = 0x4000800C; +pub const SSI0_CPSR_R: u32 = 0x40008010; +pub const SSI0_IM_R: u32 = 0x40008014; +pub const SSI0_RIS_R: u32 = 0x40008018; +pub const SSI0_MIS_R: u32 = 0x4000801C; +pub const SSI0_ICR_R: u32 = 0x40008020; +pub const SSI0_DMACTL_R: u32 = 0x40008024; +pub const SSI0_CC_R: u32 = 0x40008FC8; +//***************************************************************************** +// +// SSI registers (SSI1) +// +//***************************************************************************** +pub const SSI1_CR0_R: u32 = 0x40009000; +pub const SSI1_CR1_R: u32 = 0x40009004; +pub const SSI1_DR_R: u32 = 0x40009008; +pub const SSI1_SR_R: u32 = 0x4000900C; +pub const SSI1_CPSR_R: u32 = 0x40009010; +pub const SSI1_IM_R: u32 = 0x40009014; +pub const SSI1_RIS_R: u32 = 0x40009018; +pub const SSI1_MIS_R: u32 = 0x4000901C; +pub const SSI1_ICR_R: u32 = 0x40009020; +pub const SSI1_DMACTL_R: u32 = 0x40009024; +pub const SSI1_CC_R: u32 = 0x40009FC8; +//***************************************************************************** +// +// SSI registers (SSI2) +// +//***************************************************************************** +pub const SSI2_CR0_R: u32 = 0x4000A000; +pub const SSI2_CR1_R: u32 = 0x4000A004; +pub const SSI2_DR_R: u32 = 0x4000A008; +pub const SSI2_SR_R: u32 = 0x4000A00C; +pub const SSI2_CPSR_R: u32 = 0x4000A010; +pub const SSI2_IM_R: u32 = 0x4000A014; +pub const SSI2_RIS_R: u32 = 0x4000A018; +pub const SSI2_MIS_R: u32 = 0x4000A01C; +pub const SSI2_ICR_R: u32 = 0x4000A020; +pub const SSI2_DMACTL_R: u32 = 0x4000A024; +pub const SSI2_CC_R: u32 = 0x4000AFC8; +//***************************************************************************** +// +// SSI registers (SSI3) +// +//***************************************************************************** +pub const SSI3_CR0_R: u32 = 0x4000B000; +pub const SSI3_CR1_R: u32 = 0x4000B004; +pub const SSI3_DR_R: u32 = 0x4000B008; +pub const SSI3_SR_R: u32 = 0x4000B00C; +pub const SSI3_CPSR_R: u32 = 0x4000B010; +pub const SSI3_IM_R: u32 = 0x4000B014; +pub const SSI3_RIS_R: u32 = 0x4000B018; +pub const SSI3_MIS_R: u32 = 0x4000B01C; +pub const SSI3_ICR_R: u32 = 0x4000B020; +pub const SSI3_DMACTL_R: u32 = 0x4000B024; +pub const SSI3_CC_R: u32 = 0x4000BFC8; +//***************************************************************************** +// +// UART registers (UART0) +// +//***************************************************************************** +pub const UART0_DR_R: u32 = 0x4000C000; +pub const UART0_RSR_R: u32 = 0x4000C004; +pub const UART0_ECR_R: u32 = 0x4000C004; +pub const UART0_FR_R: u32 = 0x4000C018; +pub const UART0_ILPR_R: u32 = 0x4000C020; +pub const UART0_IBRD_R: u32 = 0x4000C024; +pub const UART0_FBRD_R: u32 = 0x4000C028; +pub const UART0_LCRH_R: u32 = 0x4000C02C; +pub const UART0_CTL_R: u32 = 0x4000C030; +pub const UART0_IFLS_R: u32 = 0x4000C034; +pub const UART0_IM_R: u32 = 0x4000C038; +pub const UART0_RIS_R: u32 = 0x4000C03C; +pub const UART0_MIS_R: u32 = 0x4000C040; +pub const UART0_ICR_R: u32 = 0x4000C044; +pub const UART0_DMACTL_R: u32 = 0x4000C048; +pub const UART0_9BITADDR_R: u32 = 0x4000C0A4; +pub const UART0_9BITAMASK_R: u32 = 0x4000C0A8; +pub const UART0_PP_R: u32 = 0x4000CFC0; +pub const UART0_CC_R: u32 = 0x4000CFC8; +//***************************************************************************** +// +// UART registers (UART1) +// +//***************************************************************************** +pub const UART1_DR_R: u32 = 0x4000D000; +pub const UART1_RSR_R: u32 = 0x4000D004; +pub const UART1_ECR_R: u32 = 0x4000D004; +pub const UART1_FR_R: u32 = 0x4000D018; +pub const UART1_ILPR_R: u32 = 0x4000D020; +pub const UART1_IBRD_R: u32 = 0x4000D024; +pub const UART1_FBRD_R: u32 = 0x4000D028; +pub const UART1_LCRH_R: u32 = 0x4000D02C; +pub const UART1_CTL_R: u32 = 0x4000D030; +pub const UART1_IFLS_R: u32 = 0x4000D034; +pub const UART1_IM_R: u32 = 0x4000D038; +pub const UART1_RIS_R: u32 = 0x4000D03C; +pub const UART1_MIS_R: u32 = 0x4000D040; +pub const UART1_ICR_R: u32 = 0x4000D044; +pub const UART1_DMACTL_R: u32 = 0x4000D048; +pub const UART1_9BITADDR_R: u32 = 0x4000D0A4; +pub const UART1_9BITAMASK_R: u32 = 0x4000D0A8; +pub const UART1_PP_R: u32 = 0x4000DFC0; +pub const UART1_CC_R: u32 = 0x4000DFC8; +//***************************************************************************** +// +// UART registers (UART2) +// +//***************************************************************************** +pub const UART2_DR_R: u32 = 0x4000E000; +pub const UART2_RSR_R: u32 = 0x4000E004; +pub const UART2_ECR_R: u32 = 0x4000E004; +pub const UART2_FR_R: u32 = 0x4000E018; +pub const UART2_ILPR_R: u32 = 0x4000E020; +pub const UART2_IBRD_R: u32 = 0x4000E024; +pub const UART2_FBRD_R: u32 = 0x4000E028; +pub const UART2_LCRH_R: u32 = 0x4000E02C; +pub const UART2_CTL_R: u32 = 0x4000E030; +pub const UART2_IFLS_R: u32 = 0x4000E034; +pub const UART2_IM_R: u32 = 0x4000E038; +pub const UART2_RIS_R: u32 = 0x4000E03C; +pub const UART2_MIS_R: u32 = 0x4000E040; +pub const UART2_ICR_R: u32 = 0x4000E044; +pub const UART2_DMACTL_R: u32 = 0x4000E048; +pub const UART2_9BITADDR_R: u32 = 0x4000E0A4; +pub const UART2_9BITAMASK_R: u32 = 0x4000E0A8; +pub const UART2_PP_R: u32 = 0x4000EFC0; +pub const UART2_CC_R: u32 = 0x4000EFC8; +//***************************************************************************** +// +// UART registers (UART3) +// +//***************************************************************************** +pub const UART3_DR_R: u32 = 0x4000F000; +pub const UART3_RSR_R: u32 = 0x4000F004; +pub const UART3_ECR_R: u32 = 0x4000F004; +pub const UART3_FR_R: u32 = 0x4000F018; +pub const UART3_ILPR_R: u32 = 0x4000F020; +pub const UART3_IBRD_R: u32 = 0x4000F024; +pub const UART3_FBRD_R: u32 = 0x4000F028; +pub const UART3_LCRH_R: u32 = 0x4000F02C; +pub const UART3_CTL_R: u32 = 0x4000F030; +pub const UART3_IFLS_R: u32 = 0x4000F034; +pub const UART3_IM_R: u32 = 0x4000F038; +pub const UART3_RIS_R: u32 = 0x4000F03C; +pub const UART3_MIS_R: u32 = 0x4000F040; +pub const UART3_ICR_R: u32 = 0x4000F044; +pub const UART3_DMACTL_R: u32 = 0x4000F048; +pub const UART3_9BITADDR_R: u32 = 0x4000F0A4; +pub const UART3_9BITAMASK_R: u32 = 0x4000F0A8; +pub const UART3_PP_R: u32 = 0x4000FFC0; +pub const UART3_CC_R: u32 = 0x4000FFC8; +//***************************************************************************** +// +// UART registers (UART4) +// +//***************************************************************************** +pub const UART4_DR_R: u32 = 0x40010000; +pub const UART4_RSR_R: u32 = 0x40010004; +pub const UART4_ECR_R: u32 = 0x40010004; +pub const UART4_FR_R: u32 = 0x40010018; +pub const UART4_ILPR_R: u32 = 0x40010020; +pub const UART4_IBRD_R: u32 = 0x40010024; +pub const UART4_FBRD_R: u32 = 0x40010028; +pub const UART4_LCRH_R: u32 = 0x4001002C; +pub const UART4_CTL_R: u32 = 0x40010030; +pub const UART4_IFLS_R: u32 = 0x40010034; +pub const UART4_IM_R: u32 = 0x40010038; +pub const UART4_RIS_R: u32 = 0x4001003C; +pub const UART4_MIS_R: u32 = 0x40010040; +pub const UART4_ICR_R: u32 = 0x40010044; +pub const UART4_DMACTL_R: u32 = 0x40010048; +pub const UART4_9BITADDR_R: u32 = 0x400100A4; +pub const UART4_9BITAMASK_R: u32 = 0x400100A8; +pub const UART4_PP_R: u32 = 0x40010FC0; +pub const UART4_CC_R: u32 = 0x40010FC8; +//***************************************************************************** +// +// UART registers (UART5) +// +//***************************************************************************** +pub const UART5_DR_R: u32 = 0x40011000; +pub const UART5_RSR_R: u32 = 0x40011004; +pub const UART5_ECR_R: u32 = 0x40011004; +pub const UART5_FR_R: u32 = 0x40011018; +pub const UART5_ILPR_R: u32 = 0x40011020; +pub const UART5_IBRD_R: u32 = 0x40011024; +pub const UART5_FBRD_R: u32 = 0x40011028; +pub const UART5_LCRH_R: u32 = 0x4001102C; +pub const UART5_CTL_R: u32 = 0x40011030; +pub const UART5_IFLS_R: u32 = 0x40011034; +pub const UART5_IM_R: u32 = 0x40011038; +pub const UART5_RIS_R: u32 = 0x4001103C; +pub const UART5_MIS_R: u32 = 0x40011040; +pub const UART5_ICR_R: u32 = 0x40011044; +pub const UART5_DMACTL_R: u32 = 0x40011048; +pub const UART5_9BITADDR_R: u32 = 0x400110A4; +pub const UART5_9BITAMASK_R: u32 = 0x400110A8; +pub const UART5_PP_R: u32 = 0x40011FC0; +pub const UART5_CC_R: u32 = 0x40011FC8; +//***************************************************************************** +// +// UART registers (UART6) +// +//***************************************************************************** +pub const UART6_DR_R: u32 = 0x40012000; +pub const UART6_RSR_R: u32 = 0x40012004; +pub const UART6_ECR_R: u32 = 0x40012004; +pub const UART6_FR_R: u32 = 0x40012018; +pub const UART6_ILPR_R: u32 = 0x40012020; +pub const UART6_IBRD_R: u32 = 0x40012024; +pub const UART6_FBRD_R: u32 = 0x40012028; +pub const UART6_LCRH_R: u32 = 0x4001202C; +pub const UART6_CTL_R: u32 = 0x40012030; +pub const UART6_IFLS_R: u32 = 0x40012034; +pub const UART6_IM_R: u32 = 0x40012038; +pub const UART6_RIS_R: u32 = 0x4001203C; +pub const UART6_MIS_R: u32 = 0x40012040; +pub const UART6_ICR_R: u32 = 0x40012044; +pub const UART6_DMACTL_R: u32 = 0x40012048; +pub const UART6_9BITADDR_R: u32 = 0x400120A4; +pub const UART6_9BITAMASK_R: u32 = 0x400120A8; +pub const UART6_PP_R: u32 = 0x40012FC0; +pub const UART6_CC_R: u32 = 0x40012FC8; +//***************************************************************************** +// +// UART registers (UART7) +// +//***************************************************************************** +pub const UART7_DR_R: u32 = 0x40013000; +pub const UART7_RSR_R: u32 = 0x40013004; +pub const UART7_ECR_R: u32 = 0x40013004; +pub const UART7_FR_R: u32 = 0x40013018; +pub const UART7_ILPR_R: u32 = 0x40013020; +pub const UART7_IBRD_R: u32 = 0x40013024; +pub const UART7_FBRD_R: u32 = 0x40013028; +pub const UART7_LCRH_R: u32 = 0x4001302C; +pub const UART7_CTL_R: u32 = 0x40013030; +pub const UART7_IFLS_R: u32 = 0x40013034; +pub const UART7_IM_R: u32 = 0x40013038; +pub const UART7_RIS_R: u32 = 0x4001303C; +pub const UART7_MIS_R: u32 = 0x40013040; +pub const UART7_ICR_R: u32 = 0x40013044; +pub const UART7_DMACTL_R: u32 = 0x40013048; +pub const UART7_9BITADDR_R: u32 = 0x400130A4; +pub const UART7_9BITAMASK_R: u32 = 0x400130A8; +pub const UART7_PP_R: u32 = 0x40013FC0; +pub const UART7_CC_R: u32 = 0x40013FC8; +//***************************************************************************** +// +// I2C registers (I2C0) +// +//***************************************************************************** +pub const I2C0_MSA_R: u32 = 0x40020000; +pub const I2C0_MCS_R: u32 = 0x40020004; +pub const I2C0_MDR_R: u32 = 0x40020008; +pub const I2C0_MTPR_R: u32 = 0x4002000C; +pub const I2C0_MIMR_R: u32 = 0x40020010; +pub const I2C0_MRIS_R: u32 = 0x40020014; +pub const I2C0_MMIS_R: u32 = 0x40020018; +pub const I2C0_MICR_R: u32 = 0x4002001C; +pub const I2C0_MCR_R: u32 = 0x40020020; +pub const I2C0_MCLKOCNT_R: u32 = 0x40020024; +pub const I2C0_MBMON_R: u32 = 0x4002002C; +pub const I2C0_MCR2_R: u32 = 0x40020038; +pub const I2C0_SOAR_R: u32 = 0x40020800; +pub const I2C0_SCSR_R: u32 = 0x40020804; +pub const I2C0_SDR_R: u32 = 0x40020808; +pub const I2C0_SIMR_R: u32 = 0x4002080C; +pub const I2C0_SRIS_R: u32 = 0x40020810; +pub const I2C0_SMIS_R: u32 = 0x40020814; +pub const I2C0_SICR_R: u32 = 0x40020818; +pub const I2C0_SOAR2_R: u32 = 0x4002081C; +pub const I2C0_SACKCTL_R: u32 = 0x40020820; +pub const I2C0_PP_R: u32 = 0x40020FC0; +pub const I2C0_PC_R: u32 = 0x40020FC4; +//***************************************************************************** +// +// I2C registers (I2C1) +// +//***************************************************************************** +pub const I2C1_MSA_R: u32 = 0x40021000; +pub const I2C1_MCS_R: u32 = 0x40021004; +pub const I2C1_MDR_R: u32 = 0x40021008; +pub const I2C1_MTPR_R: u32 = 0x4002100C; +pub const I2C1_MIMR_R: u32 = 0x40021010; +pub const I2C1_MRIS_R: u32 = 0x40021014; +pub const I2C1_MMIS_R: u32 = 0x40021018; +pub const I2C1_MICR_R: u32 = 0x4002101C; +pub const I2C1_MCR_R: u32 = 0x40021020; +pub const I2C1_MCLKOCNT_R: u32 = 0x40021024; +pub const I2C1_MBMON_R: u32 = 0x4002102C; +pub const I2C1_MCR2_R: u32 = 0x40021038; +pub const I2C1_SOAR_R: u32 = 0x40021800; +pub const I2C1_SCSR_R: u32 = 0x40021804; +pub const I2C1_SDR_R: u32 = 0x40021808; +pub const I2C1_SIMR_R: u32 = 0x4002180C; +pub const I2C1_SRIS_R: u32 = 0x40021810; +pub const I2C1_SMIS_R: u32 = 0x40021814; +pub const I2C1_SICR_R: u32 = 0x40021818; +pub const I2C1_SOAR2_R: u32 = 0x4002181C; +pub const I2C1_SACKCTL_R: u32 = 0x40021820; +pub const I2C1_PP_R: u32 = 0x40021FC0; +pub const I2C1_PC_R: u32 = 0x40021FC4; +//***************************************************************************** +// +// I2C registers (I2C2) +// +//***************************************************************************** +pub const I2C2_MSA_R: u32 = 0x40022000; +pub const I2C2_MCS_R: u32 = 0x40022004; +pub const I2C2_MDR_R: u32 = 0x40022008; +pub const I2C2_MTPR_R: u32 = 0x4002200C; +pub const I2C2_MIMR_R: u32 = 0x40022010; +pub const I2C2_MRIS_R: u32 = 0x40022014; +pub const I2C2_MMIS_R: u32 = 0x40022018; +pub const I2C2_MICR_R: u32 = 0x4002201C; +pub const I2C2_MCR_R: u32 = 0x40022020; +pub const I2C2_MCLKOCNT_R: u32 = 0x40022024; +pub const I2C2_MBMON_R: u32 = 0x4002202C; +pub const I2C2_MCR2_R: u32 = 0x40022038; +pub const I2C2_SOAR_R: u32 = 0x40022800; +pub const I2C2_SCSR_R: u32 = 0x40022804; +pub const I2C2_SDR_R: u32 = 0x40022808; +pub const I2C2_SIMR_R: u32 = 0x4002280C; +pub const I2C2_SRIS_R: u32 = 0x40022810; +pub const I2C2_SMIS_R: u32 = 0x40022814; +pub const I2C2_SICR_R: u32 = 0x40022818; +pub const I2C2_SOAR2_R: u32 = 0x4002281C; +pub const I2C2_SACKCTL_R: u32 = 0x40022820; +pub const I2C2_PP_R: u32 = 0x40022FC0; +pub const I2C2_PC_R: u32 = 0x40022FC4; +//***************************************************************************** +// +// I2C registers (I2C3) +// +//***************************************************************************** +pub const I2C3_MSA_R: u32 = 0x40023000; +pub const I2C3_MCS_R: u32 = 0x40023004; +pub const I2C3_MDR_R: u32 = 0x40023008; +pub const I2C3_MTPR_R: u32 = 0x4002300C; +pub const I2C3_MIMR_R: u32 = 0x40023010; +pub const I2C3_MRIS_R: u32 = 0x40023014; +pub const I2C3_MMIS_R: u32 = 0x40023018; +pub const I2C3_MICR_R: u32 = 0x4002301C; +pub const I2C3_MCR_R: u32 = 0x40023020; +pub const I2C3_MCLKOCNT_R: u32 = 0x40023024; +pub const I2C3_MBMON_R: u32 = 0x4002302C; +pub const I2C3_MCR2_R: u32 = 0x40023038; +pub const I2C3_SOAR_R: u32 = 0x40023800; +pub const I2C3_SCSR_R: u32 = 0x40023804; +pub const I2C3_SDR_R: u32 = 0x40023808; +pub const I2C3_SIMR_R: u32 = 0x4002380C; +pub const I2C3_SRIS_R: u32 = 0x40023810; +pub const I2C3_SMIS_R: u32 = 0x40023814; +pub const I2C3_SICR_R: u32 = 0x40023818; +pub const I2C3_SOAR2_R: u32 = 0x4002381C; +pub const I2C3_SACKCTL_R: u32 = 0x40023820; +pub const I2C3_PP_R: u32 = 0x40023FC0; +pub const I2C3_PC_R: u32 = 0x40023FC4; +//***************************************************************************** +// +// GPIO registers (PORTE) +// +//***************************************************************************** +pub const GPIO_PORTE_DATA_BITS_R: u32 = 0x40024000; +pub const GPIO_PORTE_DATA_R: u32 = 0x400243FC; +pub const GPIO_PORTE_DIR_R: u32 = 0x40024400; +pub const GPIO_PORTE_IS_R: u32 = 0x40024404; +pub const GPIO_PORTE_IBE_R: u32 = 0x40024408; +pub const GPIO_PORTE_IEV_R: u32 = 0x4002440C; +pub const GPIO_PORTE_IM_R: u32 = 0x40024410; +pub const GPIO_PORTE_RIS_R: u32 = 0x40024414; +pub const GPIO_PORTE_MIS_R: u32 = 0x40024418; +pub const GPIO_PORTE_ICR_R: u32 = 0x4002441C; +pub const GPIO_PORTE_AFSEL_R: u32 = 0x40024420; +pub const GPIO_PORTE_DR2R_R: u32 = 0x40024500; +pub const GPIO_PORTE_DR4R_R: u32 = 0x40024504; +pub const GPIO_PORTE_DR8R_R: u32 = 0x40024508; +pub const GPIO_PORTE_ODR_R: u32 = 0x4002450C; +pub const GPIO_PORTE_PUR_R: u32 = 0x40024510; +pub const GPIO_PORTE_PDR_R: u32 = 0x40024514; +pub const GPIO_PORTE_SLR_R: u32 = 0x40024518; +pub const GPIO_PORTE_DEN_R: u32 = 0x4002451C; +pub const GPIO_PORTE_LOCK_R: u32 = 0x40024520; +pub const GPIO_PORTE_CR_R: u32 = 0x40024524; +pub const GPIO_PORTE_AMSEL_R: u32 = 0x40024528; +pub const GPIO_PORTE_PCTL_R: u32 = 0x4002452C; +pub const GPIO_PORTE_ADCCTL_R: u32 = 0x40024530; +pub const GPIO_PORTE_DMACTL_R: u32 = 0x40024534; +//***************************************************************************** +// +// GPIO registers (PORTF) +// +//***************************************************************************** +pub const GPIO_PORTF_DATA_BITS_R: u32 = 0x40025000; +pub const GPIO_PORTF_DATA_R: u32 = 0x400253FC; +pub const GPIO_PORTF_DIR_R: u32 = 0x40025400; +pub const GPIO_PORTF_IS_R: u32 = 0x40025404; +pub const GPIO_PORTF_IBE_R: u32 = 0x40025408; +pub const GPIO_PORTF_IEV_R: u32 = 0x4002540C; +pub const GPIO_PORTF_IM_R: u32 = 0x40025410; +pub const GPIO_PORTF_RIS_R: u32 = 0x40025414; +pub const GPIO_PORTF_MIS_R: u32 = 0x40025418; +pub const GPIO_PORTF_ICR_R: u32 = 0x4002541C; +pub const GPIO_PORTF_AFSEL_R: u32 = 0x40025420; +pub const GPIO_PORTF_DR2R_R: u32 = 0x40025500; +pub const GPIO_PORTF_DR4R_R: u32 = 0x40025504; +pub const GPIO_PORTF_DR8R_R: u32 = 0x40025508; +pub const GPIO_PORTF_ODR_R: u32 = 0x4002550C; +pub const GPIO_PORTF_PUR_R: u32 = 0x40025510; +pub const GPIO_PORTF_PDR_R: u32 = 0x40025514; +pub const GPIO_PORTF_SLR_R: u32 = 0x40025518; +pub const GPIO_PORTF_DEN_R: u32 = 0x4002551C; +pub const GPIO_PORTF_LOCK_R: u32 = 0x40025520; +pub const GPIO_PORTF_CR_R: u32 = 0x40025524; +pub const GPIO_PORTF_AMSEL_R: u32 = 0x40025528; +pub const GPIO_PORTF_PCTL_R: u32 = 0x4002552C; +pub const GPIO_PORTF_ADCCTL_R: u32 = 0x40025530; +pub const GPIO_PORTF_DMACTL_R: u32 = 0x40025534; +//***************************************************************************** +// +// PWM registers (PWM0) +// +//***************************************************************************** +pub const PWM0_CTL_R: u32 = 0x40028000; +pub const PWM0_SYNC_R: u32 = 0x40028004; +pub const PWM0_ENABLE_R: u32 = 0x40028008; +pub const PWM0_INVERT_R: u32 = 0x4002800C; +pub const PWM0_FAULT_R: u32 = 0x40028010; +pub const PWM0_INTEN_R: u32 = 0x40028014; +pub const PWM0_RIS_R: u32 = 0x40028018; +pub const PWM0_ISC_R: u32 = 0x4002801C; +pub const PWM0_STATUS_R: u32 = 0x40028020; +pub const PWM0_FAULTVAL_R: u32 = 0x40028024; +pub const PWM0_ENUPD_R: u32 = 0x40028028; +pub const PWM0_0_CTL_R: u32 = 0x40028040; +pub const PWM0_0_INTEN_R: u32 = 0x40028044; +pub const PWM0_0_RIS_R: u32 = 0x40028048; +pub const PWM0_0_ISC_R: u32 = 0x4002804C; +pub const PWM0_0_LOAD_R: u32 = 0x40028050; +pub const PWM0_0_COUNT_R: u32 = 0x40028054; +pub const PWM0_0_CMPA_R: u32 = 0x40028058; +pub const PWM0_0_CMPB_R: u32 = 0x4002805C; +pub const PWM0_0_GENA_R: u32 = 0x40028060; +pub const PWM0_0_GENB_R: u32 = 0x40028064; +pub const PWM0_0_DBCTL_R: u32 = 0x40028068; +pub const PWM0_0_DBRISE_R: u32 = 0x4002806C; +pub const PWM0_0_DBFALL_R: u32 = 0x40028070; +pub const PWM0_0_FLTSRC0_R: u32 = 0x40028074; +pub const PWM0_0_FLTSRC1_R: u32 = 0x40028078; +pub const PWM0_0_MINFLTPER_R: u32 = 0x4002807C; +pub const PWM0_1_CTL_R: u32 = 0x40028080; +pub const PWM0_1_INTEN_R: u32 = 0x40028084; +pub const PWM0_1_RIS_R: u32 = 0x40028088; +pub const PWM0_1_ISC_R: u32 = 0x4002808C; +pub const PWM0_1_LOAD_R: u32 = 0x40028090; +pub const PWM0_1_COUNT_R: u32 = 0x40028094; +pub const PWM0_1_CMPA_R: u32 = 0x40028098; +pub const PWM0_1_CMPB_R: u32 = 0x4002809C; +pub const PWM0_1_GENA_R: u32 = 0x400280A0; +pub const PWM0_1_GENB_R: u32 = 0x400280A4; +pub const PWM0_1_DBCTL_R: u32 = 0x400280A8; +pub const PWM0_1_DBRISE_R: u32 = 0x400280AC; +pub const PWM0_1_DBFALL_R: u32 = 0x400280B0; +pub const PWM0_1_FLTSRC0_R: u32 = 0x400280B4; +pub const PWM0_1_FLTSRC1_R: u32 = 0x400280B8; +pub const PWM0_1_MINFLTPER_R: u32 = 0x400280BC; +pub const PWM0_2_CTL_R: u32 = 0x400280C0; +pub const PWM0_2_INTEN_R: u32 = 0x400280C4; +pub const PWM0_2_RIS_R: u32 = 0x400280C8; +pub const PWM0_2_ISC_R: u32 = 0x400280CC; +pub const PWM0_2_LOAD_R: u32 = 0x400280D0; +pub const PWM0_2_COUNT_R: u32 = 0x400280D4; +pub const PWM0_2_CMPA_R: u32 = 0x400280D8; +pub const PWM0_2_CMPB_R: u32 = 0x400280DC; +pub const PWM0_2_GENA_R: u32 = 0x400280E0; +pub const PWM0_2_GENB_R: u32 = 0x400280E4; +pub const PWM0_2_DBCTL_R: u32 = 0x400280E8; +pub const PWM0_2_DBRISE_R: u32 = 0x400280EC; +pub const PWM0_2_DBFALL_R: u32 = 0x400280F0; +pub const PWM0_2_FLTSRC0_R: u32 = 0x400280F4; +pub const PWM0_2_FLTSRC1_R: u32 = 0x400280F8; +pub const PWM0_2_MINFLTPER_R: u32 = 0x400280FC; +pub const PWM0_3_CTL_R: u32 = 0x40028100; +pub const PWM0_3_INTEN_R: u32 = 0x40028104; +pub const PWM0_3_RIS_R: u32 = 0x40028108; +pub const PWM0_3_ISC_R: u32 = 0x4002810C; +pub const PWM0_3_LOAD_R: u32 = 0x40028110; +pub const PWM0_3_COUNT_R: u32 = 0x40028114; +pub const PWM0_3_CMPA_R: u32 = 0x40028118; +pub const PWM0_3_CMPB_R: u32 = 0x4002811C; +pub const PWM0_3_GENA_R: u32 = 0x40028120; +pub const PWM0_3_GENB_R: u32 = 0x40028124; +pub const PWM0_3_DBCTL_R: u32 = 0x40028128; +pub const PWM0_3_DBRISE_R: u32 = 0x4002812C; +pub const PWM0_3_DBFALL_R: u32 = 0x40028130; +pub const PWM0_3_FLTSRC0_R: u32 = 0x40028134; +pub const PWM0_3_FLTSRC1_R: u32 = 0x40028138; +pub const PWM0_3_MINFLTPER_R: u32 = 0x4002813C; +pub const PWM0_0_FLTSEN_R: u32 = 0x40028800; +pub const PWM0_0_FLTSTAT0_R: u32 = 0x40028804; +pub const PWM0_0_FLTSTAT1_R: u32 = 0x40028808; +pub const PWM0_1_FLTSEN_R: u32 = 0x40028880; +pub const PWM0_1_FLTSTAT0_R: u32 = 0x40028884; +pub const PWM0_1_FLTSTAT1_R: u32 = 0x40028888; +pub const PWM0_2_FLTSTAT0_R: u32 = 0x40028904; +pub const PWM0_2_FLTSTAT1_R: u32 = 0x40028908; +pub const PWM0_3_FLTSTAT0_R: u32 = 0x40028984; +pub const PWM0_3_FLTSTAT1_R: u32 = 0x40028988; +pub const PWM0_PP_R: u32 = 0x40028FC0; +//***************************************************************************** +// +// PWM registers (PWM1) +// +//***************************************************************************** +pub const PWM1_CTL_R: u32 = 0x40029000; +pub const PWM1_SYNC_R: u32 = 0x40029004; +pub const PWM1_ENABLE_R: u32 = 0x40029008; +pub const PWM1_INVERT_R: u32 = 0x4002900C; +pub const PWM1_FAULT_R: u32 = 0x40029010; +pub const PWM1_INTEN_R: u32 = 0x40029014; +pub const PWM1_RIS_R: u32 = 0x40029018; +pub const PWM1_ISC_R: u32 = 0x4002901C; +pub const PWM1_STATUS_R: u32 = 0x40029020; +pub const PWM1_FAULTVAL_R: u32 = 0x40029024; +pub const PWM1_ENUPD_R: u32 = 0x40029028; +pub const PWM1_0_CTL_R: u32 = 0x40029040; +pub const PWM1_0_INTEN_R: u32 = 0x40029044; +pub const PWM1_0_RIS_R: u32 = 0x40029048; +pub const PWM1_0_ISC_R: u32 = 0x4002904C; +pub const PWM1_0_LOAD_R: u32 = 0x40029050; +pub const PWM1_0_COUNT_R: u32 = 0x40029054; +pub const PWM1_0_CMPA_R: u32 = 0x40029058; +pub const PWM1_0_CMPB_R: u32 = 0x4002905C; +pub const PWM1_0_GENA_R: u32 = 0x40029060; +pub const PWM1_0_GENB_R: u32 = 0x40029064; +pub const PWM1_0_DBCTL_R: u32 = 0x40029068; +pub const PWM1_0_DBRISE_R: u32 = 0x4002906C; +pub const PWM1_0_DBFALL_R: u32 = 0x40029070; +pub const PWM1_0_FLTSRC0_R: u32 = 0x40029074; +pub const PWM1_0_FLTSRC1_R: u32 = 0x40029078; +pub const PWM1_0_MINFLTPER_R: u32 = 0x4002907C; +pub const PWM1_1_CTL_R: u32 = 0x40029080; +pub const PWM1_1_INTEN_R: u32 = 0x40029084; +pub const PWM1_1_RIS_R: u32 = 0x40029088; +pub const PWM1_1_ISC_R: u32 = 0x4002908C; +pub const PWM1_1_LOAD_R: u32 = 0x40029090; +pub const PWM1_1_COUNT_R: u32 = 0x40029094; +pub const PWM1_1_CMPA_R: u32 = 0x40029098; +pub const PWM1_1_CMPB_R: u32 = 0x4002909C; +pub const PWM1_1_GENA_R: u32 = 0x400290A0; +pub const PWM1_1_GENB_R: u32 = 0x400290A4; +pub const PWM1_1_DBCTL_R: u32 = 0x400290A8; +pub const PWM1_1_DBRISE_R: u32 = 0x400290AC; +pub const PWM1_1_DBFALL_R: u32 = 0x400290B0; +pub const PWM1_1_FLTSRC0_R: u32 = 0x400290B4; +pub const PWM1_1_FLTSRC1_R: u32 = 0x400290B8; +pub const PWM1_1_MINFLTPER_R: u32 = 0x400290BC; +pub const PWM1_2_CTL_R: u32 = 0x400290C0; +pub const PWM1_2_INTEN_R: u32 = 0x400290C4; +pub const PWM1_2_RIS_R: u32 = 0x400290C8; +pub const PWM1_2_ISC_R: u32 = 0x400290CC; +pub const PWM1_2_LOAD_R: u32 = 0x400290D0; +pub const PWM1_2_COUNT_R: u32 = 0x400290D4; +pub const PWM1_2_CMPA_R: u32 = 0x400290D8; +pub const PWM1_2_CMPB_R: u32 = 0x400290DC; +pub const PWM1_2_GENA_R: u32 = 0x400290E0; +pub const PWM1_2_GENB_R: u32 = 0x400290E4; +pub const PWM1_2_DBCTL_R: u32 = 0x400290E8; +pub const PWM1_2_DBRISE_R: u32 = 0x400290EC; +pub const PWM1_2_DBFALL_R: u32 = 0x400290F0; +pub const PWM1_2_FLTSRC0_R: u32 = 0x400290F4; +pub const PWM1_2_FLTSRC1_R: u32 = 0x400290F8; +pub const PWM1_2_MINFLTPER_R: u32 = 0x400290FC; +pub const PWM1_3_CTL_R: u32 = 0x40029100; +pub const PWM1_3_INTEN_R: u32 = 0x40029104; +pub const PWM1_3_RIS_R: u32 = 0x40029108; +pub const PWM1_3_ISC_R: u32 = 0x4002910C; +pub const PWM1_3_LOAD_R: u32 = 0x40029110; +pub const PWM1_3_COUNT_R: u32 = 0x40029114; +pub const PWM1_3_CMPA_R: u32 = 0x40029118; +pub const PWM1_3_CMPB_R: u32 = 0x4002911C; +pub const PWM1_3_GENA_R: u32 = 0x40029120; +pub const PWM1_3_GENB_R: u32 = 0x40029124; +pub const PWM1_3_DBCTL_R: u32 = 0x40029128; +pub const PWM1_3_DBRISE_R: u32 = 0x4002912C; +pub const PWM1_3_DBFALL_R: u32 = 0x40029130; +pub const PWM1_3_FLTSRC0_R: u32 = 0x40029134; +pub const PWM1_3_FLTSRC1_R: u32 = 0x40029138; +pub const PWM1_3_MINFLTPER_R: u32 = 0x4002913C; +pub const PWM1_0_FLTSEN_R: u32 = 0x40029800; +pub const PWM1_0_FLTSTAT0_R: u32 = 0x40029804; +pub const PWM1_0_FLTSTAT1_R: u32 = 0x40029808; +pub const PWM1_1_FLTSEN_R: u32 = 0x40029880; +pub const PWM1_1_FLTSTAT0_R: u32 = 0x40029884; +pub const PWM1_1_FLTSTAT1_R: u32 = 0x40029888; +pub const PWM1_2_FLTSTAT0_R: u32 = 0x40029904; +pub const PWM1_2_FLTSTAT1_R: u32 = 0x40029908; +pub const PWM1_3_FLTSTAT0_R: u32 = 0x40029984; +pub const PWM1_3_FLTSTAT1_R: u32 = 0x40029988; +pub const PWM1_PP_R: u32 = 0x40029FC0; +//***************************************************************************** +// +// QEI registers (QEI0) +// +//***************************************************************************** +pub const QEI0_CTL_R: u32 = 0x4002C000; +pub const QEI0_STAT_R: u32 = 0x4002C004; +pub const QEI0_POS_R: u32 = 0x4002C008; +pub const QEI0_MAXPOS_R: u32 = 0x4002C00C; +pub const QEI0_LOAD_R: u32 = 0x4002C010; +pub const QEI0_TIME_R: u32 = 0x4002C014; +pub const QEI0_COUNT_R: u32 = 0x4002C018; +pub const QEI0_SPEED_R: u32 = 0x4002C01C; +pub const QEI0_INTEN_R: u32 = 0x4002C020; +pub const QEI0_RIS_R: u32 = 0x4002C024; +pub const QEI0_ISC_R: u32 = 0x4002C028; +//***************************************************************************** +// +// QEI registers (QEI1) +// +//***************************************************************************** +pub const QEI1_CTL_R: u32 = 0x4002D000; +pub const QEI1_STAT_R: u32 = 0x4002D004; +pub const QEI1_POS_R: u32 = 0x4002D008; +pub const QEI1_MAXPOS_R: u32 = 0x4002D00C; +pub const QEI1_LOAD_R: u32 = 0x4002D010; +pub const QEI1_TIME_R: u32 = 0x4002D014; +pub const QEI1_COUNT_R: u32 = 0x4002D018; +pub const QEI1_SPEED_R: u32 = 0x4002D01C; +pub const QEI1_INTEN_R: u32 = 0x4002D020; +pub const QEI1_RIS_R: u32 = 0x4002D024; +pub const QEI1_ISC_R: u32 = 0x4002D028; +//***************************************************************************** +// +// Timer registers (TIMER0) +// +//***************************************************************************** +pub const TIMER0_CFG_R: u32 = 0x40030000; +pub const TIMER0_TAMR_R: u32 = 0x40030004; +pub const TIMER0_TBMR_R: u32 = 0x40030008; +pub const TIMER0_CTL_R: u32 = 0x4003000C; +pub const TIMER0_SYNC_R: u32 = 0x40030010; +pub const TIMER0_IMR_R: u32 = 0x40030018; +pub const TIMER0_RIS_R: u32 = 0x4003001C; +pub const TIMER0_MIS_R: u32 = 0x40030020; +pub const TIMER0_ICR_R: u32 = 0x40030024; +pub const TIMER0_TAILR_R: u32 = 0x40030028; +pub const TIMER0_TBILR_R: u32 = 0x4003002C; +pub const TIMER0_TAMATCHR_R: u32 = 0x40030030; +pub const TIMER0_TBMATCHR_R: u32 = 0x40030034; +pub const TIMER0_TAPR_R: u32 = 0x40030038; +pub const TIMER0_TBPR_R: u32 = 0x4003003C; +pub const TIMER0_TAPMR_R: u32 = 0x40030040; +pub const TIMER0_TBPMR_R: u32 = 0x40030044; +pub const TIMER0_TAR_R: u32 = 0x40030048; +pub const TIMER0_TBR_R: u32 = 0x4003004C; +pub const TIMER0_TAV_R: u32 = 0x40030050; +pub const TIMER0_TBV_R: u32 = 0x40030054; +pub const TIMER0_RTCPD_R: u32 = 0x40030058; +pub const TIMER0_TAPS_R: u32 = 0x4003005C; +pub const TIMER0_TBPS_R: u32 = 0x40030060; +pub const TIMER0_TAPV_R: u32 = 0x40030064; +pub const TIMER0_TBPV_R: u32 = 0x40030068; +pub const TIMER0_PP_R: u32 = 0x40030FC0; +//***************************************************************************** +// +// Timer registers (TIMER1) +// +//***************************************************************************** +pub const TIMER1_CFG_R: u32 = 0x40031000; +pub const TIMER1_TAMR_R: u32 = 0x40031004; +pub const TIMER1_TBMR_R: u32 = 0x40031008; +pub const TIMER1_CTL_R: u32 = 0x4003100C; +pub const TIMER1_SYNC_R: u32 = 0x40031010; +pub const TIMER1_IMR_R: u32 = 0x40031018; +pub const TIMER1_RIS_R: u32 = 0x4003101C; +pub const TIMER1_MIS_R: u32 = 0x40031020; +pub const TIMER1_ICR_R: u32 = 0x40031024; +pub const TIMER1_TAILR_R: u32 = 0x40031028; +pub const TIMER1_TBILR_R: u32 = 0x4003102C; +pub const TIMER1_TAMATCHR_R: u32 = 0x40031030; +pub const TIMER1_TBMATCHR_R: u32 = 0x40031034; +pub const TIMER1_TAPR_R: u32 = 0x40031038; +pub const TIMER1_TBPR_R: u32 = 0x4003103C; +pub const TIMER1_TAPMR_R: u32 = 0x40031040; +pub const TIMER1_TBPMR_R: u32 = 0x40031044; +pub const TIMER1_TAR_R: u32 = 0x40031048; +pub const TIMER1_TBR_R: u32 = 0x4003104C; +pub const TIMER1_TAV_R: u32 = 0x40031050; +pub const TIMER1_TBV_R: u32 = 0x40031054; +pub const TIMER1_RTCPD_R: u32 = 0x40031058; +pub const TIMER1_TAPS_R: u32 = 0x4003105C; +pub const TIMER1_TBPS_R: u32 = 0x40031060; +pub const TIMER1_TAPV_R: u32 = 0x40031064; +pub const TIMER1_TBPV_R: u32 = 0x40031068; +pub const TIMER1_PP_R: u32 = 0x40031FC0; +//***************************************************************************** +// +// Timer registers (TIMER2) +// +//***************************************************************************** +pub const TIMER2_CFG_R: u32 = 0x40032000; +pub const TIMER2_TAMR_R: u32 = 0x40032004; +pub const TIMER2_TBMR_R: u32 = 0x40032008; +pub const TIMER2_CTL_R: u32 = 0x4003200C; +pub const TIMER2_SYNC_R: u32 = 0x40032010; +pub const TIMER2_IMR_R: u32 = 0x40032018; +pub const TIMER2_RIS_R: u32 = 0x4003201C; +pub const TIMER2_MIS_R: u32 = 0x40032020; +pub const TIMER2_ICR_R: u32 = 0x40032024; +pub const TIMER2_TAILR_R: u32 = 0x40032028; +pub const TIMER2_TBILR_R: u32 = 0x4003202C; +pub const TIMER2_TAMATCHR_R: u32 = 0x40032030; +pub const TIMER2_TBMATCHR_R: u32 = 0x40032034; +pub const TIMER2_TAPR_R: u32 = 0x40032038; +pub const TIMER2_TBPR_R: u32 = 0x4003203C; +pub const TIMER2_TAPMR_R: u32 = 0x40032040; +pub const TIMER2_TBPMR_R: u32 = 0x40032044; +pub const TIMER2_TAR_R: u32 = 0x40032048; +pub const TIMER2_TBR_R: u32 = 0x4003204C; +pub const TIMER2_TAV_R: u32 = 0x40032050; +pub const TIMER2_TBV_R: u32 = 0x40032054; +pub const TIMER2_RTCPD_R: u32 = 0x40032058; +pub const TIMER2_TAPS_R: u32 = 0x4003205C; +pub const TIMER2_TBPS_R: u32 = 0x40032060; +pub const TIMER2_TAPV_R: u32 = 0x40032064; +pub const TIMER2_TBPV_R: u32 = 0x40032068; +pub const TIMER2_PP_R: u32 = 0x40032FC0; +//***************************************************************************** +// +// Timer registers (TIMER3) +// +//***************************************************************************** +pub const TIMER3_CFG_R: u32 = 0x40033000; +pub const TIMER3_TAMR_R: u32 = 0x40033004; +pub const TIMER3_TBMR_R: u32 = 0x40033008; +pub const TIMER3_CTL_R: u32 = 0x4003300C; +pub const TIMER3_SYNC_R: u32 = 0x40033010; +pub const TIMER3_IMR_R: u32 = 0x40033018; +pub const TIMER3_RIS_R: u32 = 0x4003301C; +pub const TIMER3_MIS_R: u32 = 0x40033020; +pub const TIMER3_ICR_R: u32 = 0x40033024; +pub const TIMER3_TAILR_R: u32 = 0x40033028; +pub const TIMER3_TBILR_R: u32 = 0x4003302C; +pub const TIMER3_TAMATCHR_R: u32 = 0x40033030; +pub const TIMER3_TBMATCHR_R: u32 = 0x40033034; +pub const TIMER3_TAPR_R: u32 = 0x40033038; +pub const TIMER3_TBPR_R: u32 = 0x4003303C; +pub const TIMER3_TAPMR_R: u32 = 0x40033040; +pub const TIMER3_TBPMR_R: u32 = 0x40033044; +pub const TIMER3_TAR_R: u32 = 0x40033048; +pub const TIMER3_TBR_R: u32 = 0x4003304C; +pub const TIMER3_TAV_R: u32 = 0x40033050; +pub const TIMER3_TBV_R: u32 = 0x40033054; +pub const TIMER3_RTCPD_R: u32 = 0x40033058; +pub const TIMER3_TAPS_R: u32 = 0x4003305C; +pub const TIMER3_TBPS_R: u32 = 0x40033060; +pub const TIMER3_TAPV_R: u32 = 0x40033064; +pub const TIMER3_TBPV_R: u32 = 0x40033068; +pub const TIMER3_PP_R: u32 = 0x40033FC0; +//***************************************************************************** +// +// Timer registers (TIMER4) +// +//***************************************************************************** +pub const TIMER4_CFG_R: u32 = 0x40034000; +pub const TIMER4_TAMR_R: u32 = 0x40034004; +pub const TIMER4_TBMR_R: u32 = 0x40034008; +pub const TIMER4_CTL_R: u32 = 0x4003400C; +pub const TIMER4_SYNC_R: u32 = 0x40034010; +pub const TIMER4_IMR_R: u32 = 0x40034018; +pub const TIMER4_RIS_R: u32 = 0x4003401C; +pub const TIMER4_MIS_R: u32 = 0x40034020; +pub const TIMER4_ICR_R: u32 = 0x40034024; +pub const TIMER4_TAILR_R: u32 = 0x40034028; +pub const TIMER4_TBILR_R: u32 = 0x4003402C; +pub const TIMER4_TAMATCHR_R: u32 = 0x40034030; +pub const TIMER4_TBMATCHR_R: u32 = 0x40034034; +pub const TIMER4_TAPR_R: u32 = 0x40034038; +pub const TIMER4_TBPR_R: u32 = 0x4003403C; +pub const TIMER4_TAPMR_R: u32 = 0x40034040; +pub const TIMER4_TBPMR_R: u32 = 0x40034044; +pub const TIMER4_TAR_R: u32 = 0x40034048; +pub const TIMER4_TBR_R: u32 = 0x4003404C; +pub const TIMER4_TAV_R: u32 = 0x40034050; +pub const TIMER4_TBV_R: u32 = 0x40034054; +pub const TIMER4_RTCPD_R: u32 = 0x40034058; +pub const TIMER4_TAPS_R: u32 = 0x4003405C; +pub const TIMER4_TBPS_R: u32 = 0x40034060; +pub const TIMER4_TAPV_R: u32 = 0x40034064; +pub const TIMER4_TBPV_R: u32 = 0x40034068; +pub const TIMER4_PP_R: u32 = 0x40034FC0; +//***************************************************************************** +// +// Timer registers (TIMER5) +// +//***************************************************************************** +pub const TIMER5_CFG_R: u32 = 0x40035000; +pub const TIMER5_TAMR_R: u32 = 0x40035004; +pub const TIMER5_TBMR_R: u32 = 0x40035008; +pub const TIMER5_CTL_R: u32 = 0x4003500C; +pub const TIMER5_SYNC_R: u32 = 0x40035010; +pub const TIMER5_IMR_R: u32 = 0x40035018; +pub const TIMER5_RIS_R: u32 = 0x4003501C; +pub const TIMER5_MIS_R: u32 = 0x40035020; +pub const TIMER5_ICR_R: u32 = 0x40035024; +pub const TIMER5_TAILR_R: u32 = 0x40035028; +pub const TIMER5_TBILR_R: u32 = 0x4003502C; +pub const TIMER5_TAMATCHR_R: u32 = 0x40035030; +pub const TIMER5_TBMATCHR_R: u32 = 0x40035034; +pub const TIMER5_TAPR_R: u32 = 0x40035038; +pub const TIMER5_TBPR_R: u32 = 0x4003503C; +pub const TIMER5_TAPMR_R: u32 = 0x40035040; +pub const TIMER5_TBPMR_R: u32 = 0x40035044; +pub const TIMER5_TAR_R: u32 = 0x40035048; +pub const TIMER5_TBR_R: u32 = 0x4003504C; +pub const TIMER5_TAV_R: u32 = 0x40035050; +pub const TIMER5_TBV_R: u32 = 0x40035054; +pub const TIMER5_RTCPD_R: u32 = 0x40035058; +pub const TIMER5_TAPS_R: u32 = 0x4003505C; +pub const TIMER5_TBPS_R: u32 = 0x40035060; +pub const TIMER5_TAPV_R: u32 = 0x40035064; +pub const TIMER5_TBPV_R: u32 = 0x40035068; +pub const TIMER5_PP_R: u32 = 0x40035FC0; +//***************************************************************************** +// +// Timer registers (WTIMER0) +// +//***************************************************************************** +pub const WTIMER0_CFG_R: u32 = 0x40036000; +pub const WTIMER0_TAMR_R: u32 = 0x40036004; +pub const WTIMER0_TBMR_R: u32 = 0x40036008; +pub const WTIMER0_CTL_R: u32 = 0x4003600C; +pub const WTIMER0_SYNC_R: u32 = 0x40036010; +pub const WTIMER0_IMR_R: u32 = 0x40036018; +pub const WTIMER0_RIS_R: u32 = 0x4003601C; +pub const WTIMER0_MIS_R: u32 = 0x40036020; +pub const WTIMER0_ICR_R: u32 = 0x40036024; +pub const WTIMER0_TAILR_R: u32 = 0x40036028; +pub const WTIMER0_TBILR_R: u32 = 0x4003602C; +pub const WTIMER0_TAMATCHR_R: u32 = 0x40036030; +pub const WTIMER0_TBMATCHR_R: u32 = 0x40036034; +pub const WTIMER0_TAPR_R: u32 = 0x40036038; +pub const WTIMER0_TBPR_R: u32 = 0x4003603C; +pub const WTIMER0_TAPMR_R: u32 = 0x40036040; +pub const WTIMER0_TBPMR_R: u32 = 0x40036044; +pub const WTIMER0_TAR_R: u32 = 0x40036048; +pub const WTIMER0_TBR_R: u32 = 0x4003604C; +pub const WTIMER0_TAV_R: u32 = 0x40036050; +pub const WTIMER0_TBV_R: u32 = 0x40036054; +pub const WTIMER0_RTCPD_R: u32 = 0x40036058; +pub const WTIMER0_TAPS_R: u32 = 0x4003605C; +pub const WTIMER0_TBPS_R: u32 = 0x40036060; +pub const WTIMER0_TAPV_R: u32 = 0x40036064; +pub const WTIMER0_TBPV_R: u32 = 0x40036068; +pub const WTIMER0_PP_R: u32 = 0x40036FC0; +//***************************************************************************** +// +// Timer registers (WTIMER1) +// +//***************************************************************************** +pub const WTIMER1_CFG_R: u32 = 0x40037000; +pub const WTIMER1_TAMR_R: u32 = 0x40037004; +pub const WTIMER1_TBMR_R: u32 = 0x40037008; +pub const WTIMER1_CTL_R: u32 = 0x4003700C; +pub const WTIMER1_SYNC_R: u32 = 0x40037010; +pub const WTIMER1_IMR_R: u32 = 0x40037018; +pub const WTIMER1_RIS_R: u32 = 0x4003701C; +pub const WTIMER1_MIS_R: u32 = 0x40037020; +pub const WTIMER1_ICR_R: u32 = 0x40037024; +pub const WTIMER1_TAILR_R: u32 = 0x40037028; +pub const WTIMER1_TBILR_R: u32 = 0x4003702C; +pub const WTIMER1_TAMATCHR_R: u32 = 0x40037030; +pub const WTIMER1_TBMATCHR_R: u32 = 0x40037034; +pub const WTIMER1_TAPR_R: u32 = 0x40037038; +pub const WTIMER1_TBPR_R: u32 = 0x4003703C; +pub const WTIMER1_TAPMR_R: u32 = 0x40037040; +pub const WTIMER1_TBPMR_R: u32 = 0x40037044; +pub const WTIMER1_TAR_R: u32 = 0x40037048; +pub const WTIMER1_TBR_R: u32 = 0x4003704C; +pub const WTIMER1_TAV_R: u32 = 0x40037050; +pub const WTIMER1_TBV_R: u32 = 0x40037054; +pub const WTIMER1_RTCPD_R: u32 = 0x40037058; +pub const WTIMER1_TAPS_R: u32 = 0x4003705C; +pub const WTIMER1_TBPS_R: u32 = 0x40037060; +pub const WTIMER1_TAPV_R: u32 = 0x40037064; +pub const WTIMER1_TBPV_R: u32 = 0x40037068; +pub const WTIMER1_PP_R: u32 = 0x40037FC0; +//***************************************************************************** +// +// ADC registers (ADC0) +// +//***************************************************************************** +pub const ADC0_ACTSS_R: u32 = 0x40038000; +pub const ADC0_RIS_R: u32 = 0x40038004; +pub const ADC0_IM_R: u32 = 0x40038008; +pub const ADC0_ISC_R: u32 = 0x4003800C; +pub const ADC0_OSTAT_R: u32 = 0x40038010; +pub const ADC0_EMUX_R: u32 = 0x40038014; +pub const ADC0_USTAT_R: u32 = 0x40038018; +pub const ADC0_TSSEL_R: u32 = 0x4003801C; +pub const ADC0_SSPRI_R: u32 = 0x40038020; +pub const ADC0_SPC_R: u32 = 0x40038024; +pub const ADC0_PSSI_R: u32 = 0x40038028; +pub const ADC0_SAC_R: u32 = 0x40038030; +pub const ADC0_DCISC_R: u32 = 0x40038034; +pub const ADC0_CTL_R: u32 = 0x40038038; +pub const ADC0_SSMUX0_R: u32 = 0x40038040; +pub const ADC0_SSCTL0_R: u32 = 0x40038044; +pub const ADC0_SSFIFO0_R: u32 = 0x40038048; +pub const ADC0_SSFSTAT0_R: u32 = 0x4003804C; +pub const ADC0_SSOP0_R: u32 = 0x40038050; +pub const ADC0_SSDC0_R: u32 = 0x40038054; +pub const ADC0_SSMUX1_R: u32 = 0x40038060; +pub const ADC0_SSCTL1_R: u32 = 0x40038064; +pub const ADC0_SSFIFO1_R: u32 = 0x40038068; +pub const ADC0_SSFSTAT1_R: u32 = 0x4003806C; +pub const ADC0_SSOP1_R: u32 = 0x40038070; +pub const ADC0_SSDC1_R: u32 = 0x40038074; +pub const ADC0_SSMUX2_R: u32 = 0x40038080; +pub const ADC0_SSCTL2_R: u32 = 0x40038084; +pub const ADC0_SSFIFO2_R: u32 = 0x40038088; +pub const ADC0_SSFSTAT2_R: u32 = 0x4003808C; +pub const ADC0_SSOP2_R: u32 = 0x40038090; +pub const ADC0_SSDC2_R: u32 = 0x40038094; +pub const ADC0_SSMUX3_R: u32 = 0x400380A0; +pub const ADC0_SSCTL3_R: u32 = 0x400380A4; +pub const ADC0_SSFIFO3_R: u32 = 0x400380A8; +pub const ADC0_SSFSTAT3_R: u32 = 0x400380AC; +pub const ADC0_SSOP3_R: u32 = 0x400380B0; +pub const ADC0_SSDC3_R: u32 = 0x400380B4; +pub const ADC0_DCRIC_R: u32 = 0x40038D00; +pub const ADC0_DCCTL0_R: u32 = 0x40038E00; +pub const ADC0_DCCTL1_R: u32 = 0x40038E04; +pub const ADC0_DCCTL2_R: u32 = 0x40038E08; +pub const ADC0_DCCTL3_R: u32 = 0x40038E0C; +pub const ADC0_DCCTL4_R: u32 = 0x40038E10; +pub const ADC0_DCCTL5_R: u32 = 0x40038E14; +pub const ADC0_DCCTL6_R: u32 = 0x40038E18; +pub const ADC0_DCCTL7_R: u32 = 0x40038E1C; +pub const ADC0_DCCMP0_R: u32 = 0x40038E40; +pub const ADC0_DCCMP1_R: u32 = 0x40038E44; +pub const ADC0_DCCMP2_R: u32 = 0x40038E48; +pub const ADC0_DCCMP3_R: u32 = 0x40038E4C; +pub const ADC0_DCCMP4_R: u32 = 0x40038E50; +pub const ADC0_DCCMP5_R: u32 = 0x40038E54; +pub const ADC0_DCCMP6_R: u32 = 0x40038E58; +pub const ADC0_DCCMP7_R: u32 = 0x40038E5C; +pub const ADC0_PP_R: u32 = 0x40038FC0; +pub const ADC0_PC_R: u32 = 0x40038FC4; +pub const ADC0_CC_R: u32 = 0x40038FC8; +//***************************************************************************** +// +// ADC registers (ADC1) +// +//***************************************************************************** +pub const ADC1_ACTSS_R: u32 = 0x40039000; +pub const ADC1_RIS_R: u32 = 0x40039004; +pub const ADC1_IM_R: u32 = 0x40039008; +pub const ADC1_ISC_R: u32 = 0x4003900C; +pub const ADC1_OSTAT_R: u32 = 0x40039010; +pub const ADC1_EMUX_R: u32 = 0x40039014; +pub const ADC1_USTAT_R: u32 = 0x40039018; +pub const ADC1_TSSEL_R: u32 = 0x4003901C; +pub const ADC1_SSPRI_R: u32 = 0x40039020; +pub const ADC1_SPC_R: u32 = 0x40039024; +pub const ADC1_PSSI_R: u32 = 0x40039028; +pub const ADC1_SAC_R: u32 = 0x40039030; +pub const ADC1_DCISC_R: u32 = 0x40039034; +pub const ADC1_CTL_R: u32 = 0x40039038; +pub const ADC1_SSMUX0_R: u32 = 0x40039040; +pub const ADC1_SSCTL0_R: u32 = 0x40039044; +pub const ADC1_SSFIFO0_R: u32 = 0x40039048; +pub const ADC1_SSFSTAT0_R: u32 = 0x4003904C; +pub const ADC1_SSOP0_R: u32 = 0x40039050; +pub const ADC1_SSDC0_R: u32 = 0x40039054; +pub const ADC1_SSMUX1_R: u32 = 0x40039060; +pub const ADC1_SSCTL1_R: u32 = 0x40039064; +pub const ADC1_SSFIFO1_R: u32 = 0x40039068; +pub const ADC1_SSFSTAT1_R: u32 = 0x4003906C; +pub const ADC1_SSOP1_R: u32 = 0x40039070; +pub const ADC1_SSDC1_R: u32 = 0x40039074; +pub const ADC1_SSMUX2_R: u32 = 0x40039080; +pub const ADC1_SSCTL2_R: u32 = 0x40039084; +pub const ADC1_SSFIFO2_R: u32 = 0x40039088; +pub const ADC1_SSFSTAT2_R: u32 = 0x4003908C; +pub const ADC1_SSOP2_R: u32 = 0x40039090; +pub const ADC1_SSDC2_R: u32 = 0x40039094; +pub const ADC1_SSMUX3_R: u32 = 0x400390A0; +pub const ADC1_SSCTL3_R: u32 = 0x400390A4; +pub const ADC1_SSFIFO3_R: u32 = 0x400390A8; +pub const ADC1_SSFSTAT3_R: u32 = 0x400390AC; +pub const ADC1_SSOP3_R: u32 = 0x400390B0; +pub const ADC1_SSDC3_R: u32 = 0x400390B4; +pub const ADC1_DCRIC_R: u32 = 0x40039D00; +pub const ADC1_DCCTL0_R: u32 = 0x40039E00; +pub const ADC1_DCCTL1_R: u32 = 0x40039E04; +pub const ADC1_DCCTL2_R: u32 = 0x40039E08; +pub const ADC1_DCCTL3_R: u32 = 0x40039E0C; +pub const ADC1_DCCTL4_R: u32 = 0x40039E10; +pub const ADC1_DCCTL5_R: u32 = 0x40039E14; +pub const ADC1_DCCTL6_R: u32 = 0x40039E18; +pub const ADC1_DCCTL7_R: u32 = 0x40039E1C; +pub const ADC1_DCCMP0_R: u32 = 0x40039E40; +pub const ADC1_DCCMP1_R: u32 = 0x40039E44; +pub const ADC1_DCCMP2_R: u32 = 0x40039E48; +pub const ADC1_DCCMP3_R: u32 = 0x40039E4C; +pub const ADC1_DCCMP4_R: u32 = 0x40039E50; +pub const ADC1_DCCMP5_R: u32 = 0x40039E54; +pub const ADC1_DCCMP6_R: u32 = 0x40039E58; +pub const ADC1_DCCMP7_R: u32 = 0x40039E5C; +pub const ADC1_PP_R: u32 = 0x40039FC0; +pub const ADC1_PC_R: u32 = 0x40039FC4; +pub const ADC1_CC_R: u32 = 0x40039FC8; +//***************************************************************************** +// +// Comparator registers (COMP) +// +//***************************************************************************** +pub const COMP_ACMIS_R: u32 = 0x4003C000; +pub const COMP_ACRIS_R: u32 = 0x4003C004; +pub const COMP_ACINTEN_R: u32 = 0x4003C008; +pub const COMP_ACREFCTL_R: u32 = 0x4003C010; +pub const COMP_ACSTAT0_R: u32 = 0x4003C020; +pub const COMP_ACCTL0_R: u32 = 0x4003C024; +pub const COMP_ACSTAT1_R: u32 = 0x4003C040; +pub const COMP_ACCTL1_R: u32 = 0x4003C044; +pub const COMP_PP_R: u32 = 0x4003CFC0; +//***************************************************************************** +// +// CAN registers (CAN0) +// +//***************************************************************************** +pub const CAN0_CTL_R: u32 = 0x40040000; +pub const CAN0_STS_R: u32 = 0x40040004; +pub const CAN0_ERR_R: u32 = 0x40040008; +pub const CAN0_BIT_R: u32 = 0x4004000C; +pub const CAN0_INT_R: u32 = 0x40040010; +pub const CAN0_TST_R: u32 = 0x40040014; +pub const CAN0_BRPE_R: u32 = 0x40040018; +pub const CAN0_IF1CRQ_R: u32 = 0x40040020; +pub const CAN0_IF1CMSK_R: u32 = 0x40040024; +pub const CAN0_IF1MSK1_R: u32 = 0x40040028; +pub const CAN0_IF1MSK2_R: u32 = 0x4004002C; +pub const CAN0_IF1ARB1_R: u32 = 0x40040030; +pub const CAN0_IF1ARB2_R: u32 = 0x40040034; +pub const CAN0_IF1MCTL_R: u32 = 0x40040038; +pub const CAN0_IF1DA1_R: u32 = 0x4004003C; +pub const CAN0_IF1DA2_R: u32 = 0x40040040; +pub const CAN0_IF1DB1_R: u32 = 0x40040044; +pub const CAN0_IF1DB2_R: u32 = 0x40040048; +pub const CAN0_IF2CRQ_R: u32 = 0x40040080; +pub const CAN0_IF2CMSK_R: u32 = 0x40040084; +pub const CAN0_IF2MSK1_R: u32 = 0x40040088; +pub const CAN0_IF2MSK2_R: u32 = 0x4004008C; +pub const CAN0_IF2ARB1_R: u32 = 0x40040090; +pub const CAN0_IF2ARB2_R: u32 = 0x40040094; +pub const CAN0_IF2MCTL_R: u32 = 0x40040098; +pub const CAN0_IF2DA1_R: u32 = 0x4004009C; +pub const CAN0_IF2DA2_R: u32 = 0x400400A0; +pub const CAN0_IF2DB1_R: u32 = 0x400400A4; +pub const CAN0_IF2DB2_R: u32 = 0x400400A8; +pub const CAN0_TXRQ1_R: u32 = 0x40040100; +pub const CAN0_TXRQ2_R: u32 = 0x40040104; +pub const CAN0_NWDA1_R: u32 = 0x40040120; +pub const CAN0_NWDA2_R: u32 = 0x40040124; +pub const CAN0_MSG1INT_R: u32 = 0x40040140; +pub const CAN0_MSG2INT_R: u32 = 0x40040144; +pub const CAN0_MSG1VAL_R: u32 = 0x40040160; +pub const CAN0_MSG2VAL_R: u32 = 0x40040164; +//***************************************************************************** +// +// CAN registers (CAN1) +// +//***************************************************************************** +pub const CAN1_CTL_R: u32 = 0x40041000; +pub const CAN1_STS_R: u32 = 0x40041004; +pub const CAN1_ERR_R: u32 = 0x40041008; +pub const CAN1_BIT_R: u32 = 0x4004100C; +pub const CAN1_INT_R: u32 = 0x40041010; +pub const CAN1_TST_R: u32 = 0x40041014; +pub const CAN1_BRPE_R: u32 = 0x40041018; +pub const CAN1_IF1CRQ_R: u32 = 0x40041020; +pub const CAN1_IF1CMSK_R: u32 = 0x40041024; +pub const CAN1_IF1MSK1_R: u32 = 0x40041028; +pub const CAN1_IF1MSK2_R: u32 = 0x4004102C; +pub const CAN1_IF1ARB1_R: u32 = 0x40041030; +pub const CAN1_IF1ARB2_R: u32 = 0x40041034; +pub const CAN1_IF1MCTL_R: u32 = 0x40041038; +pub const CAN1_IF1DA1_R: u32 = 0x4004103C; +pub const CAN1_IF1DA2_R: u32 = 0x40041040; +pub const CAN1_IF1DB1_R: u32 = 0x40041044; +pub const CAN1_IF1DB2_R: u32 = 0x40041048; +pub const CAN1_IF2CRQ_R: u32 = 0x40041080; +pub const CAN1_IF2CMSK_R: u32 = 0x40041084; +pub const CAN1_IF2MSK1_R: u32 = 0x40041088; +pub const CAN1_IF2MSK2_R: u32 = 0x4004108C; +pub const CAN1_IF2ARB1_R: u32 = 0x40041090; +pub const CAN1_IF2ARB2_R: u32 = 0x40041094; +pub const CAN1_IF2MCTL_R: u32 = 0x40041098; +pub const CAN1_IF2DA1_R: u32 = 0x4004109C; +pub const CAN1_IF2DA2_R: u32 = 0x400410A0; +pub const CAN1_IF2DB1_R: u32 = 0x400410A4; +pub const CAN1_IF2DB2_R: u32 = 0x400410A8; +pub const CAN1_TXRQ1_R: u32 = 0x40041100; +pub const CAN1_TXRQ2_R: u32 = 0x40041104; +pub const CAN1_NWDA1_R: u32 = 0x40041120; +pub const CAN1_NWDA2_R: u32 = 0x40041124; +pub const CAN1_MSG1INT_R: u32 = 0x40041140; +pub const CAN1_MSG2INT_R: u32 = 0x40041144; +pub const CAN1_MSG1VAL_R: u32 = 0x40041160; +pub const CAN1_MSG2VAL_R: u32 = 0x40041164; +//***************************************************************************** +// +// Timer registers (WTIMER2) +// +//***************************************************************************** +pub const WTIMER2_CFG_R: u32 = 0x4004C000; +pub const WTIMER2_TAMR_R: u32 = 0x4004C004; +pub const WTIMER2_TBMR_R: u32 = 0x4004C008; +pub const WTIMER2_CTL_R: u32 = 0x4004C00C; +pub const WTIMER2_SYNC_R: u32 = 0x4004C010; +pub const WTIMER2_IMR_R: u32 = 0x4004C018; +pub const WTIMER2_RIS_R: u32 = 0x4004C01C; +pub const WTIMER2_MIS_R: u32 = 0x4004C020; +pub const WTIMER2_ICR_R: u32 = 0x4004C024; +pub const WTIMER2_TAILR_R: u32 = 0x4004C028; +pub const WTIMER2_TBILR_R: u32 = 0x4004C02C; +pub const WTIMER2_TAMATCHR_R: u32 = 0x4004C030; +pub const WTIMER2_TBMATCHR_R: u32 = 0x4004C034; +pub const WTIMER2_TAPR_R: u32 = 0x4004C038; +pub const WTIMER2_TBPR_R: u32 = 0x4004C03C; +pub const WTIMER2_TAPMR_R: u32 = 0x4004C040; +pub const WTIMER2_TBPMR_R: u32 = 0x4004C044; +pub const WTIMER2_TAR_R: u32 = 0x4004C048; +pub const WTIMER2_TBR_R: u32 = 0x4004C04C; +pub const WTIMER2_TAV_R: u32 = 0x4004C050; +pub const WTIMER2_TBV_R: u32 = 0x4004C054; +pub const WTIMER2_RTCPD_R: u32 = 0x4004C058; +pub const WTIMER2_TAPS_R: u32 = 0x4004C05C; +pub const WTIMER2_TBPS_R: u32 = 0x4004C060; +pub const WTIMER2_TAPV_R: u32 = 0x4004C064; +pub const WTIMER2_TBPV_R: u32 = 0x4004C068; +pub const WTIMER2_PP_R: u32 = 0x4004CFC0; +//***************************************************************************** +// +// Timer registers (WTIMER3) +// +//***************************************************************************** +pub const WTIMER3_CFG_R: u32 = 0x4004D000; +pub const WTIMER3_TAMR_R: u32 = 0x4004D004; +pub const WTIMER3_TBMR_R: u32 = 0x4004D008; +pub const WTIMER3_CTL_R: u32 = 0x4004D00C; +pub const WTIMER3_SYNC_R: u32 = 0x4004D010; +pub const WTIMER3_IMR_R: u32 = 0x4004D018; +pub const WTIMER3_RIS_R: u32 = 0x4004D01C; +pub const WTIMER3_MIS_R: u32 = 0x4004D020; +pub const WTIMER3_ICR_R: u32 = 0x4004D024; +pub const WTIMER3_TAILR_R: u32 = 0x4004D028; +pub const WTIMER3_TBILR_R: u32 = 0x4004D02C; +pub const WTIMER3_TAMATCHR_R: u32 = 0x4004D030; +pub const WTIMER3_TBMATCHR_R: u32 = 0x4004D034; +pub const WTIMER3_TAPR_R: u32 = 0x4004D038; +pub const WTIMER3_TBPR_R: u32 = 0x4004D03C; +pub const WTIMER3_TAPMR_R: u32 = 0x4004D040; +pub const WTIMER3_TBPMR_R: u32 = 0x4004D044; +pub const WTIMER3_TAR_R: u32 = 0x4004D048; +pub const WTIMER3_TBR_R: u32 = 0x4004D04C; +pub const WTIMER3_TAV_R: u32 = 0x4004D050; +pub const WTIMER3_TBV_R: u32 = 0x4004D054; +pub const WTIMER3_RTCPD_R: u32 = 0x4004D058; +pub const WTIMER3_TAPS_R: u32 = 0x4004D05C; +pub const WTIMER3_TBPS_R: u32 = 0x4004D060; +pub const WTIMER3_TAPV_R: u32 = 0x4004D064; +pub const WTIMER3_TBPV_R: u32 = 0x4004D068; +pub const WTIMER3_PP_R: u32 = 0x4004DFC0; +//***************************************************************************** +// +// Timer registers (WTIMER4) +// +//***************************************************************************** +pub const WTIMER4_CFG_R: u32 = 0x4004E000; +pub const WTIMER4_TAMR_R: u32 = 0x4004E004; +pub const WTIMER4_TBMR_R: u32 = 0x4004E008; +pub const WTIMER4_CTL_R: u32 = 0x4004E00C; +pub const WTIMER4_SYNC_R: u32 = 0x4004E010; +pub const WTIMER4_IMR_R: u32 = 0x4004E018; +pub const WTIMER4_RIS_R: u32 = 0x4004E01C; +pub const WTIMER4_MIS_R: u32 = 0x4004E020; +pub const WTIMER4_ICR_R: u32 = 0x4004E024; +pub const WTIMER4_TAILR_R: u32 = 0x4004E028; +pub const WTIMER4_TBILR_R: u32 = 0x4004E02C; +pub const WTIMER4_TAMATCHR_R: u32 = 0x4004E030; +pub const WTIMER4_TBMATCHR_R: u32 = 0x4004E034; +pub const WTIMER4_TAPR_R: u32 = 0x4004E038; +pub const WTIMER4_TBPR_R: u32 = 0x4004E03C; +pub const WTIMER4_TAPMR_R: u32 = 0x4004E040; +pub const WTIMER4_TBPMR_R: u32 = 0x4004E044; +pub const WTIMER4_TAR_R: u32 = 0x4004E048; +pub const WTIMER4_TBR_R: u32 = 0x4004E04C; +pub const WTIMER4_TAV_R: u32 = 0x4004E050; +pub const WTIMER4_TBV_R: u32 = 0x4004E054; +pub const WTIMER4_RTCPD_R: u32 = 0x4004E058; +pub const WTIMER4_TAPS_R: u32 = 0x4004E05C; +pub const WTIMER4_TBPS_R: u32 = 0x4004E060; +pub const WTIMER4_TAPV_R: u32 = 0x4004E064; +pub const WTIMER4_TBPV_R: u32 = 0x4004E068; +pub const WTIMER4_PP_R: u32 = 0x4004EFC0; +//***************************************************************************** +// +// Timer registers (WTIMER5) +// +//***************************************************************************** +pub const WTIMER5_CFG_R: u32 = 0x4004F000; +pub const WTIMER5_TAMR_R: u32 = 0x4004F004; +pub const WTIMER5_TBMR_R: u32 = 0x4004F008; +pub const WTIMER5_CTL_R: u32 = 0x4004F00C; +pub const WTIMER5_SYNC_R: u32 = 0x4004F010; +pub const WTIMER5_IMR_R: u32 = 0x4004F018; +pub const WTIMER5_RIS_R: u32 = 0x4004F01C; +pub const WTIMER5_MIS_R: u32 = 0x4004F020; +pub const WTIMER5_ICR_R: u32 = 0x4004F024; +pub const WTIMER5_TAILR_R: u32 = 0x4004F028; +pub const WTIMER5_TBILR_R: u32 = 0x4004F02C; +pub const WTIMER5_TAMATCHR_R: u32 = 0x4004F030; +pub const WTIMER5_TBMATCHR_R: u32 = 0x4004F034; +pub const WTIMER5_TAPR_R: u32 = 0x4004F038; +pub const WTIMER5_TBPR_R: u32 = 0x4004F03C; +pub const WTIMER5_TAPMR_R: u32 = 0x4004F040; +pub const WTIMER5_TBPMR_R: u32 = 0x4004F044; +pub const WTIMER5_TAR_R: u32 = 0x4004F048; +pub const WTIMER5_TBR_R: u32 = 0x4004F04C; +pub const WTIMER5_TAV_R: u32 = 0x4004F050; +pub const WTIMER5_TBV_R: u32 = 0x4004F054; +pub const WTIMER5_RTCPD_R: u32 = 0x4004F058; +pub const WTIMER5_TAPS_R: u32 = 0x4004F05C; +pub const WTIMER5_TBPS_R: u32 = 0x4004F060; +pub const WTIMER5_TAPV_R: u32 = 0x4004F064; +pub const WTIMER5_TBPV_R: u32 = 0x4004F068; +pub const WTIMER5_PP_R: u32 = 0x4004FFC0; +//***************************************************************************** +// +// Univeral Serial Bus registers (USB0) +// +//***************************************************************************** +pub const USB0_FADDR_R: u32 = 0x40050000; +pub const USB0_POWER_R: u32 = 0x40050001; +pub const USB0_TXIS_R: u32 = 0x40050002; +pub const USB0_RXIS_R: u32 = 0x40050004; +pub const USB0_TXIE_R: u32 = 0x40050006; +pub const USB0_RXIE_R: u32 = 0x40050008; +pub const USB0_IS_R: u32 = 0x4005000A; +pub const USB0_IE_R: u32 = 0x4005000B; +pub const USB0_FRAME_R: u32 = 0x4005000C; +pub const USB0_EPIDX_R: u32 = 0x4005000E; +pub const USB0_TEST_R: u32 = 0x4005000F; +pub const USB0_FIFO0_R: u32 = 0x40050020; +pub const USB0_FIFO1_R: u32 = 0x40050024; +pub const USB0_FIFO2_R: u32 = 0x40050028; +pub const USB0_FIFO3_R: u32 = 0x4005002C; +pub const USB0_FIFO4_R: u32 = 0x40050030; +pub const USB0_FIFO5_R: u32 = 0x40050034; +pub const USB0_FIFO6_R: u32 = 0x40050038; +pub const USB0_FIFO7_R: u32 = 0x4005003C; +pub const USB0_DEVCTL_R: u32 = 0x40050060; +pub const USB0_TXFIFOSZ_R: u32 = 0x40050062; +pub const USB0_RXFIFOSZ_R: u32 = 0x40050063; +pub const USB0_TXFIFOADD_R: u32 = 0x40050064; +pub const USB0_RXFIFOADD_R: u32 = 0x40050066; +pub const USB0_CONTIM_R: u32 = 0x4005007A; +pub const USB0_VPLEN_R: u32 = 0x4005007B; +pub const USB0_FSEOF_R: u32 = 0x4005007D; +pub const USB0_LSEOF_R: u32 = 0x4005007E; +pub const USB0_TXFUNCADDR0_R: u32 = 0x40050080; +pub const USB0_TXHUBADDR0_R: u32 = 0x40050082; +pub const USB0_TXHUBPORT0_R: u32 = 0x40050083; +pub const USB0_TXFUNCADDR1_R: u32 = 0x40050088; +pub const USB0_TXHUBADDR1_R: u32 = 0x4005008A; +pub const USB0_TXHUBPORT1_R: u32 = 0x4005008B; +pub const USB0_RXFUNCADDR1_R: u32 = 0x4005008C; +pub const USB0_RXHUBADDR1_R: u32 = 0x4005008E; +pub const USB0_RXHUBPORT1_R: u32 = 0x4005008F; +pub const USB0_TXFUNCADDR2_R: u32 = 0x40050090; +pub const USB0_TXHUBADDR2_R: u32 = 0x40050092; +pub const USB0_TXHUBPORT2_R: u32 = 0x40050093; +pub const USB0_RXFUNCADDR2_R: u32 = 0x40050094; +pub const USB0_RXHUBADDR2_R: u32 = 0x40050096; +pub const USB0_RXHUBPORT2_R: u32 = 0x40050097; +pub const USB0_TXFUNCADDR3_R: u32 = 0x40050098; +pub const USB0_TXHUBADDR3_R: u32 = 0x4005009A; +pub const USB0_TXHUBPORT3_R: u32 = 0x4005009B; +pub const USB0_RXFUNCADDR3_R: u32 = 0x4005009C; +pub const USB0_RXHUBADDR3_R: u32 = 0x4005009E; +pub const USB0_RXHUBPORT3_R: u32 = 0x4005009F; +pub const USB0_TXFUNCADDR4_R: u32 = 0x400500A0; +pub const USB0_TXHUBADDR4_R: u32 = 0x400500A2; +pub const USB0_TXHUBPORT4_R: u32 = 0x400500A3; +pub const USB0_RXFUNCADDR4_R: u32 = 0x400500A4; +pub const USB0_RXHUBADDR4_R: u32 = 0x400500A6; +pub const USB0_RXHUBPORT4_R: u32 = 0x400500A7; +pub const USB0_TXFUNCADDR5_R: u32 = 0x400500A8; +pub const USB0_TXHUBADDR5_R: u32 = 0x400500AA; +pub const USB0_TXHUBPORT5_R: u32 = 0x400500AB; +pub const USB0_RXFUNCADDR5_R: u32 = 0x400500AC; +pub const USB0_RXHUBADDR5_R: u32 = 0x400500AE; +pub const USB0_RXHUBPORT5_R: u32 = 0x400500AF; +pub const USB0_TXFUNCADDR6_R: u32 = 0x400500B0; +pub const USB0_TXHUBADDR6_R: u32 = 0x400500B2; +pub const USB0_TXHUBPORT6_R: u32 = 0x400500B3; +pub const USB0_RXFUNCADDR6_R: u32 = 0x400500B4; +pub const USB0_RXHUBADDR6_R: u32 = 0x400500B6; +pub const USB0_RXHUBPORT6_R: u32 = 0x400500B7; +pub const USB0_TXFUNCADDR7_R: u32 = 0x400500B8; +pub const USB0_TXHUBADDR7_R: u32 = 0x400500BA; +pub const USB0_TXHUBPORT7_R: u32 = 0x400500BB; +pub const USB0_RXFUNCADDR7_R: u32 = 0x400500BC; +pub const USB0_RXHUBADDR7_R: u32 = 0x400500BE; +pub const USB0_RXHUBPORT7_R: u32 = 0x400500BF; +pub const USB0_CSRL0_R: u32 = 0x40050102; +pub const USB0_CSRH0_R: u32 = 0x40050103; +pub const USB0_COUNT0_R: u32 = 0x40050108; +pub const USB0_TYPE0_R: u32 = 0x4005010A; +pub const USB0_NAKLMT_R: u32 = 0x4005010B; +pub const USB0_TXMAXP1_R: u32 = 0x40050110; +pub const USB0_TXCSRL1_R: u32 = 0x40050112; +pub const USB0_TXCSRH1_R: u32 = 0x40050113; +pub const USB0_RXMAXP1_R: u32 = 0x40050114; +pub const USB0_RXCSRL1_R: u32 = 0x40050116; +pub const USB0_RXCSRH1_R: u32 = 0x40050117; +pub const USB0_RXCOUNT1_R: u32 = 0x40050118; +pub const USB0_TXTYPE1_R: u32 = 0x4005011A; +pub const USB0_TXINTERVAL1_R: u32 = 0x4005011B; +pub const USB0_RXTYPE1_R: u32 = 0x4005011C; +pub const USB0_RXINTERVAL1_R: u32 = 0x4005011D; +pub const USB0_TXMAXP2_R: u32 = 0x40050120; +pub const USB0_TXCSRL2_R: u32 = 0x40050122; +pub const USB0_TXCSRH2_R: u32 = 0x40050123; +pub const USB0_RXMAXP2_R: u32 = 0x40050124; +pub const USB0_RXCSRL2_R: u32 = 0x40050126; +pub const USB0_RXCSRH2_R: u32 = 0x40050127; +pub const USB0_RXCOUNT2_R: u32 = 0x40050128; +pub const USB0_TXTYPE2_R: u32 = 0x4005012A; +pub const USB0_TXINTERVAL2_R: u32 = 0x4005012B; +pub const USB0_RXTYPE2_R: u32 = 0x4005012C; +pub const USB0_RXINTERVAL2_R: u32 = 0x4005012D; +pub const USB0_TXMAXP3_R: u32 = 0x40050130; +pub const USB0_TXCSRL3_R: u32 = 0x40050132; +pub const USB0_TXCSRH3_R: u32 = 0x40050133; +pub const USB0_RXMAXP3_R: u32 = 0x40050134; +pub const USB0_RXCSRL3_R: u32 = 0x40050136; +pub const USB0_RXCSRH3_R: u32 = 0x40050137; +pub const USB0_RXCOUNT3_R: u32 = 0x40050138; +pub const USB0_TXTYPE3_R: u32 = 0x4005013A; +pub const USB0_TXINTERVAL3_R: u32 = 0x4005013B; +pub const USB0_RXTYPE3_R: u32 = 0x4005013C; +pub const USB0_RXINTERVAL3_R: u32 = 0x4005013D; +pub const USB0_TXMAXP4_R: u32 = 0x40050140; +pub const USB0_TXCSRL4_R: u32 = 0x40050142; +pub const USB0_TXCSRH4_R: u32 = 0x40050143; +pub const USB0_RXMAXP4_R: u32 = 0x40050144; +pub const USB0_RXCSRL4_R: u32 = 0x40050146; +pub const USB0_RXCSRH4_R: u32 = 0x40050147; +pub const USB0_RXCOUNT4_R: u32 = 0x40050148; +pub const USB0_TXTYPE4_R: u32 = 0x4005014A; +pub const USB0_TXINTERVAL4_R: u32 = 0x4005014B; +pub const USB0_RXTYPE4_R: u32 = 0x4005014C; +pub const USB0_RXINTERVAL4_R: u32 = 0x4005014D; +pub const USB0_TXMAXP5_R: u32 = 0x40050150; +pub const USB0_TXCSRL5_R: u32 = 0x40050152; +pub const USB0_TXCSRH5_R: u32 = 0x40050153; +pub const USB0_RXMAXP5_R: u32 = 0x40050154; +pub const USB0_RXCSRL5_R: u32 = 0x40050156; +pub const USB0_RXCSRH5_R: u32 = 0x40050157; +pub const USB0_RXCOUNT5_R: u32 = 0x40050158; +pub const USB0_TXTYPE5_R: u32 = 0x4005015A; +pub const USB0_TXINTERVAL5_R: u32 = 0x4005015B; +pub const USB0_RXTYPE5_R: u32 = 0x4005015C; +pub const USB0_RXINTERVAL5_R: u32 = 0x4005015D; +pub const USB0_TXMAXP6_R: u32 = 0x40050160; +pub const USB0_TXCSRL6_R: u32 = 0x40050162; +pub const USB0_TXCSRH6_R: u32 = 0x40050163; +pub const USB0_RXMAXP6_R: u32 = 0x40050164; +pub const USB0_RXCSRL6_R: u32 = 0x40050166; +pub const USB0_RXCSRH6_R: u32 = 0x40050167; +pub const USB0_RXCOUNT6_R: u32 = 0x40050168; +pub const USB0_TXTYPE6_R: u32 = 0x4005016A; +pub const USB0_TXINTERVAL6_R: u32 = 0x4005016B; +pub const USB0_RXTYPE6_R: u32 = 0x4005016C; +pub const USB0_RXINTERVAL6_R: u32 = 0x4005016D; +pub const USB0_TXMAXP7_R: u32 = 0x40050170; +pub const USB0_TXCSRL7_R: u32 = 0x40050172; +pub const USB0_TXCSRH7_R: u32 = 0x40050173; +pub const USB0_RXMAXP7_R: u32 = 0x40050174; +pub const USB0_RXCSRL7_R: u32 = 0x40050176; +pub const USB0_RXCSRH7_R: u32 = 0x40050177; +pub const USB0_RXCOUNT7_R: u32 = 0x40050178; +pub const USB0_TXTYPE7_R: u32 = 0x4005017A; +pub const USB0_TXINTERVAL7_R: u32 = 0x4005017B; +pub const USB0_RXTYPE7_R: u32 = 0x4005017C; +pub const USB0_RXINTERVAL7_R: u32 = 0x4005017D; +pub const USB0_RQPKTCOUNT1_R: u32 = 0x40050304; +pub const USB0_RQPKTCOUNT2_R: u32 = 0x40050308; +pub const USB0_RQPKTCOUNT3_R: u32 = 0x4005030C; +pub const USB0_RQPKTCOUNT4_R: u32 = 0x40050310; +pub const USB0_RQPKTCOUNT5_R: u32 = 0x40050314; +pub const USB0_RQPKTCOUNT6_R: u32 = 0x40050318; +pub const USB0_RQPKTCOUNT7_R: u32 = 0x4005031C; +pub const USB0_RXDPKTBUFDIS_R: u32 = 0x40050340; +pub const USB0_TXDPKTBUFDIS_R: u32 = 0x40050342; +pub const USB0_EPC_R: u32 = 0x40050400; +pub const USB0_EPCRIS_R: u32 = 0x40050404; +pub const USB0_EPCIM_R: u32 = 0x40050408; +pub const USB0_EPCISC_R: u32 = 0x4005040C; +pub const USB0_DRRIS_R: u32 = 0x40050410; +pub const USB0_DRIM_R: u32 = 0x40050414; +pub const USB0_DRISC_R: u32 = 0x40050418; +pub const USB0_GPCS_R: u32 = 0x4005041C; +pub const USB0_VDC_R: u32 = 0x40050430; +pub const USB0_VDCRIS_R: u32 = 0x40050434; +pub const USB0_VDCIM_R: u32 = 0x40050438; +pub const USB0_VDCISC_R: u32 = 0x4005043C; +pub const USB0_IDVRIS_R: u32 = 0x40050444; +pub const USB0_IDVIM_R: u32 = 0x40050448; +pub const USB0_IDVISC_R: u32 = 0x4005044C; +pub const USB0_DMASEL_R: u32 = 0x40050450; +pub const USB0_PP_R: u32 = 0x40050FC0; +//***************************************************************************** +// +// GPIO registers (PORTA AHB) +// +//***************************************************************************** +pub const GPIO_PORTA_AHB_DATA_BITS_R: u32 = 0x40058000; +pub const GPIO_PORTA_AHB_DATA_R: u32 = 0x400583FC; +pub const GPIO_PORTA_AHB_DIR_R: u32 = 0x40058400; +pub const GPIO_PORTA_AHB_IS_R: u32 = 0x40058404; +pub const GPIO_PORTA_AHB_IBE_R: u32 = 0x40058408; +pub const GPIO_PORTA_AHB_IEV_R: u32 = 0x4005840C; +pub const GPIO_PORTA_AHB_IM_R: u32 = 0x40058410; +pub const GPIO_PORTA_AHB_RIS_R: u32 = 0x40058414; +pub const GPIO_PORTA_AHB_MIS_R: u32 = 0x40058418; +pub const GPIO_PORTA_AHB_ICR_R: u32 = 0x4005841C; +pub const GPIO_PORTA_AHB_AFSEL_R: u32 = 0x40058420; +pub const GPIO_PORTA_AHB_DR2R_R: u32 = 0x40058500; +pub const GPIO_PORTA_AHB_DR4R_R: u32 = 0x40058504; +pub const GPIO_PORTA_AHB_DR8R_R: u32 = 0x40058508; +pub const GPIO_PORTA_AHB_ODR_R: u32 = 0x4005850C; +pub const GPIO_PORTA_AHB_PUR_R: u32 = 0x40058510; +pub const GPIO_PORTA_AHB_PDR_R: u32 = 0x40058514; +pub const GPIO_PORTA_AHB_SLR_R: u32 = 0x40058518; +pub const GPIO_PORTA_AHB_DEN_R: u32 = 0x4005851C; +pub const GPIO_PORTA_AHB_LOCK_R: u32 = 0x40058520; +pub const GPIO_PORTA_AHB_CR_R: u32 = 0x40058524; +pub const GPIO_PORTA_AHB_AMSEL_R: u32 = 0x40058528; +pub const GPIO_PORTA_AHB_PCTL_R: u32 = 0x4005852C; +pub const GPIO_PORTA_AHB_ADCCTL_R: u32 = 0x40058530; +pub const GPIO_PORTA_AHB_DMACTL_R: u32 = 0x40058534; +//***************************************************************************** +// +// GPIO registers (PORTB AHB) +// +//***************************************************************************** +pub const GPIO_PORTB_AHB_DATA_BITS_R: u32 = 0x40059000; +pub const GPIO_PORTB_AHB_DATA_R: u32 = 0x400593FC; +pub const GPIO_PORTB_AHB_DIR_R: u32 = 0x40059400; +pub const GPIO_PORTB_AHB_IS_R: u32 = 0x40059404; +pub const GPIO_PORTB_AHB_IBE_R: u32 = 0x40059408; +pub const GPIO_PORTB_AHB_IEV_R: u32 = 0x4005940C; +pub const GPIO_PORTB_AHB_IM_R: u32 = 0x40059410; +pub const GPIO_PORTB_AHB_RIS_R: u32 = 0x40059414; +pub const GPIO_PORTB_AHB_MIS_R: u32 = 0x40059418; +pub const GPIO_PORTB_AHB_ICR_R: u32 = 0x4005941C; +pub const GPIO_PORTB_AHB_AFSEL_R: u32 = 0x40059420; +pub const GPIO_PORTB_AHB_DR2R_R: u32 = 0x40059500; +pub const GPIO_PORTB_AHB_DR4R_R: u32 = 0x40059504; +pub const GPIO_PORTB_AHB_DR8R_R: u32 = 0x40059508; +pub const GPIO_PORTB_AHB_ODR_R: u32 = 0x4005950C; +pub const GPIO_PORTB_AHB_PUR_R: u32 = 0x40059510; +pub const GPIO_PORTB_AHB_PDR_R: u32 = 0x40059514; +pub const GPIO_PORTB_AHB_SLR_R: u32 = 0x40059518; +pub const GPIO_PORTB_AHB_DEN_R: u32 = 0x4005951C; +pub const GPIO_PORTB_AHB_LOCK_R: u32 = 0x40059520; +pub const GPIO_PORTB_AHB_CR_R: u32 = 0x40059524; +pub const GPIO_PORTB_AHB_AMSEL_R: u32 = 0x40059528; +pub const GPIO_PORTB_AHB_PCTL_R: u32 = 0x4005952C; +pub const GPIO_PORTB_AHB_ADCCTL_R: u32 = 0x40059530; +pub const GPIO_PORTB_AHB_DMACTL_R: u32 = 0x40059534; +//***************************************************************************** +// +// GPIO registers (PORTC AHB) +// +//***************************************************************************** +pub const GPIO_PORTC_AHB_DATA_BITS_R: u32 = 0x4005A000; +pub const GPIO_PORTC_AHB_DATA_R: u32 = 0x4005A3FC; +pub const GPIO_PORTC_AHB_DIR_R: u32 = 0x4005A400; +pub const GPIO_PORTC_AHB_IS_R: u32 = 0x4005A404; +pub const GPIO_PORTC_AHB_IBE_R: u32 = 0x4005A408; +pub const GPIO_PORTC_AHB_IEV_R: u32 = 0x4005A40C; +pub const GPIO_PORTC_AHB_IM_R: u32 = 0x4005A410; +pub const GPIO_PORTC_AHB_RIS_R: u32 = 0x4005A414; +pub const GPIO_PORTC_AHB_MIS_R: u32 = 0x4005A418; +pub const GPIO_PORTC_AHB_ICR_R: u32 = 0x4005A41C; +pub const GPIO_PORTC_AHB_AFSEL_R: u32 = 0x4005A420; +pub const GPIO_PORTC_AHB_DR2R_R: u32 = 0x4005A500; +pub const GPIO_PORTC_AHB_DR4R_R: u32 = 0x4005A504; +pub const GPIO_PORTC_AHB_DR8R_R: u32 = 0x4005A508; +pub const GPIO_PORTC_AHB_ODR_R: u32 = 0x4005A50C; +pub const GPIO_PORTC_AHB_PUR_R: u32 = 0x4005A510; +pub const GPIO_PORTC_AHB_PDR_R: u32 = 0x4005A514; +pub const GPIO_PORTC_AHB_SLR_R: u32 = 0x4005A518; +pub const GPIO_PORTC_AHB_DEN_R: u32 = 0x4005A51C; +pub const GPIO_PORTC_AHB_LOCK_R: u32 = 0x4005A520; +pub const GPIO_PORTC_AHB_CR_R: u32 = 0x4005A524; +pub const GPIO_PORTC_AHB_AMSEL_R: u32 = 0x4005A528; +pub const GPIO_PORTC_AHB_PCTL_R: u32 = 0x4005A52C; +pub const GPIO_PORTC_AHB_ADCCTL_R: u32 = 0x4005A530; +pub const GPIO_PORTC_AHB_DMACTL_R: u32 = 0x4005A534; +//***************************************************************************** +// +// GPIO registers (PORTD AHB) +// +//***************************************************************************** +pub const GPIO_PORTD_AHB_DATA_BITS_R: u32 = 0x4005B000; +pub const GPIO_PORTD_AHB_DATA_R: u32 = 0x4005B3FC; +pub const GPIO_PORTD_AHB_DIR_R: u32 = 0x4005B400; +pub const GPIO_PORTD_AHB_IS_R: u32 = 0x4005B404; +pub const GPIO_PORTD_AHB_IBE_R: u32 = 0x4005B408; +pub const GPIO_PORTD_AHB_IEV_R: u32 = 0x4005B40C; +pub const GPIO_PORTD_AHB_IM_R: u32 = 0x4005B410; +pub const GPIO_PORTD_AHB_RIS_R: u32 = 0x4005B414; +pub const GPIO_PORTD_AHB_MIS_R: u32 = 0x4005B418; +pub const GPIO_PORTD_AHB_ICR_R: u32 = 0x4005B41C; +pub const GPIO_PORTD_AHB_AFSEL_R: u32 = 0x4005B420; +pub const GPIO_PORTD_AHB_DR2R_R: u32 = 0x4005B500; +pub const GPIO_PORTD_AHB_DR4R_R: u32 = 0x4005B504; +pub const GPIO_PORTD_AHB_DR8R_R: u32 = 0x4005B508; +pub const GPIO_PORTD_AHB_ODR_R: u32 = 0x4005B50C; +pub const GPIO_PORTD_AHB_PUR_R: u32 = 0x4005B510; +pub const GPIO_PORTD_AHB_PDR_R: u32 = 0x4005B514; +pub const GPIO_PORTD_AHB_SLR_R: u32 = 0x4005B518; +pub const GPIO_PORTD_AHB_DEN_R: u32 = 0x4005B51C; +pub const GPIO_PORTD_AHB_LOCK_R: u32 = 0x4005B520; +pub const GPIO_PORTD_AHB_CR_R: u32 = 0x4005B524; +pub const GPIO_PORTD_AHB_AMSEL_R: u32 = 0x4005B528; +pub const GPIO_PORTD_AHB_PCTL_R: u32 = 0x4005B52C; +pub const GPIO_PORTD_AHB_ADCCTL_R: u32 = 0x4005B530; +pub const GPIO_PORTD_AHB_DMACTL_R: u32 = 0x4005B534; +//***************************************************************************** +// +// GPIO registers (PORTE AHB) +// +//***************************************************************************** +pub const GPIO_PORTE_AHB_DATA_BITS_R: u32 = 0x4005C000; +pub const GPIO_PORTE_AHB_DATA_R: u32 = 0x4005C3FC; +pub const GPIO_PORTE_AHB_DIR_R: u32 = 0x4005C400; +pub const GPIO_PORTE_AHB_IS_R: u32 = 0x4005C404; +pub const GPIO_PORTE_AHB_IBE_R: u32 = 0x4005C408; +pub const GPIO_PORTE_AHB_IEV_R: u32 = 0x4005C40C; +pub const GPIO_PORTE_AHB_IM_R: u32 = 0x4005C410; +pub const GPIO_PORTE_AHB_RIS_R: u32 = 0x4005C414; +pub const GPIO_PORTE_AHB_MIS_R: u32 = 0x4005C418; +pub const GPIO_PORTE_AHB_ICR_R: u32 = 0x4005C41C; +pub const GPIO_PORTE_AHB_AFSEL_R: u32 = 0x4005C420; +pub const GPIO_PORTE_AHB_DR2R_R: u32 = 0x4005C500; +pub const GPIO_PORTE_AHB_DR4R_R: u32 = 0x4005C504; +pub const GPIO_PORTE_AHB_DR8R_R: u32 = 0x4005C508; +pub const GPIO_PORTE_AHB_ODR_R: u32 = 0x4005C50C; +pub const GPIO_PORTE_AHB_PUR_R: u32 = 0x4005C510; +pub const GPIO_PORTE_AHB_PDR_R: u32 = 0x4005C514; +pub const GPIO_PORTE_AHB_SLR_R: u32 = 0x4005C518; +pub const GPIO_PORTE_AHB_DEN_R: u32 = 0x4005C51C; +pub const GPIO_PORTE_AHB_LOCK_R: u32 = 0x4005C520; +pub const GPIO_PORTE_AHB_CR_R: u32 = 0x4005C524; +pub const GPIO_PORTE_AHB_AMSEL_R: u32 = 0x4005C528; +pub const GPIO_PORTE_AHB_PCTL_R: u32 = 0x4005C52C; +pub const GPIO_PORTE_AHB_ADCCTL_R: u32 = 0x4005C530; +pub const GPIO_PORTE_AHB_DMACTL_R: u32 = 0x4005C534; +//***************************************************************************** +// +// GPIO registers (PORTF AHB) +// +//***************************************************************************** +pub const GPIO_PORTF_AHB_DATA_BITS_R: u32 = 0x4005D000; +pub const GPIO_PORTF_AHB_DATA_R: u32 = 0x4005D3FC; +pub const GPIO_PORTF_AHB_DIR_R: u32 = 0x4005D400; +pub const GPIO_PORTF_AHB_IS_R: u32 = 0x4005D404; +pub const GPIO_PORTF_AHB_IBE_R: u32 = 0x4005D408; +pub const GPIO_PORTF_AHB_IEV_R: u32 = 0x4005D40C; +pub const GPIO_PORTF_AHB_IM_R: u32 = 0x4005D410; +pub const GPIO_PORTF_AHB_RIS_R: u32 = 0x4005D414; +pub const GPIO_PORTF_AHB_MIS_R: u32 = 0x4005D418; +pub const GPIO_PORTF_AHB_ICR_R: u32 = 0x4005D41C; +pub const GPIO_PORTF_AHB_AFSEL_R: u32 = 0x4005D420; +pub const GPIO_PORTF_AHB_DR2R_R: u32 = 0x4005D500; +pub const GPIO_PORTF_AHB_DR4R_R: u32 = 0x4005D504; +pub const GPIO_PORTF_AHB_DR8R_R: u32 = 0x4005D508; +pub const GPIO_PORTF_AHB_ODR_R: u32 = 0x4005D50C; +pub const GPIO_PORTF_AHB_PUR_R: u32 = 0x4005D510; +pub const GPIO_PORTF_AHB_PDR_R: u32 = 0x4005D514; +pub const GPIO_PORTF_AHB_SLR_R: u32 = 0x4005D518; +pub const GPIO_PORTF_AHB_DEN_R: u32 = 0x4005D51C; +pub const GPIO_PORTF_AHB_LOCK_R: u32 = 0x4005D520; +pub const GPIO_PORTF_AHB_CR_R: u32 = 0x4005D524; +pub const GPIO_PORTF_AHB_AMSEL_R: u32 = 0x4005D528; +pub const GPIO_PORTF_AHB_PCTL_R: u32 = 0x4005D52C; +pub const GPIO_PORTF_AHB_ADCCTL_R: u32 = 0x4005D530; +pub const GPIO_PORTF_AHB_DMACTL_R: u32 = 0x4005D534; +//***************************************************************************** +// +// EEPROM registers (EEPROM) +// +//***************************************************************************** +pub const EEPROM_EESIZE_R: u32 = 0x400AF000; +pub const EEPROM_EEBLOCK_R: u32 = 0x400AF004; +pub const EEPROM_EEOFFSET_R: u32 = 0x400AF008; +pub const EEPROM_EERDWR_R: u32 = 0x400AF010; +pub const EEPROM_EERDWRINC_R: u32 = 0x400AF014; +pub const EEPROM_EEDONE_R: u32 = 0x400AF018; +pub const EEPROM_EESUPP_R: u32 = 0x400AF01C; +pub const EEPROM_EEUNLOCK_R: u32 = 0x400AF020; +pub const EEPROM_EEPROT_R: u32 = 0x400AF030; +pub const EEPROM_EEPASS0_R: u32 = 0x400AF034; +pub const EEPROM_EEPASS1_R: u32 = 0x400AF038; +pub const EEPROM_EEPASS2_R: u32 = 0x400AF03C; +pub const EEPROM_EEINT_R: u32 = 0x400AF040; +pub const EEPROM_EEHIDE_R: u32 = 0x400AF050; +pub const EEPROM_EEDBGME_R: u32 = 0x400AF080; +pub const EEPROM_PP_R: u32 = 0x400AFFC0; +//***************************************************************************** +// +// System Exception Module registers (SYSEXC) +// +//***************************************************************************** +pub const SYSEXC_RIS_R: u32 = 0x400F9000; +pub const SYSEXC_IM_R: u32 = 0x400F9004; +pub const SYSEXC_MIS_R: u32 = 0x400F9008; +pub const SYSEXC_IC_R: u32 = 0x400F900C; +//***************************************************************************** +// +// Hibernation module registers (HIB) +// +//***************************************************************************** +pub const HIB_RTCC_R: u32 = 0x400FC000; +pub const HIB_RTCM0_R: u32 = 0x400FC004; +pub const HIB_RTCLD_R: u32 = 0x400FC00C; +pub const HIB_CTL_R: u32 = 0x400FC010; +pub const HIB_IM_R: u32 = 0x400FC014; +pub const HIB_RIS_R: u32 = 0x400FC018; +pub const HIB_MIS_R: u32 = 0x400FC01C; +pub const HIB_IC_R: u32 = 0x400FC020; +pub const HIB_RTCT_R: u32 = 0x400FC024; +pub const HIB_RTCSS_R: u32 = 0x400FC028; +pub const HIB_DATA_R: u32 = 0x400FC030; +//***************************************************************************** +// +// FLASH registers (FLASH CTRL) +// +//***************************************************************************** +pub const FLASH_FMA_R: u32 = 0x400FD000; +pub const FLASH_FMD_R: u32 = 0x400FD004; +pub const FLASH_FMC_R: u32 = 0x400FD008; +pub const FLASH_FCRIS_R: u32 = 0x400FD00C; +pub const FLASH_FCIM_R: u32 = 0x400FD010; +pub const FLASH_FCMISC_R: u32 = 0x400FD014; +pub const FLASH_FMC2_R: u32 = 0x400FD020; +pub const FLASH_FWBVAL_R: u32 = 0x400FD030; +pub const FLASH_FWBN_R: u32 = 0x400FD100; +pub const FLASH_FSIZE_R: u32 = 0x400FDFC0; +pub const FLASH_SSIZE_R: u32 = 0x400FDFC4; +pub const FLASH_ROMSWMAP_R: u32 = 0x400FDFCC; +pub const FLASH_RMCTL_R: u32 = 0x400FE0F0; +pub const FLASH_BOOTCFG_R: u32 = 0x400FE1D0; +pub const FLASH_USERREG0_R: u32 = 0x400FE1E0; +pub const FLASH_USERREG1_R: u32 = 0x400FE1E4; +pub const FLASH_USERREG2_R: u32 = 0x400FE1E8; +pub const FLASH_USERREG3_R: u32 = 0x400FE1EC; +pub const FLASH_FMPRE0_R: u32 = 0x400FE200; +pub const FLASH_FMPRE1_R: u32 = 0x400FE204; +pub const FLASH_FMPRE2_R: u32 = 0x400FE208; +pub const FLASH_FMPRE3_R: u32 = 0x400FE20C; +pub const FLASH_FMPPE0_R: u32 = 0x400FE400; +pub const FLASH_FMPPE1_R: u32 = 0x400FE404; +pub const FLASH_FMPPE2_R: u32 = 0x400FE408; +pub const FLASH_FMPPE3_R: u32 = 0x400FE40C; +//***************************************************************************** +// +// System Control registers (SYSCTL) +// +//***************************************************************************** +pub const SYSCTL_DID0_R: u32 = 0x400FE000; +pub const SYSCTL_DID1_R: u32 = 0x400FE004; +pub const SYSCTL_DC0_R: u32 = 0x400FE008; +pub const SYSCTL_DC1_R: u32 = 0x400FE010; +pub const SYSCTL_DC2_R: u32 = 0x400FE014; +pub const SYSCTL_DC3_R: u32 = 0x400FE018; +pub const SYSCTL_DC4_R: u32 = 0x400FE01C; +pub const SYSCTL_DC5_R: u32 = 0x400FE020; +pub const SYSCTL_DC6_R: u32 = 0x400FE024; +pub const SYSCTL_DC7_R: u32 = 0x400FE028; +pub const SYSCTL_DC8_R: u32 = 0x400FE02C; +pub const SYSCTL_PBORCTL_R: u32 = 0x400FE030; +pub const SYSCTL_SRCR0_R: u32 = 0x400FE040; +pub const SYSCTL_SRCR1_R: u32 = 0x400FE044; +pub const SYSCTL_SRCR2_R: u32 = 0x400FE048; +pub const SYSCTL_RIS_R: u32 = 0x400FE050; +pub const SYSCTL_IMC_R: u32 = 0x400FE054; +pub const SYSCTL_MISC_R: u32 = 0x400FE058; +pub const SYSCTL_RESC_R: u32 = 0x400FE05C; +pub const SYSCTL_RCC_R: u32 = 0x400FE060; +pub const SYSCTL_GPIOHBCTL_R: u32 = 0x400FE06C; +pub const SYSCTL_RCC2_R: u32 = 0x400FE070; +pub const SYSCTL_MOSCCTL_R: u32 = 0x400FE07C; +pub const SYSCTL_RCGC0_R: u32 = 0x400FE100; +pub const SYSCTL_RCGC1_R: u32 = 0x400FE104; +pub const SYSCTL_RCGC2_R: u32 = 0x400FE108; +pub const SYSCTL_SCGC0_R: u32 = 0x400FE110; +pub const SYSCTL_SCGC1_R: u32 = 0x400FE114; +pub const SYSCTL_SCGC2_R: u32 = 0x400FE118; +pub const SYSCTL_DCGC0_R: u32 = 0x400FE120; +pub const SYSCTL_DCGC1_R: u32 = 0x400FE124; +pub const SYSCTL_DCGC2_R: u32 = 0x400FE128; +pub const SYSCTL_DSLPCLKCFG_R: u32 = 0x400FE144; +pub const SYSCTL_SYSPROP_R: u32 = 0x400FE14C; +pub const SYSCTL_PIOSCCAL_R: u32 = 0x400FE150; +pub const SYSCTL_PIOSCSTAT_R: u32 = 0x400FE154; +pub const SYSCTL_PLLFREQ0_R: u32 = 0x400FE160; +pub const SYSCTL_PLLFREQ1_R: u32 = 0x400FE164; +pub const SYSCTL_PLLSTAT_R: u32 = 0x400FE168; +pub const SYSCTL_SLPPWRCFG_R: u32 = 0x400FE188; +pub const SYSCTL_DSLPPWRCFG_R: u32 = 0x400FE18C; +pub const SYSCTL_DC9_R: u32 = 0x400FE190; +pub const SYSCTL_NVMSTAT_R: u32 = 0x400FE1A0; +pub const SYSCTL_LDOSPCTL_R: u32 = 0x400FE1B4; +pub const SYSCTL_LDODPCTL_R: u32 = 0x400FE1BC; +pub const SYSCTL_PPWD_R: u32 = 0x400FE300; +pub const SYSCTL_PPTIMER_R: u32 = 0x400FE304; +pub const SYSCTL_PPGPIO_R: u32 = 0x400FE308; +pub const SYSCTL_PPDMA_R: u32 = 0x400FE30C; +pub const SYSCTL_PPHIB_R: u32 = 0x400FE314; +pub const SYSCTL_PPUART_R: u32 = 0x400FE318; +pub const SYSCTL_PPSSI_R: u32 = 0x400FE31C; +pub const SYSCTL_PPI2C_R: u32 = 0x400FE320; +pub const SYSCTL_PPUSB_R: u32 = 0x400FE328; +pub const SYSCTL_PPCAN_R: u32 = 0x400FE334; +pub const SYSCTL_PPADC_R: u32 = 0x400FE338; +pub const SYSCTL_PPACMP_R: u32 = 0x400FE33C; +pub const SYSCTL_PPPWM_R: u32 = 0x400FE340; +pub const SYSCTL_PPQEI_R: u32 = 0x400FE344; +pub const SYSCTL_PPEEPROM_R: u32 = 0x400FE358; +pub const SYSCTL_PPWTIMER_R: u32 = 0x400FE35C; +pub const SYSCTL_SRWD_R: u32 = 0x400FE500; +pub const SYSCTL_SRTIMER_R: u32 = 0x400FE504; +pub const SYSCTL_SRGPIO_R: u32 = 0x400FE508; +pub const SYSCTL_SRDMA_R: u32 = 0x400FE50C; +pub const SYSCTL_SRHIB_R: u32 = 0x400FE514; +pub const SYSCTL_SRUART_R: u32 = 0x400FE518; +pub const SYSCTL_SRSSI_R: u32 = 0x400FE51C; +pub const SYSCTL_SRI2C_R: u32 = 0x400FE520; +pub const SYSCTL_SRUSB_R: u32 = 0x400FE528; +pub const SYSCTL_SRCAN_R: u32 = 0x400FE534; +pub const SYSCTL_SRADC_R: u32 = 0x400FE538; +pub const SYSCTL_SRACMP_R: u32 = 0x400FE53C; +pub const SYSCTL_SRPWM_R: u32 = 0x400FE540; +pub const SYSCTL_SRQEI_R: u32 = 0x400FE544; +pub const SYSCTL_SREEPROM_R: u32 = 0x400FE558; +pub const SYSCTL_SRWTIMER_R: u32 = 0x400FE55C; +pub const SYSCTL_RCGCWD_R: u32 = 0x400FE600; +pub const SYSCTL_RCGCTIMER_R: u32 = 0x400FE604; +pub const SYSCTL_RCGCGPIO_R: u32 = 0x400FE608; +pub const SYSCTL_RCGCDMA_R: u32 = 0x400FE60C; +pub const SYSCTL_RCGCHIB_R: u32 = 0x400FE614; +pub const SYSCTL_RCGCUART_R: u32 = 0x400FE618; +pub const SYSCTL_RCGCSSI_R: u32 = 0x400FE61C; +pub const SYSCTL_RCGCI2C_R: u32 = 0x400FE620; +pub const SYSCTL_RCGCUSB_R: u32 = 0x400FE628; +pub const SYSCTL_RCGCCAN_R: u32 = 0x400FE634; +pub const SYSCTL_RCGCADC_R: u32 = 0x400FE638; +pub const SYSCTL_RCGCACMP_R: u32 = 0x400FE63C; +pub const SYSCTL_RCGCPWM_R: u32 = 0x400FE640; +pub const SYSCTL_RCGCQEI_R: u32 = 0x400FE644; +pub const SYSCTL_RCGCEEPROM_R: u32 = 0x400FE658; +pub const SYSCTL_RCGCWTIMER_R: u32 = 0x400FE65C; +pub const SYSCTL_SCGCWD_R: u32 = 0x400FE700; +pub const SYSCTL_SCGCTIMER_R: u32 = 0x400FE704; +pub const SYSCTL_SCGCGPIO_R: u32 = 0x400FE708; +pub const SYSCTL_SCGCDMA_R: u32 = 0x400FE70C; +pub const SYSCTL_SCGCHIB_R: u32 = 0x400FE714; +pub const SYSCTL_SCGCUART_R: u32 = 0x400FE718; +pub const SYSCTL_SCGCSSI_R: u32 = 0x400FE71C; +pub const SYSCTL_SCGCI2C_R: u32 = 0x400FE720; +pub const SYSCTL_SCGCUSB_R: u32 = 0x400FE728; +pub const SYSCTL_SCGCCAN_R: u32 = 0x400FE734; +pub const SYSCTL_SCGCADC_R: u32 = 0x400FE738; +pub const SYSCTL_SCGCACMP_R: u32 = 0x400FE73C; +pub const SYSCTL_SCGCPWM_R: u32 = 0x400FE740; +pub const SYSCTL_SCGCQEI_R: u32 = 0x400FE744; +pub const SYSCTL_SCGCEEPROM_R: u32 = 0x400FE758; +pub const SYSCTL_SCGCWTIMER_R: u32 = 0x400FE75C; +pub const SYSCTL_DCGCWD_R: u32 = 0x400FE800; +pub const SYSCTL_DCGCTIMER_R: u32 = 0x400FE804; +pub const SYSCTL_DCGCGPIO_R: u32 = 0x400FE808; +pub const SYSCTL_DCGCDMA_R: u32 = 0x400FE80C; +pub const SYSCTL_DCGCHIB_R: u32 = 0x400FE814; +pub const SYSCTL_DCGCUART_R: u32 = 0x400FE818; +pub const SYSCTL_DCGCSSI_R: u32 = 0x400FE81C; +pub const SYSCTL_DCGCI2C_R: u32 = 0x400FE820; +pub const SYSCTL_DCGCUSB_R: u32 = 0x400FE828; +pub const SYSCTL_DCGCCAN_R: u32 = 0x400FE834; +pub const SYSCTL_DCGCADC_R: u32 = 0x400FE838; +pub const SYSCTL_DCGCACMP_R: u32 = 0x400FE83C; +pub const SYSCTL_DCGCPWM_R: u32 = 0x400FE840; +pub const SYSCTL_DCGCQEI_R: u32 = 0x400FE844; +pub const SYSCTL_DCGCEEPROM_R: u32 = 0x400FE858; +pub const SYSCTL_DCGCWTIMER_R: u32 = 0x400FE85C; +pub const SYSCTL_PRWD_R: u32 = 0x400FEA00; +pub const SYSCTL_PRTIMER_R: u32 = 0x400FEA04; +pub const SYSCTL_PRGPIO_R: u32 = 0x400FEA08; +pub const SYSCTL_PRDMA_R: u32 = 0x400FEA0C; +pub const SYSCTL_PRHIB_R: u32 = 0x400FEA14; +pub const SYSCTL_PRUART_R: u32 = 0x400FEA18; +pub const SYSCTL_PRSSI_R: u32 = 0x400FEA1C; +pub const SYSCTL_PRI2C_R: u32 = 0x400FEA20; +pub const SYSCTL_PRUSB_R: u32 = 0x400FEA28; +pub const SYSCTL_PRCAN_R: u32 = 0x400FEA34; +pub const SYSCTL_PRADC_R: u32 = 0x400FEA38; +pub const SYSCTL_PRACMP_R: u32 = 0x400FEA3C; +pub const SYSCTL_PRPWM_R: u32 = 0x400FEA40; +pub const SYSCTL_PRQEI_R: u32 = 0x400FEA44; +pub const SYSCTL_PREEPROM_R: u32 = 0x400FEA58; +pub const SYSCTL_PRWTIMER_R: u32 = 0x400FEA5C; +//***************************************************************************** +// +// Micro Direct Memory Access registers (UDMA) +// +//***************************************************************************** +pub const UDMA_STAT_R: u32 = 0x400FF000; +pub const UDMA_CFG_R: u32 = 0x400FF004; +pub const UDMA_CTLBASE_R: u32 = 0x400FF008; +pub const UDMA_ALTBASE_R: u32 = 0x400FF00C; +pub const UDMA_WAITSTAT_R: u32 = 0x400FF010; +pub const UDMA_SWREQ_R: u32 = 0x400FF014; +pub const UDMA_USEBURSTSET_R: u32 = 0x400FF018; +pub const UDMA_USEBURSTCLR_R: u32 = 0x400FF01C; +pub const UDMA_REQMASKSET_R: u32 = 0x400FF020; +pub const UDMA_REQMASKCLR_R: u32 = 0x400FF024; +pub const UDMA_ENASET_R: u32 = 0x400FF028; +pub const UDMA_ENACLR_R: u32 = 0x400FF02C; +pub const UDMA_ALTSET_R: u32 = 0x400FF030; +pub const UDMA_ALTCLR_R: u32 = 0x400FF034; +pub const UDMA_PRIOSET_R: u32 = 0x400FF038; +pub const UDMA_PRIOCLR_R: u32 = 0x400FF03C; +pub const UDMA_ERRCLR_R: u32 = 0x400FF04C; +pub const UDMA_CHASGN_R: u32 = 0x400FF500; +pub const UDMA_CHIS_R: u32 = 0x400FF504; +pub const UDMA_CHMAP0_R: u32 = 0x400FF510; +pub const UDMA_CHMAP1_R: u32 = 0x400FF514; +pub const UDMA_CHMAP2_R: u32 = 0x400FF518; +pub const UDMA_CHMAP3_R: u32 = 0x400FF51C; +//***************************************************************************** +// +// Micro Direct Memory Access (uDMA) offsets (UDMA) +// +//***************************************************************************** +pub const UDMA_SRCENDP: u32 = 0x00000000; // DMA Channel Source Address End + // Pointer +pub const UDMA_DSTENDP: u32 = 0x00000004; // DMA Channel Destination Address + // End Pointer +pub const UDMA_CHCTL: u32 = 0x00000008; // DMA Channel Control Word +//***************************************************************************** +// +// NVIC registers (NVIC) +// +//***************************************************************************** +pub const NVIC_ACTLR_R: u32 = 0xE000E008; +pub const NVIC_ST_CTRL_R: u32 = 0xE000E010; +pub const NVIC_ST_RELOAD_R: u32 = 0xE000E014; +pub const NVIC_ST_CURRENT_R: u32 = 0xE000E018; +pub const NVIC_EN0_R: u32 = 0xE000E100; +pub const NVIC_EN1_R: u32 = 0xE000E104; +pub const NVIC_EN2_R: u32 = 0xE000E108; +pub const NVIC_EN3_R: u32 = 0xE000E10C; +pub const NVIC_EN4_R: u32 = 0xE000E110; +pub const NVIC_DIS0_R: u32 = 0xE000E180; +pub const NVIC_DIS1_R: u32 = 0xE000E184; +pub const NVIC_DIS2_R: u32 = 0xE000E188; +pub const NVIC_DIS3_R: u32 = 0xE000E18C; +pub const NVIC_DIS4_R: u32 = 0xE000E190; +pub const NVIC_PEND0_R: u32 = 0xE000E200; +pub const NVIC_PEND1_R: u32 = 0xE000E204; +pub const NVIC_PEND2_R: u32 = 0xE000E208; +pub const NVIC_PEND3_R: u32 = 0xE000E20C; +pub const NVIC_PEND4_R: u32 = 0xE000E210; +pub const NVIC_UNPEND0_R: u32 = 0xE000E280; +pub const NVIC_UNPEND1_R: u32 = 0xE000E284; +pub const NVIC_UNPEND2_R: u32 = 0xE000E288; +pub const NVIC_UNPEND3_R: u32 = 0xE000E28C; +pub const NVIC_UNPEND4_R: u32 = 0xE000E290; +pub const NVIC_ACTIVE0_R: u32 = 0xE000E300; +pub const NVIC_ACTIVE1_R: u32 = 0xE000E304; +pub const NVIC_ACTIVE2_R: u32 = 0xE000E308; +pub const NVIC_ACTIVE3_R: u32 = 0xE000E30C; +pub const NVIC_ACTIVE4_R: u32 = 0xE000E310; +pub const NVIC_PRI0_R: u32 = 0xE000E400; +pub const NVIC_PRI1_R: u32 = 0xE000E404; +pub const NVIC_PRI2_R: u32 = 0xE000E408; +pub const NVIC_PRI3_R: u32 = 0xE000E40C; +pub const NVIC_PRI4_R: u32 = 0xE000E410; +pub const NVIC_PRI5_R: u32 = 0xE000E414; +pub const NVIC_PRI6_R: u32 = 0xE000E418; +pub const NVIC_PRI7_R: u32 = 0xE000E41C; +pub const NVIC_PRI8_R: u32 = 0xE000E420; +pub const NVIC_PRI9_R: u32 = 0xE000E424; +pub const NVIC_PRI10_R: u32 = 0xE000E428; +pub const NVIC_PRI11_R: u32 = 0xE000E42C; +pub const NVIC_PRI12_R: u32 = 0xE000E430; +pub const NVIC_PRI13_R: u32 = 0xE000E434; +pub const NVIC_PRI14_R: u32 = 0xE000E438; +pub const NVIC_PRI15_R: u32 = 0xE000E43C; +pub const NVIC_PRI16_R: u32 = 0xE000E440; +pub const NVIC_PRI17_R: u32 = 0xE000E444; +pub const NVIC_PRI18_R: u32 = 0xE000E448; +pub const NVIC_PRI19_R: u32 = 0xE000E44C; +pub const NVIC_PRI20_R: u32 = 0xE000E450; +pub const NVIC_PRI21_R: u32 = 0xE000E454; +pub const NVIC_PRI22_R: u32 = 0xE000E458; +pub const NVIC_PRI23_R: u32 = 0xE000E45C; +pub const NVIC_PRI24_R: u32 = 0xE000E460; +pub const NVIC_PRI25_R: u32 = 0xE000E464; +pub const NVIC_PRI26_R: u32 = 0xE000E468; +pub const NVIC_PRI27_R: u32 = 0xE000E46C; +pub const NVIC_PRI28_R: u32 = 0xE000E470; +pub const NVIC_PRI29_R: u32 = 0xE000E474; +pub const NVIC_PRI30_R: u32 = 0xE000E478; +pub const NVIC_PRI31_R: u32 = 0xE000E47C; +pub const NVIC_PRI32_R: u32 = 0xE000E480; +pub const NVIC_PRI33_R: u32 = 0xE000E484; +pub const NVIC_PRI34_R: u32 = 0xE000E488; +pub const NVIC_CPUID_R: u32 = 0xE000ED00; +pub const NVIC_INT_CTRL_R: u32 = 0xE000ED04; +pub const NVIC_VTABLE_R: u32 = 0xE000ED08; +pub const NVIC_APINT_R: u32 = 0xE000ED0C; +pub const NVIC_SYS_CTRL_R: u32 = 0xE000ED10; +pub const NVIC_CFG_CTRL_R: u32 = 0xE000ED14; +pub const NVIC_SYS_PRI1_R: u32 = 0xE000ED18; +pub const NVIC_SYS_PRI2_R: u32 = 0xE000ED1C; +pub const NVIC_SYS_PRI3_R: u32 = 0xE000ED20; +pub const NVIC_SYS_HND_CTRL_R: u32 = 0xE000ED24; +pub const NVIC_FAULT_STAT_R: u32 = 0xE000ED28; +pub const NVIC_HFAULT_STAT_R: u32 = 0xE000ED2C; +pub const NVIC_DEBUG_STAT_R: u32 = 0xE000ED30; +pub const NVIC_MM_ADDR_R: u32 = 0xE000ED34; +pub const NVIC_FAULT_ADDR_R: u32 = 0xE000ED38; +pub const NVIC_CPAC_R: u32 = 0xE000ED88; +pub const NVIC_MPU_TYPE_R: u32 = 0xE000ED90; +pub const NVIC_MPU_CTRL_R: u32 = 0xE000ED94; +pub const NVIC_MPU_NUMBER_R: u32 = 0xE000ED98; +pub const NVIC_MPU_BASE_R: u32 = 0xE000ED9C; +pub const NVIC_MPU_ATTR_R: u32 = 0xE000EDA0; +pub const NVIC_MPU_BASE1_R: u32 = 0xE000EDA4; +pub const NVIC_MPU_ATTR1_R: u32 = 0xE000EDA8; +pub const NVIC_MPU_BASE2_R: u32 = 0xE000EDAC; +pub const NVIC_MPU_ATTR2_R: u32 = 0xE000EDB0; +pub const NVIC_MPU_BASE3_R: u32 = 0xE000EDB4; +pub const NVIC_MPU_ATTR3_R: u32 = 0xE000EDB8; +pub const NVIC_DBG_CTRL_R: u32 = 0xE000EDF0; +pub const NVIC_DBG_XFER_R: u32 = 0xE000EDF4; +pub const NVIC_DBG_DATA_R: u32 = 0xE000EDF8; +pub const NVIC_DBG_INT_R: u32 = 0xE000EDFC; +pub const NVIC_SW_TRIG_R: u32 = 0xE000EF00; +pub const NVIC_FPCC_R: u32 = 0xE000EF34; +pub const NVIC_FPCA_R: u32 = 0xE000EF38; +pub const NVIC_FPDSC_R: u32 = 0xE000EF3C; +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//***************************************************************************** +pub const WDT_LOAD_M: u32 = 0xFFFFFFFF; // Watchdog Load Value +pub const WDT_LOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//***************************************************************************** +pub const WDT_VALUE_M: u32 = 0xFFFFFFFF; // Watchdog Value +pub const WDT_VALUE_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//***************************************************************************** +pub const WDT_CTL_WRC: u32 = 0x80000000; // Write Complete +pub const WDT_CTL_INTTYPE: u32 = 0x00000004; // Watchdog Interrupt Type +pub const WDT_CTL_RESEN: u32 = 0x00000002; // Watchdog Reset Enable +pub const WDT_CTL_INTEN: u32 = 0x00000001; // Watchdog Interrupt Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//***************************************************************************** +pub const WDT_ICR_M: u32 = 0xFFFFFFFF; // Watchdog Interrupt Clear +pub const WDT_ICR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//***************************************************************************** +pub const WDT_RIS_WDTRIS: u32 = 0x00000001; // Watchdog Raw Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//***************************************************************************** +pub const WDT_MIS_WDTMIS: u32 = 0x00000001; // Watchdog Masked Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//***************************************************************************** +pub const WDT_TEST_STALL: u32 = 0x00000100; // Watchdog Stall Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +pub const WDT_LOCK_M: u32 = 0xFFFFFFFF; // Watchdog Lock +pub const WDT_LOCK_UNLOCKED: u32 = 0x00000000; // Unlocked +pub const WDT_LOCK_LOCKED: u32 = 0x00000001; // Locked +pub const WDT_LOCK_UNLOCK: u32 = 0x1ACCE551; // Unlocks the watchdog timer +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_IM register. +// +//***************************************************************************** +pub const GPIO_IM_GPIO_M: u32 = 0x000000FF; // GPIO Interrupt Mask Enable +pub const GPIO_IM_GPIO_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_RIS register. +// +//***************************************************************************** +pub const GPIO_RIS_GPIO_M: u32 = 0x000000FF; // GPIO Interrupt Raw Status +pub const GPIO_RIS_GPIO_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_MIS register. +// +//***************************************************************************** +pub const GPIO_MIS_GPIO_M: u32 = 0x000000FF; // GPIO Masked Interrupt Status +pub const GPIO_MIS_GPIO_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_ICR register. +// +//***************************************************************************** +pub const GPIO_ICR_GPIO_M: u32 = 0x000000FF; // GPIO Interrupt Clear +pub const GPIO_ICR_GPIO_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_LOCK register. +// +//***************************************************************************** +pub const GPIO_LOCK_M: u32 = 0xFFFFFFFF; // GPIO Lock +pub const GPIO_LOCK_UNLOCKED: u32 = 0x00000000; // The GPIOCR register is unlocked + // and may be modified +pub const GPIO_LOCK_LOCKED: u32 = 0x00000001; // The GPIOCR register is locked + // and may not be modified +pub const GPIO_LOCK_KEY: u32 = 0x4C4F434B; // Unlocks the GPIO_CR register +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port A. +// +//***************************************************************************** +pub const GPIO_PCTL_PA7_M: u32 = 0xF0000000; // PA7 Mask +pub const GPIO_PCTL_PA7_I2C1SDA: u32 = 0x30000000; // I2C1SDA on PA7 +pub const GPIO_PCTL_PA7_M1PWM3: u32 = 0x50000000; // M1PWM3 on PA7 +pub const GPIO_PCTL_PA6_M: u32 = 0x0F000000; // PA6 Mask +pub const GPIO_PCTL_PA6_I2C1SCL: u32 = 0x03000000; // I2C1SCL on PA6 +pub const GPIO_PCTL_PA6_M1PWM2: u32 = 0x05000000; // M1PWM2 on PA6 +pub const GPIO_PCTL_PA5_M: u32 = 0x00F00000; // PA5 Mask +pub const GPIO_PCTL_PA5_SSI0TX: u32 = 0x00200000; // SSI0TX on PA5 +pub const GPIO_PCTL_PA4_M: u32 = 0x000F0000; // PA4 Mask +pub const GPIO_PCTL_PA4_SSI0RX: u32 = 0x00020000; // SSI0RX on PA4 +pub const GPIO_PCTL_PA3_M: u32 = 0x0000F000; // PA3 Mask +pub const GPIO_PCTL_PA3_SSI0FSS: u32 = 0x00002000; // SSI0FSS on PA3 +pub const GPIO_PCTL_PA2_M: u32 = 0x00000F00; // PA2 Mask +pub const GPIO_PCTL_PA2_SSI0CLK: u32 = 0x00000200; // SSI0CLK on PA2 +pub const GPIO_PCTL_PA1_M: u32 = 0x000000F0; // PA1 Mask +pub const GPIO_PCTL_PA1_U0TX: u32 = 0x00000010; // U0TX on PA1 +pub const GPIO_PCTL_PA1_CAN1TX: u32 = 0x00000080; // CAN1TX on PA1 +pub const GPIO_PCTL_PA0_M: u32 = 0x0000000F; // PA0 Mask +pub const GPIO_PCTL_PA0_U0RX: u32 = 0x00000001; // U0RX on PA0 +pub const GPIO_PCTL_PA0_CAN1RX: u32 = 0x00000008; // CAN1RX on PA0 +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port B. +// +//***************************************************************************** +pub const GPIO_PCTL_PB7_M: u32 = 0xF0000000; // PB7 Mask +pub const GPIO_PCTL_PB7_SSI2TX: u32 = 0x20000000; // SSI2TX on PB7 +pub const GPIO_PCTL_PB7_M0PWM1: u32 = 0x40000000; // M0PWM1 on PB7 +pub const GPIO_PCTL_PB7_T0CCP1: u32 = 0x70000000; // T0CCP1 on PB7 +pub const GPIO_PCTL_PB6_M: u32 = 0x0F000000; // PB6 Mask +pub const GPIO_PCTL_PB6_SSI2RX: u32 = 0x02000000; // SSI2RX on PB6 +pub const GPIO_PCTL_PB6_M0PWM0: u32 = 0x04000000; // M0PWM0 on PB6 +pub const GPIO_PCTL_PB6_T0CCP0: u32 = 0x07000000; // T0CCP0 on PB6 +pub const GPIO_PCTL_PB5_M: u32 = 0x00F00000; // PB5 Mask +pub const GPIO_PCTL_PB5_SSI2FSS: u32 = 0x00200000; // SSI2FSS on PB5 +pub const GPIO_PCTL_PB5_M0PWM3: u32 = 0x00400000; // M0PWM3 on PB5 +pub const GPIO_PCTL_PB5_T1CCP1: u32 = 0x00700000; // T1CCP1 on PB5 +pub const GPIO_PCTL_PB5_CAN0TX: u32 = 0x00800000; // CAN0TX on PB5 +pub const GPIO_PCTL_PB4_M: u32 = 0x000F0000; // PB4 Mask +pub const GPIO_PCTL_PB4_SSI2CLK: u32 = 0x00020000; // SSI2CLK on PB4 +pub const GPIO_PCTL_PB4_M0PWM2: u32 = 0x00040000; // M0PWM2 on PB4 +pub const GPIO_PCTL_PB4_T1CCP0: u32 = 0x00070000; // T1CCP0 on PB4 +pub const GPIO_PCTL_PB4_CAN0RX: u32 = 0x00080000; // CAN0RX on PB4 +pub const GPIO_PCTL_PB3_M: u32 = 0x0000F000; // PB3 Mask +pub const GPIO_PCTL_PB3_I2C0SDA: u32 = 0x00003000; // I2C0SDA on PB3 +pub const GPIO_PCTL_PB3_T3CCP1: u32 = 0x00007000; // T3CCP1 on PB3 +pub const GPIO_PCTL_PB2_M: u32 = 0x00000F00; // PB2 Mask +pub const GPIO_PCTL_PB2_I2C0SCL: u32 = 0x00000300; // I2C0SCL on PB2 +pub const GPIO_PCTL_PB2_T3CCP0: u32 = 0x00000700; // T3CCP0 on PB2 +pub const GPIO_PCTL_PB1_M: u32 = 0x000000F0; // PB1 Mask +pub const GPIO_PCTL_PB1_USB0VBUS: u32 = 0x00000000; // USB0VBUS on PB1 +pub const GPIO_PCTL_PB1_U1TX: u32 = 0x00000010; // U1TX on PB1 +pub const GPIO_PCTL_PB1_T2CCP1: u32 = 0x00000070; // T2CCP1 on PB1 +pub const GPIO_PCTL_PB0_M: u32 = 0x0000000F; // PB0 Mask +pub const GPIO_PCTL_PB0_USB0ID: u32 = 0x00000000; // USB0ID on PB0 +pub const GPIO_PCTL_PB0_U1RX: u32 = 0x00000001; // U1RX on PB0 +pub const GPIO_PCTL_PB0_T2CCP0: u32 = 0x00000007; // T2CCP0 on PB0 +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port C. +// +//***************************************************************************** +pub const GPIO_PCTL_PC7_M: u32 = 0xF0000000; // PC7 Mask +pub const GPIO_PCTL_PC7_U3TX: u32 = 0x10000000; // U3TX on PC7 +pub const GPIO_PCTL_PC7_WT1CCP1: u32 = 0x70000000; // WT1CCP1 on PC7 +pub const GPIO_PCTL_PC7_USB0PFLT: u32 = 0x80000000; // USB0PFLT on PC7 +pub const GPIO_PCTL_PC6_M: u32 = 0x0F000000; // PC6 Mask +pub const GPIO_PCTL_PC6_U3RX: u32 = 0x01000000; // U3RX on PC6 +pub const GPIO_PCTL_PC6_PHB1: u32 = 0x06000000; // PHB1 on PC6 +pub const GPIO_PCTL_PC6_WT1CCP0: u32 = 0x07000000; // WT1CCP0 on PC6 +pub const GPIO_PCTL_PC6_USB0EPEN: u32 = 0x08000000; // USB0EPEN on PC6 +pub const GPIO_PCTL_PC5_M: u32 = 0x00F00000; // PC5 Mask +pub const GPIO_PCTL_PC5_U4TX: u32 = 0x00100000; // U4TX on PC5 +pub const GPIO_PCTL_PC5_U1TX: u32 = 0x00200000; // U1TX on PC5 +pub const GPIO_PCTL_PC5_M0PWM7: u32 = 0x00400000; // M0PWM7 on PC5 +pub const GPIO_PCTL_PC5_PHA1: u32 = 0x00600000; // PHA1 on PC5 +pub const GPIO_PCTL_PC5_WT0CCP1: u32 = 0x00700000; // WT0CCP1 on PC5 +pub const GPIO_PCTL_PC5_U1CTS: u32 = 0x00800000; // U1CTS on PC5 +pub const GPIO_PCTL_PC4_M: u32 = 0x000F0000; // PC4 Mask +pub const GPIO_PCTL_PC4_U4RX: u32 = 0x00010000; // U4RX on PC4 +pub const GPIO_PCTL_PC4_U1RX: u32 = 0x00020000; // U1RX on PC4 +pub const GPIO_PCTL_PC4_M0PWM6: u32 = 0x00040000; // M0PWM6 on PC4 +pub const GPIO_PCTL_PC4_IDX1: u32 = 0x00060000; // IDX1 on PC4 +pub const GPIO_PCTL_PC4_WT0CCP0: u32 = 0x00070000; // WT0CCP0 on PC4 +pub const GPIO_PCTL_PC4_U1RTS: u32 = 0x00080000; // U1RTS on PC4 +pub const GPIO_PCTL_PC3_M: u32 = 0x0000F000; // PC3 Mask +pub const GPIO_PCTL_PC3_TDO: u32 = 0x00001000; // TDO on PC3 +pub const GPIO_PCTL_PC3_T5CCP1: u32 = 0x00007000; // T5CCP1 on PC3 +pub const GPIO_PCTL_PC2_M: u32 = 0x00000F00; // PC2 Mask +pub const GPIO_PCTL_PC2_TDI: u32 = 0x00000100; // TDI on PC2 +pub const GPIO_PCTL_PC2_T5CCP0: u32 = 0x00000700; // T5CCP0 on PC2 +pub const GPIO_PCTL_PC1_M: u32 = 0x000000F0; // PC1 Mask +pub const GPIO_PCTL_PC1_TMS: u32 = 0x00000010; // TMS on PC1 +pub const GPIO_PCTL_PC1_T4CCP1: u32 = 0x00000070; // T4CCP1 on PC1 +pub const GPIO_PCTL_PC0_M: u32 = 0x0000000F; // PC0 Mask +pub const GPIO_PCTL_PC0_TCK: u32 = 0x00000001; // TCK on PC0 +pub const GPIO_PCTL_PC0_T4CCP0: u32 = 0x00000007; // T4CCP0 on PC0 +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port D. +// +//***************************************************************************** +pub const GPIO_PCTL_PD7_M: u32 = 0xF0000000; // PD7 Mask +pub const GPIO_PCTL_PD7_U2TX: u32 = 0x10000000; // U2TX on PD7 +pub const GPIO_PCTL_PD7_PHB0: u32 = 0x60000000; // PHB0 on PD7 +pub const GPIO_PCTL_PD7_WT5CCP1: u32 = 0x70000000; // WT5CCP1 on PD7 +pub const GPIO_PCTL_PD7_NMI: u32 = 0x80000000; // NMI on PD7 +pub const GPIO_PCTL_PD6_M: u32 = 0x0F000000; // PD6 Mask +pub const GPIO_PCTL_PD6_U2RX: u32 = 0x01000000; // U2RX on PD6 +pub const GPIO_PCTL_PD6_M0FAULT0: u32 = 0x04000000; // M0FAULT0 on PD6 +pub const GPIO_PCTL_PD6_PHA0: u32 = 0x06000000; // PHA0 on PD6 +pub const GPIO_PCTL_PD6_WT5CCP0: u32 = 0x07000000; // WT5CCP0 on PD6 +pub const GPIO_PCTL_PD5_M: u32 = 0x00F00000; // PD5 Mask +pub const GPIO_PCTL_PD5_USB0DP: u32 = 0x00000000; // USB0DP on PD5 +pub const GPIO_PCTL_PD5_U6TX: u32 = 0x00100000; // U6TX on PD5 +pub const GPIO_PCTL_PD5_WT4CCP1: u32 = 0x00700000; // WT4CCP1 on PD5 +pub const GPIO_PCTL_PD4_M: u32 = 0x000F0000; // PD4 Mask +pub const GPIO_PCTL_PD4_USB0DM: u32 = 0x00000000; // USB0DM on PD4 +pub const GPIO_PCTL_PD4_U6RX: u32 = 0x00010000; // U6RX on PD4 +pub const GPIO_PCTL_PD4_WT4CCP0: u32 = 0x00070000; // WT4CCP0 on PD4 +pub const GPIO_PCTL_PD3_M: u32 = 0x0000F000; // PD3 Mask +pub const GPIO_PCTL_PD3_AIN4: u32 = 0x00000000; // AIN4 on PD3 +pub const GPIO_PCTL_PD3_SSI3TX: u32 = 0x00001000; // SSI3TX on PD3 +pub const GPIO_PCTL_PD3_SSI1TX: u32 = 0x00002000; // SSI1TX on PD3 +pub const GPIO_PCTL_PD3_IDX0: u32 = 0x00006000; // IDX0 on PD3 +pub const GPIO_PCTL_PD3_WT3CCP1: u32 = 0x00007000; // WT3CCP1 on PD3 +pub const GPIO_PCTL_PD3_USB0PFLT: u32 = 0x00008000; // USB0PFLT on PD3 +pub const GPIO_PCTL_PD2_M: u32 = 0x00000F00; // PD2 Mask +pub const GPIO_PCTL_PD2_AIN5: u32 = 0x00000000; // AIN5 on PD2 +pub const GPIO_PCTL_PD2_SSI3RX: u32 = 0x00000100; // SSI3RX on PD2 +pub const GPIO_PCTL_PD2_SSI1RX: u32 = 0x00000200; // SSI1RX on PD2 +pub const GPIO_PCTL_PD2_M0FAULT0: u32 = 0x00000400; // M0FAULT0 on PD2 +pub const GPIO_PCTL_PD2_WT3CCP0: u32 = 0x00000700; // WT3CCP0 on PD2 +pub const GPIO_PCTL_PD2_USB0EPEN: u32 = 0x00000800; // USB0EPEN on PD2 +pub const GPIO_PCTL_PD1_M: u32 = 0x000000F0; // PD1 Mask +pub const GPIO_PCTL_PD1_AIN6: u32 = 0x00000000; // AIN6 on PD1 +pub const GPIO_PCTL_PD1_SSI3FSS: u32 = 0x00000010; // SSI3FSS on PD1 +pub const GPIO_PCTL_PD1_SSI1FSS: u32 = 0x00000020; // SSI1FSS on PD1 +pub const GPIO_PCTL_PD1_I2C3SDA: u32 = 0x00000030; // I2C3SDA on PD1 +pub const GPIO_PCTL_PD1_M0PWM7: u32 = 0x00000040; // M0PWM7 on PD1 +pub const GPIO_PCTL_PD1_M1PWM1: u32 = 0x00000050; // M1PWM1 on PD1 +pub const GPIO_PCTL_PD1_WT2CCP1: u32 = 0x00000070; // WT2CCP1 on PD1 +pub const GPIO_PCTL_PD0_M: u32 = 0x0000000F; // PD0 Mask +pub const GPIO_PCTL_PD0_AIN7: u32 = 0x00000000; // AIN7 on PD0 +pub const GPIO_PCTL_PD0_SSI3CLK: u32 = 0x00000001; // SSI3CLK on PD0 +pub const GPIO_PCTL_PD0_SSI1CLK: u32 = 0x00000002; // SSI1CLK on PD0 +pub const GPIO_PCTL_PD0_I2C3SCL: u32 = 0x00000003; // I2C3SCL on PD0 +pub const GPIO_PCTL_PD0_M0PWM6: u32 = 0x00000004; // M0PWM6 on PD0 +pub const GPIO_PCTL_PD0_M1PWM0: u32 = 0x00000005; // M1PWM0 on PD0 +pub const GPIO_PCTL_PD0_WT2CCP0: u32 = 0x00000007; // WT2CCP0 on PD0 +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port E. +// +//***************************************************************************** +pub const GPIO_PCTL_PE5_M: u32 = 0x00F00000; // PE5 Mask +pub const GPIO_PCTL_PE5_AIN8: u32 = 0x00000000; // AIN8 on PE5 +pub const GPIO_PCTL_PE5_U5TX: u32 = 0x00100000; // U5TX on PE5 +pub const GPIO_PCTL_PE5_I2C2SDA: u32 = 0x00300000; // I2C2SDA on PE5 +pub const GPIO_PCTL_PE5_M0PWM5: u32 = 0x00400000; // M0PWM5 on PE5 +pub const GPIO_PCTL_PE5_M1PWM3: u32 = 0x00500000; // M1PWM3 on PE5 +pub const GPIO_PCTL_PE5_CAN0TX: u32 = 0x00800000; // CAN0TX on PE5 +pub const GPIO_PCTL_PE4_M: u32 = 0x000F0000; // PE4 Mask +pub const GPIO_PCTL_PE4_AIN9: u32 = 0x00000000; // AIN9 on PE4 +pub const GPIO_PCTL_PE4_U5RX: u32 = 0x00010000; // U5RX on PE4 +pub const GPIO_PCTL_PE4_I2C2SCL: u32 = 0x00030000; // I2C2SCL on PE4 +pub const GPIO_PCTL_PE4_M0PWM4: u32 = 0x00040000; // M0PWM4 on PE4 +pub const GPIO_PCTL_PE4_M1PWM2: u32 = 0x00050000; // M1PWM2 on PE4 +pub const GPIO_PCTL_PE4_CAN0RX: u32 = 0x00080000; // CAN0RX on PE4 +pub const GPIO_PCTL_PE3_M: u32 = 0x0000F000; // PE3 Mask +pub const GPIO_PCTL_PE3_AIN0: u32 = 0x00000000; // AIN0 on PE3 +pub const GPIO_PCTL_PE2_M: u32 = 0x00000F00; // PE2 Mask +pub const GPIO_PCTL_PE2_AIN1: u32 = 0x00000000; // AIN1 on PE2 +pub const GPIO_PCTL_PE1_M: u32 = 0x000000F0; // PE1 Mask +pub const GPIO_PCTL_PE1_AIN2: u32 = 0x00000000; // AIN2 on PE1 +pub const GPIO_PCTL_PE1_U7TX: u32 = 0x00000010; // U7TX on PE1 +pub const GPIO_PCTL_PE0_M: u32 = 0x0000000F; // PE0 Mask +pub const GPIO_PCTL_PE0_AIN3: u32 = 0x00000000; // AIN3 on PE0 +pub const GPIO_PCTL_PE0_U7RX: u32 = 0x00000001; // U7RX on PE0 +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port F. +// +//***************************************************************************** +pub const GPIO_PCTL_PF4_M: u32 = 0x000F0000; // PF4 Mask +pub const GPIO_PCTL_PF4_M1FAULT0: u32 = 0x00050000; // M1FAULT0 on PF4 +pub const GPIO_PCTL_PF4_IDX0: u32 = 0x00060000; // IDX0 on PF4 +pub const GPIO_PCTL_PF4_T2CCP0: u32 = 0x00070000; // T2CCP0 on PF4 +pub const GPIO_PCTL_PF4_USB0EPEN: u32 = 0x00080000; // USB0EPEN on PF4 +pub const GPIO_PCTL_PF3_M: u32 = 0x0000F000; // PF3 Mask +pub const GPIO_PCTL_PF3_SSI1FSS: u32 = 0x00002000; // SSI1FSS on PF3 +pub const GPIO_PCTL_PF3_CAN0TX: u32 = 0x00003000; // CAN0TX on PF3 +pub const GPIO_PCTL_PF3_M1PWM7: u32 = 0x00005000; // M1PWM7 on PF3 +pub const GPIO_PCTL_PF3_T1CCP1: u32 = 0x00007000; // T1CCP1 on PF3 +pub const GPIO_PCTL_PF3_TRCLK: u32 = 0x0000E000; // TRCLK on PF3 +pub const GPIO_PCTL_PF2_M: u32 = 0x00000F00; // PF2 Mask +pub const GPIO_PCTL_PF2_SSI1CLK: u32 = 0x00000200; // SSI1CLK on PF2 +pub const GPIO_PCTL_PF2_M0FAULT0: u32 = 0x00000400; // M0FAULT0 on PF2 +pub const GPIO_PCTL_PF2_M1PWM6: u32 = 0x00000500; // M1PWM6 on PF2 +pub const GPIO_PCTL_PF2_T1CCP0: u32 = 0x00000700; // T1CCP0 on PF2 +pub const GPIO_PCTL_PF2_TRD0: u32 = 0x00000E00; // TRD0 on PF2 +pub const GPIO_PCTL_PF1_M: u32 = 0x000000F0; // PF1 Mask +pub const GPIO_PCTL_PF1_U1CTS: u32 = 0x00000010; // U1CTS on PF1 +pub const GPIO_PCTL_PF1_SSI1TX: u32 = 0x00000020; // SSI1TX on PF1 +pub const GPIO_PCTL_PF1_M1PWM5: u32 = 0x00000050; // M1PWM5 on PF1 +pub const GPIO_PCTL_PF1_PHB0: u32 = 0x00000060; // PHB0 on PF1 +pub const GPIO_PCTL_PF1_T0CCP1: u32 = 0x00000070; // T0CCP1 on PF1 +pub const GPIO_PCTL_PF1_C1O: u32 = 0x00000090; // C1O on PF1 +pub const GPIO_PCTL_PF1_TRD1: u32 = 0x000000E0; // TRD1 on PF1 +pub const GPIO_PCTL_PF0_M: u32 = 0x0000000F; // PF0 Mask +pub const GPIO_PCTL_PF0_U1RTS: u32 = 0x00000001; // U1RTS on PF0 +pub const GPIO_PCTL_PF0_SSI1RX: u32 = 0x00000002; // SSI1RX on PF0 +pub const GPIO_PCTL_PF0_CAN0RX: u32 = 0x00000003; // CAN0RX on PF0 +pub const GPIO_PCTL_PF0_M1PWM4: u32 = 0x00000005; // M1PWM4 on PF0 +pub const GPIO_PCTL_PF0_PHA0: u32 = 0x00000006; // PHA0 on PF0 +pub const GPIO_PCTL_PF0_T0CCP0: u32 = 0x00000007; // T0CCP0 on PF0 +pub const GPIO_PCTL_PF0_NMI: u32 = 0x00000008; // NMI on PF0 +pub const GPIO_PCTL_PF0_C0O: u32 = 0x00000009; // C0O on PF0 +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR0 register. +// +//***************************************************************************** +pub const SSI_CR0_SCR_M: u32 = 0x0000FF00; // SSI Serial Clock Rate +pub const SSI_CR0_SPH: u32 = 0x00000080; // SSI Serial Clock Phase +pub const SSI_CR0_SPO: u32 = 0x00000040; // SSI Serial Clock Polarity +pub const SSI_CR0_FRF_M: u32 = 0x00000030; // SSI Frame Format Select +pub const SSI_CR0_FRF_MOTO: u32 = 0x00000000; // Freescale SPI Frame Format +pub const SSI_CR0_FRF_TI: u32 = 0x00000010; // Synchronous Serial Frame Format +pub const SSI_CR0_FRF_NMW: u32 = 0x00000020; // MICROWIRE Frame Format +pub const SSI_CR0_DSS_M: u32 = 0x0000000F; // SSI Data Size Select +pub const SSI_CR0_DSS_4: u32 = 0x00000003; // 4-bit data +pub const SSI_CR0_DSS_5: u32 = 0x00000004; // 5-bit data +pub const SSI_CR0_DSS_6: u32 = 0x00000005; // 6-bit data +pub const SSI_CR0_DSS_7: u32 = 0x00000006; // 7-bit data +pub const SSI_CR0_DSS_8: u32 = 0x00000007; // 8-bit data +pub const SSI_CR0_DSS_9: u32 = 0x00000008; // 9-bit data +pub const SSI_CR0_DSS_10: u32 = 0x00000009; // 10-bit data +pub const SSI_CR0_DSS_11: u32 = 0x0000000A; // 11-bit data +pub const SSI_CR0_DSS_12: u32 = 0x0000000B; // 12-bit data +pub const SSI_CR0_DSS_13: u32 = 0x0000000C; // 13-bit data +pub const SSI_CR0_DSS_14: u32 = 0x0000000D; // 14-bit data +pub const SSI_CR0_DSS_15: u32 = 0x0000000E; // 15-bit data +pub const SSI_CR0_DSS_16: u32 = 0x0000000F; // 16-bit data +pub const SSI_CR0_SCR_S: u32 = 8; +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR1 register. +// +//***************************************************************************** +pub const SSI_CR1_EOT: u32 = 0x00000010; // End of Transmission +pub const SSI_CR1_MS: u32 = 0x00000004; // SSI Master/Slave Select +pub const SSI_CR1_SSE: u32 = 0x00000002; // SSI Synchronous Serial Port + // Enable +pub const SSI_CR1_LBM: u32 = 0x00000001; // SSI Loopback Mode +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DR register. +// +//***************************************************************************** +pub const SSI_DR_DATA_M: u32 = 0x0000FFFF; // SSI Receive/Transmit Data +pub const SSI_DR_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_SR register. +// +//***************************************************************************** +pub const SSI_SR_BSY: u32 = 0x00000010; // SSI Busy Bit +pub const SSI_SR_RFF: u32 = 0x00000008; // SSI Receive FIFO Full +pub const SSI_SR_RNE: u32 = 0x00000004; // SSI Receive FIFO Not Empty +pub const SSI_SR_TNF: u32 = 0x00000002; // SSI Transmit FIFO Not Full +pub const SSI_SR_TFE: u32 = 0x00000001; // SSI Transmit FIFO Empty +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CPSR register. +// +//***************************************************************************** +pub const SSI_CPSR_CPSDVSR_M: u32 = 0x000000FF; // SSI Clock Prescale Divisor +pub const SSI_CPSR_CPSDVSR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_IM register. +// +//***************************************************************************** +pub const SSI_IM_TXIM: u32 = 0x00000008; // SSI Transmit FIFO Interrupt Mask +pub const SSI_IM_RXIM: u32 = 0x00000004; // SSI Receive FIFO Interrupt Mask +pub const SSI_IM_RTIM: u32 = 0x00000002; // SSI Receive Time-Out Interrupt + // Mask +pub const SSI_IM_RORIM: u32 = 0x00000001; // SSI Receive Overrun Interrupt + // Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_RIS register. +// +//***************************************************************************** +pub const SSI_RIS_TXRIS: u32 = 0x00000008; // SSI Transmit FIFO Raw Interrupt + // Status +pub const SSI_RIS_RXRIS: u32 = 0x00000004; // SSI Receive FIFO Raw Interrupt + // Status +pub const SSI_RIS_RTRIS: u32 = 0x00000002; // SSI Receive Time-Out Raw + // Interrupt Status +pub const SSI_RIS_RORRIS: u32 = 0x00000001; // SSI Receive Overrun Raw + // Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_MIS register. +// +//***************************************************************************** +pub const SSI_MIS_TXMIS: u32 = 0x00000008; // SSI Transmit FIFO Masked + // Interrupt Status +pub const SSI_MIS_RXMIS: u32 = 0x00000004; // SSI Receive FIFO Masked + // Interrupt Status +pub const SSI_MIS_RTMIS: u32 = 0x00000002; // SSI Receive Time-Out Masked + // Interrupt Status +pub const SSI_MIS_RORMIS: u32 = 0x00000001; // SSI Receive Overrun Masked + // Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_ICR register. +// +//***************************************************************************** +pub const SSI_ICR_RTIC: u32 = 0x00000002; // SSI Receive Time-Out Interrupt + // Clear +pub const SSI_ICR_RORIC: u32 = 0x00000001; // SSI Receive Overrun Interrupt + // Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DMACTL register. +// +//***************************************************************************** +pub const SSI_DMACTL_TXDMAE: u32 = 0x00000002; // Transmit DMA Enable +pub const SSI_DMACTL_RXDMAE: u32 = 0x00000001; // Receive DMA Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CC register. +// +//***************************************************************************** +pub const SSI_CC_CS_M: u32 = 0x0000000F; // SSI Baud Clock Source +pub const SSI_CC_CS_SYSPLL: u32 = 0x00000000; // System clock (based on clock + // source and divisor factor) +pub const SSI_CC_CS_PIOSC: u32 = 0x00000005; // PIOSC +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//***************************************************************************** +pub const UART_DR_OE: u32 = 0x00000800; // UART Overrun Error +pub const UART_DR_BE: u32 = 0x00000400; // UART Break Error +pub const UART_DR_PE: u32 = 0x00000200; // UART Parity Error +pub const UART_DR_FE: u32 = 0x00000100; // UART Framing Error +pub const UART_DR_DATA_M: u32 = 0x000000FF; // Data Transmitted or Received +pub const UART_DR_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//***************************************************************************** +pub const UART_RSR_OE: u32 = 0x00000008; // UART Overrun Error +pub const UART_RSR_BE: u32 = 0x00000004; // UART Break Error +pub const UART_RSR_PE: u32 = 0x00000002; // UART Parity Error +pub const UART_RSR_FE: u32 = 0x00000001; // UART Framing Error +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//***************************************************************************** +pub const UART_ECR_DATA_M: u32 = 0x000000FF; // Error Clear +pub const UART_ECR_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//***************************************************************************** +pub const UART_FR_TXFE: u32 = 0x00000080; // UART Transmit FIFO Empty +pub const UART_FR_RXFF: u32 = 0x00000040; // UART Receive FIFO Full +pub const UART_FR_TXFF: u32 = 0x00000020; // UART Transmit FIFO Full +pub const UART_FR_RXFE: u32 = 0x00000010; // UART Receive FIFO Empty +pub const UART_FR_BUSY: u32 = 0x00000008; // UART Busy +pub const UART_FR_CTS: u32 = 0x00000001; // Clear To Send +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//***************************************************************************** +pub const UART_ILPR_ILPDVSR_M: u32 = 0x000000FF; // IrDA Low-Power Divisor +pub const UART_ILPR_ILPDVSR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//***************************************************************************** +pub const UART_IBRD_DIVINT_M: u32 = 0x0000FFFF; // Integer Baud-Rate Divisor +pub const UART_IBRD_DIVINT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//***************************************************************************** +pub const UART_FBRD_DIVFRAC_M: u32 = 0x0000003F; // Fractional Baud-Rate Divisor +pub const UART_FBRD_DIVFRAC_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//***************************************************************************** +pub const UART_LCRH_SPS: u32 = 0x00000080; // UART Stick Parity Select +pub const UART_LCRH_WLEN_M: u32 = 0x00000060; // UART Word Length +pub const UART_LCRH_WLEN_5: u32 = 0x00000000; // 5 bits (default) +pub const UART_LCRH_WLEN_6: u32 = 0x00000020; // 6 bits +pub const UART_LCRH_WLEN_7: u32 = 0x00000040; // 7 bits +pub const UART_LCRH_WLEN_8: u32 = 0x00000060; // 8 bits +pub const UART_LCRH_FEN: u32 = 0x00000010; // UART Enable FIFOs +pub const UART_LCRH_STP2: u32 = 0x00000008; // UART Two Stop Bits Select +pub const UART_LCRH_EPS: u32 = 0x00000004; // UART Even Parity Select +pub const UART_LCRH_PEN: u32 = 0x00000002; // UART Parity Enable +pub const UART_LCRH_BRK: u32 = 0x00000001; // UART Send Break +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//***************************************************************************** +pub const UART_CTL_CTSEN: u32 = 0x00008000; // Enable Clear To Send +pub const UART_CTL_RTSEN: u32 = 0x00004000; // Enable Request to Send +pub const UART_CTL_RTS: u32 = 0x00000800; // Request to Send +pub const UART_CTL_RXE: u32 = 0x00000200; // UART Receive Enable +pub const UART_CTL_TXE: u32 = 0x00000100; // UART Transmit Enable +pub const UART_CTL_LBE: u32 = 0x00000080; // UART Loop Back Enable +pub const UART_CTL_HSE: u32 = 0x00000020; // High-Speed Enable +pub const UART_CTL_EOT: u32 = 0x00000010; // End of Transmission +pub const UART_CTL_SMART: u32 = 0x00000008; // ISO 7816 Smart Card Support +pub const UART_CTL_SIRLP: u32 = 0x00000004; // UART SIR Low-Power Mode +pub const UART_CTL_SIREN: u32 = 0x00000002; // UART SIR Enable +pub const UART_CTL_UARTEN: u32 = 0x00000001; // UART Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//***************************************************************************** +pub const UART_IFLS_RX_M: u32 = 0x00000038; // UART Receive Interrupt FIFO + // Level Select +pub const UART_IFLS_RX1_8: u32 = 0x00000000; // RX FIFO >= 1/8 full +pub const UART_IFLS_RX2_8: u32 = 0x00000008; // RX FIFO >= 1/4 full +pub const UART_IFLS_RX4_8: u32 = 0x00000010; // RX FIFO >= 1/2 full (default) +pub const UART_IFLS_RX6_8: u32 = 0x00000018; // RX FIFO >= 3/4 full +pub const UART_IFLS_RX7_8: u32 = 0x00000020; // RX FIFO >= 7/8 full +pub const UART_IFLS_TX_M: u32 = 0x00000007; // UART Transmit Interrupt FIFO + // Level Select +pub const UART_IFLS_TX1_8: u32 = 0x00000000; // TX FIFO <= 1/8 full +pub const UART_IFLS_TX2_8: u32 = 0x00000001; // TX FIFO <= 1/4 full +pub const UART_IFLS_TX4_8: u32 = 0x00000002; // TX FIFO <= 1/2 full (default) +pub const UART_IFLS_TX6_8: u32 = 0x00000003; // TX FIFO <= 3/4 full +pub const UART_IFLS_TX7_8: u32 = 0x00000004; // TX FIFO <= 7/8 full +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//***************************************************************************** +pub const UART_IM_9BITIM: u32 = 0x00001000; // 9-Bit Mode Interrupt Mask +pub const UART_IM_OEIM: u32 = 0x00000400; // UART Overrun Error Interrupt + // Mask +pub const UART_IM_BEIM: u32 = 0x00000200; // UART Break Error Interrupt Mask +pub const UART_IM_PEIM: u32 = 0x00000100; // UART Parity Error Interrupt Mask +pub const UART_IM_FEIM: u32 = 0x00000080; // UART Framing Error Interrupt + // Mask +pub const UART_IM_RTIM: u32 = 0x00000040; // UART Receive Time-Out Interrupt + // Mask +pub const UART_IM_TXIM: u32 = 0x00000020; // UART Transmit Interrupt Mask +pub const UART_IM_RXIM: u32 = 0x00000010; // UART Receive Interrupt Mask +pub const UART_IM_CTSMIM: u32 = 0x00000002; // UART Clear to Send Modem + // Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//***************************************************************************** +pub const UART_RIS_9BITRIS: u32 = 0x00001000; // 9-Bit Mode Raw Interrupt Status +pub const UART_RIS_OERIS: u32 = 0x00000400; // UART Overrun Error Raw Interrupt + // Status +pub const UART_RIS_BERIS: u32 = 0x00000200; // UART Break Error Raw Interrupt + // Status +pub const UART_RIS_PERIS: u32 = 0x00000100; // UART Parity Error Raw Interrupt + // Status +pub const UART_RIS_FERIS: u32 = 0x00000080; // UART Framing Error Raw Interrupt + // Status +pub const UART_RIS_RTRIS: u32 = 0x00000040; // UART Receive Time-Out Raw + // Interrupt Status +pub const UART_RIS_TXRIS: u32 = 0x00000020; // UART Transmit Raw Interrupt + // Status +pub const UART_RIS_RXRIS: u32 = 0x00000010; // UART Receive Raw Interrupt + // Status +pub const UART_RIS_CTSRIS: u32 = 0x00000002; // UART Clear to Send Modem Raw + // Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//***************************************************************************** +pub const UART_MIS_9BITMIS: u32 = 0x00001000; // 9-Bit Mode Masked Interrupt + // Status +pub const UART_MIS_OEMIS: u32 = 0x00000400; // UART Overrun Error Masked + // Interrupt Status +pub const UART_MIS_BEMIS: u32 = 0x00000200; // UART Break Error Masked + // Interrupt Status +pub const UART_MIS_PEMIS: u32 = 0x00000100; // UART Parity Error Masked + // Interrupt Status +pub const UART_MIS_FEMIS: u32 = 0x00000080; // UART Framing Error Masked + // Interrupt Status +pub const UART_MIS_RTMIS: u32 = 0x00000040; // UART Receive Time-Out Masked + // Interrupt Status +pub const UART_MIS_TXMIS: u32 = 0x00000020; // UART Transmit Masked Interrupt + // Status +pub const UART_MIS_RXMIS: u32 = 0x00000010; // UART Receive Masked Interrupt + // Status +pub const UART_MIS_CTSMIS: u32 = 0x00000002; // UART Clear to Send Modem Masked + // Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//***************************************************************************** +pub const UART_ICR_9BITIC: u32 = 0x00001000; // 9-Bit Mode Interrupt Clear +pub const UART_ICR_OEIC: u32 = 0x00000400; // Overrun Error Interrupt Clear +pub const UART_ICR_BEIC: u32 = 0x00000200; // Break Error Interrupt Clear +pub const UART_ICR_PEIC: u32 = 0x00000100; // Parity Error Interrupt Clear +pub const UART_ICR_FEIC: u32 = 0x00000080; // Framing Error Interrupt Clear +pub const UART_ICR_RTIC: u32 = 0x00000040; // Receive Time-Out Interrupt Clear +pub const UART_ICR_TXIC: u32 = 0x00000020; // Transmit Interrupt Clear +pub const UART_ICR_RXIC: u32 = 0x00000010; // Receive Interrupt Clear +pub const UART_ICR_CTSMIC: u32 = 0x00000002; // UART Clear to Send Modem + // Interrupt Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//***************************************************************************** +pub const UART_DMACTL_DMAERR: u32 = 0x00000004; // DMA on Error +pub const UART_DMACTL_TXDMAE: u32 = 0x00000002; // Transmit DMA Enable +pub const UART_DMACTL_RXDMAE: u32 = 0x00000001; // Receive DMA Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITADDR +// register. +// +//***************************************************************************** +pub const UART_9BITADDR_9BITEN: u32 = 0x00008000; // Enable 9-Bit Mode +pub const UART_9BITADDR_ADDR_M: u32 = 0x000000FF; // Self Address for 9-Bit Mode +pub const UART_9BITADDR_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITAMASK +// register. +// +//***************************************************************************** +pub const UART_9BITAMASK_MASK_M: u32 = 0x000000FF; // Self Address Mask for 9-Bit Mode +pub const UART_9BITAMASK_MASK_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//***************************************************************************** +pub const UART_PP_NB: u32 = 0x00000002; // 9-Bit Support +pub const UART_PP_SC: u32 = 0x00000001; // Smart Card Support +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//***************************************************************************** +pub const UART_CC_CS_M: u32 = 0x0000000F; // UART Baud Clock Source +pub const UART_CC_CS_SYSCLK: u32 = 0x00000000; // System clock (based on clock + // source and divisor factor) +pub const UART_CC_CS_PIOSC: u32 = 0x00000005; // PIOSC +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//***************************************************************************** +pub const I2C_MSA_SA_M: u32 = 0x000000FE; // I2C Slave Address +pub const I2C_MSA_RS: u32 = 0x00000001; // Receive not send +pub const I2C_MSA_SA_S: u32 = 1; +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//***************************************************************************** +pub const I2C_MCS_CLKTO: u32 = 0x00000080; // Clock Timeout Error +pub const I2C_MCS_BUSBSY: u32 = 0x00000040; // Bus Busy +pub const I2C_MCS_IDLE: u32 = 0x00000020; // I2C Idle +pub const I2C_MCS_ARBLST: u32 = 0x00000010; // Arbitration Lost +pub const I2C_MCS_HS: u32 = 0x00000010; // High-Speed Enable +pub const I2C_MCS_ACK: u32 = 0x00000008; // Data Acknowledge Enable +pub const I2C_MCS_DATACK: u32 = 0x00000008; // Acknowledge Data +pub const I2C_MCS_ADRACK: u32 = 0x00000004; // Acknowledge Address +pub const I2C_MCS_STOP: u32 = 0x00000004; // Generate STOP +pub const I2C_MCS_ERROR: u32 = 0x00000002; // Error +pub const I2C_MCS_START: u32 = 0x00000002; // Generate START +pub const I2C_MCS_RUN: u32 = 0x00000001; // I2C Master Enable +pub const I2C_MCS_BUSY: u32 = 0x00000001; // I2C Busy +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//***************************************************************************** +pub const I2C_MDR_DATA_M: u32 = 0x000000FF; // This byte contains the data + // transferred during a transaction +pub const I2C_MDR_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//***************************************************************************** +pub const I2C_MTPR_HS: u32 = 0x00000080; // High-Speed Enable +pub const I2C_MTPR_TPR_M: u32 = 0x0000007F; // Timer Period +pub const I2C_MTPR_TPR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//***************************************************************************** +pub const I2C_MIMR_CLKIM: u32 = 0x00000002; // Clock Timeout Interrupt Mask +pub const I2C_MIMR_IM: u32 = 0x00000001; // Master Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//***************************************************************************** +pub const I2C_MRIS_CLKRIS: u32 = 0x00000002; // Clock Timeout Raw Interrupt + // Status +pub const I2C_MRIS_RIS: u32 = 0x00000001; // Master Raw Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//***************************************************************************** +pub const I2C_MMIS_CLKMIS: u32 = 0x00000002; // Clock Timeout Masked Interrupt + // Status +pub const I2C_MMIS_MIS: u32 = 0x00000001; // Masked Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//***************************************************************************** +pub const I2C_MICR_CLKIC: u32 = 0x00000002; // Clock Timeout Interrupt Clear +pub const I2C_MICR_IC: u32 = 0x00000001; // Master Interrupt Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//***************************************************************************** +pub const I2C_MCR_GFE: u32 = 0x00000040; // I2C Glitch Filter Enable +pub const I2C_MCR_SFE: u32 = 0x00000020; // I2C Slave Function Enable +pub const I2C_MCR_MFE: u32 = 0x00000010; // I2C Master Function Enable +pub const I2C_MCR_LPBK: u32 = 0x00000001; // I2C Loopback +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//***************************************************************************** +pub const I2C_MCLKOCNT_CNTL_M: u32 = 0x000000FF; // I2C Master Count +pub const I2C_MCLKOCNT_CNTL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//***************************************************************************** +pub const I2C_MBMON_SDA: u32 = 0x00000002; // I2C SDA Status +pub const I2C_MBMON_SCL: u32 = 0x00000001; // I2C SCL Status +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR2 register. +// +//***************************************************************************** +pub const I2C_MCR2_GFPW_M: u32 = 0x00000070; // I2C Glitch Filter Pulse Width +pub const I2C_MCR2_GFPW_BYPASS: u32 = 0x00000000; // Bypass +pub const I2C_MCR2_GFPW_1: u32 = 0x00000010; // 1 clock +pub const I2C_MCR2_GFPW_2: u32 = 0x00000020; // 2 clocks +pub const I2C_MCR2_GFPW_3: u32 = 0x00000030; // 3 clocks +pub const I2C_MCR2_GFPW_4: u32 = 0x00000040; // 4 clocks +pub const I2C_MCR2_GFPW_8: u32 = 0x00000050; // 8 clocks +pub const I2C_MCR2_GFPW_16: u32 = 0x00000060; // 16 clocks +pub const I2C_MCR2_GFPW_31: u32 = 0x00000070; // 31 clocks +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//***************************************************************************** +pub const I2C_SOAR_OAR_M: u32 = 0x0000007F; // I2C Slave Own Address +pub const I2C_SOAR_OAR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//***************************************************************************** +pub const I2C_SCSR_OAR2SEL: u32 = 0x00000008; // OAR2 Address Matched +pub const I2C_SCSR_FBR: u32 = 0x00000004; // First Byte Received +pub const I2C_SCSR_TREQ: u32 = 0x00000002; // Transmit Request +pub const I2C_SCSR_DA: u32 = 0x00000001; // Device Active +pub const I2C_SCSR_RREQ: u32 = 0x00000001; // Receive Request +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//***************************************************************************** +pub const I2C_SDR_DATA_M: u32 = 0x000000FF; // Data for Transfer +pub const I2C_SDR_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//***************************************************************************** +pub const I2C_SIMR_STOPIM: u32 = 0x00000004; // Stop Condition Interrupt Mask +pub const I2C_SIMR_STARTIM: u32 = 0x00000002; // Start Condition Interrupt Mask +pub const I2C_SIMR_DATAIM: u32 = 0x00000001; // Data Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//***************************************************************************** +pub const I2C_SRIS_STOPRIS: u32 = 0x00000004; // Stop Condition Raw Interrupt + // Status +pub const I2C_SRIS_STARTRIS: u32 = 0x00000002; // Start Condition Raw Interrupt + // Status +pub const I2C_SRIS_DATARIS: u32 = 0x00000001; // Data Raw Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//***************************************************************************** +pub const I2C_SMIS_STOPMIS: u32 = 0x00000004; // Stop Condition Masked Interrupt + // Status +pub const I2C_SMIS_STARTMIS: u32 = 0x00000002; // Start Condition Masked Interrupt + // Status +pub const I2C_SMIS_DATAMIS: u32 = 0x00000001; // Data Masked Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//***************************************************************************** +pub const I2C_SICR_STOPIC: u32 = 0x00000004; // Stop Condition Interrupt Clear +pub const I2C_SICR_STARTIC: u32 = 0x00000002; // Start Condition Interrupt Clear +pub const I2C_SICR_DATAIC: u32 = 0x00000001; // Data Interrupt Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//***************************************************************************** +pub const I2C_SOAR2_OAR2EN: u32 = 0x00000080; // I2C Slave Own Address 2 Enable +pub const I2C_SOAR2_OAR2_M: u32 = 0x0000007F; // I2C Slave Own Address 2 +pub const I2C_SOAR2_OAR2_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//***************************************************************************** +pub const I2C_SACKCTL_ACKOVAL: u32 = 0x00000002; // I2C Slave ACK Override Value +pub const I2C_SACKCTL_ACKOEN: u32 = 0x00000001; // I2C Slave ACK Override Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//***************************************************************************** +pub const I2C_PP_HS: u32 = 0x00000001; // High-Speed Capable +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//***************************************************************************** +pub const I2C_PC_HS: u32 = 0x00000001; // High-Speed Capable +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_CTL register. +// +//***************************************************************************** +pub const PWM_CTL_GLOBALSYNC3: u32 = 0x00000008; // Update PWM Generator 3 +pub const PWM_CTL_GLOBALSYNC2: u32 = 0x00000004; // Update PWM Generator 2 +pub const PWM_CTL_GLOBALSYNC1: u32 = 0x00000002; // Update PWM Generator 1 +pub const PWM_CTL_GLOBALSYNC0: u32 = 0x00000001; // Update PWM Generator 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_SYNC register. +// +//***************************************************************************** +pub const PWM_SYNC_SYNC3: u32 = 0x00000008; // Reset Generator 3 Counter +pub const PWM_SYNC_SYNC2: u32 = 0x00000004; // Reset Generator 2 Counter +pub const PWM_SYNC_SYNC1: u32 = 0x00000002; // Reset Generator 1 Counter +pub const PWM_SYNC_SYNC0: u32 = 0x00000001; // Reset Generator 0 Counter +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENABLE register. +// +//***************************************************************************** +pub const PWM_ENABLE_PWM7EN: u32 = 0x00000080; // MnPWM7 Output Enable +pub const PWM_ENABLE_PWM6EN: u32 = 0x00000040; // MnPWM6 Output Enable +pub const PWM_ENABLE_PWM5EN: u32 = 0x00000020; // MnPWM5 Output Enable +pub const PWM_ENABLE_PWM4EN: u32 = 0x00000010; // MnPWM4 Output Enable +pub const PWM_ENABLE_PWM3EN: u32 = 0x00000008; // MnPWM3 Output Enable +pub const PWM_ENABLE_PWM2EN: u32 = 0x00000004; // MnPWM2 Output Enable +pub const PWM_ENABLE_PWM1EN: u32 = 0x00000002; // MnPWM1 Output Enable +pub const PWM_ENABLE_PWM0EN: u32 = 0x00000001; // MnPWM0 Output Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INVERT register. +// +//***************************************************************************** +pub const PWM_INVERT_PWM7INV: u32 = 0x00000080; // Invert MnPWM7 Signal +pub const PWM_INVERT_PWM6INV: u32 = 0x00000040; // Invert MnPWM6 Signal +pub const PWM_INVERT_PWM5INV: u32 = 0x00000020; // Invert MnPWM5 Signal +pub const PWM_INVERT_PWM4INV: u32 = 0x00000010; // Invert MnPWM4 Signal +pub const PWM_INVERT_PWM3INV: u32 = 0x00000008; // Invert MnPWM3 Signal +pub const PWM_INVERT_PWM2INV: u32 = 0x00000004; // Invert MnPWM2 Signal +pub const PWM_INVERT_PWM1INV: u32 = 0x00000002; // Invert MnPWM1 Signal +pub const PWM_INVERT_PWM0INV: u32 = 0x00000001; // Invert MnPWM0 Signal +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULT register. +// +//***************************************************************************** +pub const PWM_FAULT_FAULT7: u32 = 0x00000080; // MnPWM7 Fault +pub const PWM_FAULT_FAULT6: u32 = 0x00000040; // MnPWM6 Fault +pub const PWM_FAULT_FAULT5: u32 = 0x00000020; // MnPWM5 Fault +pub const PWM_FAULT_FAULT4: u32 = 0x00000010; // MnPWM4 Fault +//pub const PWM_FAULT_FAULT3: u32 = 0x00000008; // MnPWM3 Fault +//pub const PWM_FAULT_FAULT2: u32 = 0x00000004; // MnPWM2 Fault +//pub const PWM_FAULT_FAULT1: u32 = 0x00000002; // MnPWM1 Fault +//pub const PWM_FAULT_FAULT0: u32 = 0x00000001; // MnPWM0 Fault +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INTEN register. +// +//***************************************************************************** +pub const PWM_INTEN_INTFAULT1: u32 = 0x00020000; // Interrupt Fault 1 +pub const PWM_INTEN_INTFAULT0: u32 = 0x00010000; // Interrupt Fault 0 +pub const PWM_INTEN_INTPWM3: u32 = 0x00000008; // PWM3 Interrupt Enable +pub const PWM_INTEN_INTPWM2: u32 = 0x00000004; // PWM2 Interrupt Enable +pub const PWM_INTEN_INTPWM1: u32 = 0x00000002; // PWM1 Interrupt Enable +pub const PWM_INTEN_INTPWM0: u32 = 0x00000001; // PWM0 Interrupt Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_RIS register. +// +//***************************************************************************** +pub const PWM_RIS_INTFAULT1: u32 = 0x00020000; // Interrupt Fault PWM 1 +pub const PWM_RIS_INTFAULT0: u32 = 0x00010000; // Interrupt Fault PWM 0 +pub const PWM_RIS_INTPWM3: u32 = 0x00000008; // PWM3 Interrupt Asserted +pub const PWM_RIS_INTPWM2: u32 = 0x00000004; // PWM2 Interrupt Asserted +pub const PWM_RIS_INTPWM1: u32 = 0x00000002; // PWM1 Interrupt Asserted +pub const PWM_RIS_INTPWM0: u32 = 0x00000001; // PWM0 Interrupt Asserted +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ISC register. +// +//***************************************************************************** +pub const PWM_ISC_INTFAULT1: u32 = 0x00020000; // FAULT1 Interrupt Asserted +pub const PWM_ISC_INTFAULT0: u32 = 0x00010000; // FAULT0 Interrupt Asserted +pub const PWM_ISC_INTPWM3: u32 = 0x00000008; // PWM3 Interrupt Status +pub const PWM_ISC_INTPWM2: u32 = 0x00000004; // PWM2 Interrupt Status +pub const PWM_ISC_INTPWM1: u32 = 0x00000002; // PWM1 Interrupt Status +pub const PWM_ISC_INTPWM0: u32 = 0x00000001; // PWM0 Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_STATUS register. +// +//***************************************************************************** +pub const PWM_STATUS_FAULT1: u32 = 0x00000002; // Generator 1 Fault Status +pub const PWM_STATUS_FAULT0: u32 = 0x00000001; // Generator 0 Fault Status +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULTVAL register. +// +//***************************************************************************** +pub const PWM_FAULTVAL_PWM7: u32 = 0x00000080; // MnPWM7 Fault Value +pub const PWM_FAULTVAL_PWM6: u32 = 0x00000040; // MnPWM6 Fault Value +pub const PWM_FAULTVAL_PWM5: u32 = 0x00000020; // MnPWM5 Fault Value +pub const PWM_FAULTVAL_PWM4: u32 = 0x00000010; // MnPWM4 Fault Value +pub const PWM_FAULTVAL_PWM3: u32 = 0x00000008; // MnPWM3 Fault Value +pub const PWM_FAULTVAL_PWM2: u32 = 0x00000004; // MnPWM2 Fault Value +pub const PWM_FAULTVAL_PWM1: u32 = 0x00000002; // MnPWM1 Fault Value +pub const PWM_FAULTVAL_PWM0: u32 = 0x00000001; // MnPWM0 Fault Value +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENUPD register. +// +//***************************************************************************** +pub const PWM_ENUPD_ENUPD7_M: u32 = 0x0000C000; // MnPWM7 Enable Update Mode +pub const PWM_ENUPD_ENUPD7_IMM: u32 = 0x00000000; // Immediate +pub const PWM_ENUPD_ENUPD7_LSYNC: u32 = 0x00008000; // Locally Synchronized +pub const PWM_ENUPD_ENUPD7_GSYNC: u32 = 0x0000C000; // Globally Synchronized +pub const PWM_ENUPD_ENUPD6_M: u32 = 0x00003000; // MnPWM6 Enable Update Mode +pub const PWM_ENUPD_ENUPD6_IMM: u32 = 0x00000000; // Immediate +pub const PWM_ENUPD_ENUPD6_LSYNC: u32 = 0x00002000; // Locally Synchronized +pub const PWM_ENUPD_ENUPD6_GSYNC: u32 = 0x00003000; // Globally Synchronized +pub const PWM_ENUPD_ENUPD5_M: u32 = 0x00000C00; // MnPWM5 Enable Update Mode +pub const PWM_ENUPD_ENUPD5_IMM: u32 = 0x00000000; // Immediate +pub const PWM_ENUPD_ENUPD5_LSYNC: u32 = 0x00000800; // Locally Synchronized +pub const PWM_ENUPD_ENUPD5_GSYNC: u32 = 0x00000C00; // Globally Synchronized +pub const PWM_ENUPD_ENUPD4_M: u32 = 0x00000300; // MnPWM4 Enable Update Mode +pub const PWM_ENUPD_ENUPD4_IMM: u32 = 0x00000000; // Immediate +pub const PWM_ENUPD_ENUPD4_LSYNC: u32 = 0x00000200; // Locally Synchronized +pub const PWM_ENUPD_ENUPD4_GSYNC: u32 = 0x00000300; // Globally Synchronized +pub const PWM_ENUPD_ENUPD3_M: u32 = 0x000000C0; // MnPWM3 Enable Update Mode +pub const PWM_ENUPD_ENUPD3_IMM: u32 = 0x00000000; // Immediate +pub const PWM_ENUPD_ENUPD3_LSYNC: u32 = 0x00000080; // Locally Synchronized +pub const PWM_ENUPD_ENUPD3_GSYNC: u32 = 0x000000C0; // Globally Synchronized +pub const PWM_ENUPD_ENUPD2_M: u32 = 0x00000030; // MnPWM2 Enable Update Mode +pub const PWM_ENUPD_ENUPD2_IMM: u32 = 0x00000000; // Immediate +pub const PWM_ENUPD_ENUPD2_LSYNC: u32 = 0x00000020; // Locally Synchronized +pub const PWM_ENUPD_ENUPD2_GSYNC: u32 = 0x00000030; // Globally Synchronized +pub const PWM_ENUPD_ENUPD1_M: u32 = 0x0000000C; // MnPWM1 Enable Update Mode +pub const PWM_ENUPD_ENUPD1_IMM: u32 = 0x00000000; // Immediate +pub const PWM_ENUPD_ENUPD1_LSYNC: u32 = 0x00000008; // Locally Synchronized +pub const PWM_ENUPD_ENUPD1_GSYNC: u32 = 0x0000000C; // Globally Synchronized +pub const PWM_ENUPD_ENUPD0_M: u32 = 0x00000003; // MnPWM0 Enable Update Mode +pub const PWM_ENUPD_ENUPD0_IMM: u32 = 0x00000000; // Immediate +pub const PWM_ENUPD_ENUPD0_LSYNC: u32 = 0x00000002; // Locally Synchronized +pub const PWM_ENUPD_ENUPD0_GSYNC: u32 = 0x00000003; // Globally Synchronized +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CTL register. +// +//***************************************************************************** +pub const PWM_0_CTL_LATCH: u32 = 0x00040000; // Latch Fault Input +pub const PWM_0_CTL_MINFLTPER: u32 = 0x00020000; // Minimum Fault Period +pub const PWM_0_CTL_FLTSRC: u32 = 0x00010000; // Fault Condition Source +pub const PWM_0_CTL_DBFALLUPD_M: u32 = 0x0000C000; // PWMnDBFALL Update Mode +pub const PWM_0_CTL_DBFALLUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_0_CTL_DBFALLUPD_LS: u32 = 0x00008000; // Locally Synchronized +pub const PWM_0_CTL_DBFALLUPD_GS: u32 = 0x0000C000; // Globally Synchronized +pub const PWM_0_CTL_DBRISEUPD_M: u32 = 0x00003000; // PWMnDBRISE Update Mode +pub const PWM_0_CTL_DBRISEUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_0_CTL_DBRISEUPD_LS: u32 = 0x00002000; // Locally Synchronized +pub const PWM_0_CTL_DBRISEUPD_GS: u32 = 0x00003000; // Globally Synchronized +pub const PWM_0_CTL_DBCTLUPD_M: u32 = 0x00000C00; // PWMnDBCTL Update Mode +pub const PWM_0_CTL_DBCTLUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_0_CTL_DBCTLUPD_LS: u32 = 0x00000800; // Locally Synchronized +pub const PWM_0_CTL_DBCTLUPD_GS: u32 = 0x00000C00; // Globally Synchronized +pub const PWM_0_CTL_GENBUPD_M: u32 = 0x00000300; // PWMnGENB Update Mode +pub const PWM_0_CTL_GENBUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_0_CTL_GENBUPD_LS: u32 = 0x00000200; // Locally Synchronized +pub const PWM_0_CTL_GENBUPD_GS: u32 = 0x00000300; // Globally Synchronized +pub const PWM_0_CTL_GENAUPD_M: u32 = 0x000000C0; // PWMnGENA Update Mode +pub const PWM_0_CTL_GENAUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_0_CTL_GENAUPD_LS: u32 = 0x00000080; // Locally Synchronized +pub const PWM_0_CTL_GENAUPD_GS: u32 = 0x000000C0; // Globally Synchronized +pub const PWM_0_CTL_CMPBUPD: u32 = 0x00000020; // Comparator B Update Mode +pub const PWM_0_CTL_CMPAUPD: u32 = 0x00000010; // Comparator A Update Mode +pub const PWM_0_CTL_LOADUPD: u32 = 0x00000008; // Load Register Update Mode +pub const PWM_0_CTL_DEBUG: u32 = 0x00000004; // Debug Mode +pub const PWM_0_CTL_MODE: u32 = 0x00000002; // Counter Mode +pub const PWM_0_CTL_ENABLE: u32 = 0x00000001; // PWM Block Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_INTEN register. +// +//***************************************************************************** +pub const PWM_0_INTEN_TRCMPBD: u32 = 0x00002000; // Trigger for Counter=PWMnCMPB + // Down +pub const PWM_0_INTEN_TRCMPBU: u32 = 0x00001000; // Trigger for Counter=PWMnCMPB Up +pub const PWM_0_INTEN_TRCMPAD: u32 = 0x00000800; // Trigger for Counter=PWMnCMPA + // Down +pub const PWM_0_INTEN_TRCMPAU: u32 = 0x00000400; // Trigger for Counter=PWMnCMPA Up +pub const PWM_0_INTEN_TRCNTLOAD: u32 = 0x00000200; // Trigger for Counter=PWMnLOAD +pub const PWM_0_INTEN_TRCNTZERO: u32 = 0x00000100; // Trigger for Counter=0 +pub const PWM_0_INTEN_INTCMPBD: u32 = 0x00000020; // Interrupt for Counter=PWMnCMPB + // Down +pub const PWM_0_INTEN_INTCMPBU: u32 = 0x00000010; // Interrupt for Counter=PWMnCMPB + // Up +pub const PWM_0_INTEN_INTCMPAD: u32 = 0x00000008; // Interrupt for Counter=PWMnCMPA + // Down +pub const PWM_0_INTEN_INTCMPAU: u32 = 0x00000004; // Interrupt for Counter=PWMnCMPA + // Up +pub const PWM_0_INTEN_INTCNTLOAD: u32 = 0x00000002; // Interrupt for Counter=PWMnLOAD +pub const PWM_0_INTEN_INTCNTZERO: u32 = 0x00000001; // Interrupt for Counter=0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_RIS register. +// +//***************************************************************************** +pub const PWM_0_RIS_INTCMPBD: u32 = 0x00000020; // Comparator B Down Interrupt + // Status +pub const PWM_0_RIS_INTCMPBU: u32 = 0x00000010; // Comparator B Up Interrupt Status +pub const PWM_0_RIS_INTCMPAD: u32 = 0x00000008; // Comparator A Down Interrupt + // Status +pub const PWM_0_RIS_INTCMPAU: u32 = 0x00000004; // Comparator A Up Interrupt Status +pub const PWM_0_RIS_INTCNTLOAD: u32 = 0x00000002; // Counter=Load Interrupt Status +pub const PWM_0_RIS_INTCNTZERO: u32 = 0x00000001; // Counter=0 Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_ISC register. +// +//***************************************************************************** +pub const PWM_0_ISC_INTCMPBD: u32 = 0x00000020; // Comparator B Down Interrupt +pub const PWM_0_ISC_INTCMPBU: u32 = 0x00000010; // Comparator B Up Interrupt +pub const PWM_0_ISC_INTCMPAD: u32 = 0x00000008; // Comparator A Down Interrupt +pub const PWM_0_ISC_INTCMPAU: u32 = 0x00000004; // Comparator A Up Interrupt +pub const PWM_0_ISC_INTCNTLOAD: u32 = 0x00000002; // Counter=Load Interrupt +pub const PWM_0_ISC_INTCNTZERO: u32 = 0x00000001; // Counter=0 Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_LOAD register. +// +//***************************************************************************** +pub const PWM_0_LOAD_M: u32 = 0x0000FFFF; // Counter Load Value +pub const PWM_0_LOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_COUNT register. +// +//***************************************************************************** +pub const PWM_0_COUNT_M: u32 = 0x0000FFFF; // Counter Value +pub const PWM_0_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPA register. +// +//***************************************************************************** +pub const PWM_0_CMPA_M: u32 = 0x0000FFFF; // Comparator A Value +pub const PWM_0_CMPA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPB register. +// +//***************************************************************************** +pub const PWM_0_CMPB_M: u32 = 0x0000FFFF; // Comparator B Value +pub const PWM_0_CMPB_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENA register. +// +//***************************************************************************** +pub const PWM_0_GENA_ACTCMPBD_M: u32 = 0x00000C00; // Action for Comparator B Down +pub const PWM_0_GENA_ACTCMPBD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENA_ACTCMPBD_INV: u32 = 0x00000400; // Invert pwmA +pub const PWM_0_GENA_ACTCMPBD_ZERO: u32 = 0x00000800; // Drive pwmA Low +pub const PWM_0_GENA_ACTCMPBD_ONE: u32 = 0x00000C00; // Drive pwmA High +pub const PWM_0_GENA_ACTCMPBU_M: u32 = 0x00000300; // Action for Comparator B Up +pub const PWM_0_GENA_ACTCMPBU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENA_ACTCMPBU_INV: u32 = 0x00000100; // Invert pwmA +pub const PWM_0_GENA_ACTCMPBU_ZERO: u32 = 0x00000200; // Drive pwmA Low +pub const PWM_0_GENA_ACTCMPBU_ONE: u32 = 0x00000300; // Drive pwmA High +pub const PWM_0_GENA_ACTCMPAD_M: u32 = 0x000000C0; // Action for Comparator A Down +pub const PWM_0_GENA_ACTCMPAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENA_ACTCMPAD_INV: u32 = 0x00000040; // Invert pwmA +pub const PWM_0_GENA_ACTCMPAD_ZERO: u32 = 0x00000080; // Drive pwmA Low +pub const PWM_0_GENA_ACTCMPAD_ONE: u32 = 0x000000C0; // Drive pwmA High +pub const PWM_0_GENA_ACTCMPAU_M: u32 = 0x00000030; // Action for Comparator A Up +pub const PWM_0_GENA_ACTCMPAU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENA_ACTCMPAU_INV: u32 = 0x00000010; // Invert pwmA +pub const PWM_0_GENA_ACTCMPAU_ZERO: u32 = 0x00000020; // Drive pwmA Low +pub const PWM_0_GENA_ACTCMPAU_ONE: u32 = 0x00000030; // Drive pwmA High +pub const PWM_0_GENA_ACTLOAD_M: u32 = 0x0000000C; // Action for Counter=LOAD +pub const PWM_0_GENA_ACTLOAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENA_ACTLOAD_INV: u32 = 0x00000004; // Invert pwmA +pub const PWM_0_GENA_ACTLOAD_ZERO: u32 = 0x00000008; // Drive pwmA Low +pub const PWM_0_GENA_ACTLOAD_ONE: u32 = 0x0000000C; // Drive pwmA High +pub const PWM_0_GENA_ACTZERO_M: u32 = 0x00000003; // Action for Counter=0 +pub const PWM_0_GENA_ACTZERO_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENA_ACTZERO_INV: u32 = 0x00000001; // Invert pwmA +pub const PWM_0_GENA_ACTZERO_ZERO: u32 = 0x00000002; // Drive pwmA Low +pub const PWM_0_GENA_ACTZERO_ONE: u32 = 0x00000003; // Drive pwmA High +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENB register. +// +//***************************************************************************** +pub const PWM_0_GENB_ACTCMPBD_M: u32 = 0x00000C00; // Action for Comparator B Down +pub const PWM_0_GENB_ACTCMPBD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENB_ACTCMPBD_INV: u32 = 0x00000400; // Invert pwmB +pub const PWM_0_GENB_ACTCMPBD_ZERO: u32 = 0x00000800; // Drive pwmB Low +pub const PWM_0_GENB_ACTCMPBD_ONE: u32 = 0x00000C00; // Drive pwmB High +pub const PWM_0_GENB_ACTCMPBU_M: u32 = 0x00000300; // Action for Comparator B Up +pub const PWM_0_GENB_ACTCMPBU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENB_ACTCMPBU_INV: u32 = 0x00000100; // Invert pwmB +pub const PWM_0_GENB_ACTCMPBU_ZERO: u32 = 0x00000200; // Drive pwmB Low +pub const PWM_0_GENB_ACTCMPBU_ONE: u32 = 0x00000300; // Drive pwmB High +pub const PWM_0_GENB_ACTCMPAD_M: u32 = 0x000000C0; // Action for Comparator A Down +pub const PWM_0_GENB_ACTCMPAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENB_ACTCMPAD_INV: u32 = 0x00000040; // Invert pwmB +pub const PWM_0_GENB_ACTCMPAD_ZERO: u32 = 0x00000080; // Drive pwmB Low +pub const PWM_0_GENB_ACTCMPAD_ONE: u32 = 0x000000C0; // Drive pwmB High +pub const PWM_0_GENB_ACTCMPAU_M: u32 = 0x00000030; // Action for Comparator A Up +pub const PWM_0_GENB_ACTCMPAU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENB_ACTCMPAU_INV: u32 = 0x00000010; // Invert pwmB +pub const PWM_0_GENB_ACTCMPAU_ZERO: u32 = 0x00000020; // Drive pwmB Low +pub const PWM_0_GENB_ACTCMPAU_ONE: u32 = 0x00000030; // Drive pwmB High +pub const PWM_0_GENB_ACTLOAD_M: u32 = 0x0000000C; // Action for Counter=LOAD +pub const PWM_0_GENB_ACTLOAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENB_ACTLOAD_INV: u32 = 0x00000004; // Invert pwmB +pub const PWM_0_GENB_ACTLOAD_ZERO: u32 = 0x00000008; // Drive pwmB Low +pub const PWM_0_GENB_ACTLOAD_ONE: u32 = 0x0000000C; // Drive pwmB High +pub const PWM_0_GENB_ACTZERO_M: u32 = 0x00000003; // Action for Counter=0 +pub const PWM_0_GENB_ACTZERO_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_0_GENB_ACTZERO_INV: u32 = 0x00000001; // Invert pwmB +pub const PWM_0_GENB_ACTZERO_ZERO: u32 = 0x00000002; // Drive pwmB Low +pub const PWM_0_GENB_ACTZERO_ONE: u32 = 0x00000003; // Drive pwmB High +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBCTL register. +// +//***************************************************************************** +pub const PWM_0_DBCTL_ENABLE: u32 = 0x00000001; // Dead-Band Generator Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBRISE register. +// +//***************************************************************************** +pub const PWM_0_DBRISE_DELAY_M: u32 = 0x00000FFF; // Dead-Band Rise Delay +pub const PWM_0_DBRISE_DELAY_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBFALL register. +// +//***************************************************************************** +pub const PWM_0_DBFALL_DELAY_M: u32 = 0x00000FFF; // Dead-Band Fall Delay +pub const PWM_0_DBFALL_DELAY_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC0 +// register. +// +//***************************************************************************** +pub const PWM_0_FLTSRC0_FAULT1: u32 = 0x00000002; // Fault1 Input +pub const PWM_0_FLTSRC0_FAULT0: u32 = 0x00000001; // Fault0 Input +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC1 +// register. +// +//***************************************************************************** +pub const PWM_0_FLTSRC1_DCMP7: u32 = 0x00000080; // Digital Comparator 7 +pub const PWM_0_FLTSRC1_DCMP6: u32 = 0x00000040; // Digital Comparator 6 +pub const PWM_0_FLTSRC1_DCMP5: u32 = 0x00000020; // Digital Comparator 5 +pub const PWM_0_FLTSRC1_DCMP4: u32 = 0x00000010; // Digital Comparator 4 +pub const PWM_0_FLTSRC1_DCMP3: u32 = 0x00000008; // Digital Comparator 3 +pub const PWM_0_FLTSRC1_DCMP2: u32 = 0x00000004; // Digital Comparator 2 +pub const PWM_0_FLTSRC1_DCMP1: u32 = 0x00000002; // Digital Comparator 1 +pub const PWM_0_FLTSRC1_DCMP0: u32 = 0x00000001; // Digital Comparator 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_MINFLTPER +// register. +// +//***************************************************************************** +pub const PWM_0_MINFLTPER_M: u32 = 0x0000FFFF; // Minimum Fault Period +pub const PWM_0_MINFLTPER_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CTL register. +// +//***************************************************************************** +pub const PWM_1_CTL_LATCH: u32 = 0x00040000; // Latch Fault Input +pub const PWM_1_CTL_MINFLTPER: u32 = 0x00020000; // Minimum Fault Period +pub const PWM_1_CTL_FLTSRC: u32 = 0x00010000; // Fault Condition Source +pub const PWM_1_CTL_DBFALLUPD_M: u32 = 0x0000C000; // PWMnDBFALL Update Mode +pub const PWM_1_CTL_DBFALLUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_1_CTL_DBFALLUPD_LS: u32 = 0x00008000; // Locally Synchronized +pub const PWM_1_CTL_DBFALLUPD_GS: u32 = 0x0000C000; // Globally Synchronized +pub const PWM_1_CTL_DBRISEUPD_M: u32 = 0x00003000; // PWMnDBRISE Update Mode +pub const PWM_1_CTL_DBRISEUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_1_CTL_DBRISEUPD_LS: u32 = 0x00002000; // Locally Synchronized +pub const PWM_1_CTL_DBRISEUPD_GS: u32 = 0x00003000; // Globally Synchronized +pub const PWM_1_CTL_DBCTLUPD_M: u32 = 0x00000C00; // PWMnDBCTL Update Mode +pub const PWM_1_CTL_DBCTLUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_1_CTL_DBCTLUPD_LS: u32 = 0x00000800; // Locally Synchronized +pub const PWM_1_CTL_DBCTLUPD_GS: u32 = 0x00000C00; // Globally Synchronized +pub const PWM_1_CTL_GENBUPD_M: u32 = 0x00000300; // PWMnGENB Update Mode +pub const PWM_1_CTL_GENBUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_1_CTL_GENBUPD_LS: u32 = 0x00000200; // Locally Synchronized +pub const PWM_1_CTL_GENBUPD_GS: u32 = 0x00000300; // Globally Synchronized +pub const PWM_1_CTL_GENAUPD_M: u32 = 0x000000C0; // PWMnGENA Update Mode +pub const PWM_1_CTL_GENAUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_1_CTL_GENAUPD_LS: u32 = 0x00000080; // Locally Synchronized +pub const PWM_1_CTL_GENAUPD_GS: u32 = 0x000000C0; // Globally Synchronized +pub const PWM_1_CTL_CMPBUPD: u32 = 0x00000020; // Comparator B Update Mode +pub const PWM_1_CTL_CMPAUPD: u32 = 0x00000010; // Comparator A Update Mode +pub const PWM_1_CTL_LOADUPD: u32 = 0x00000008; // Load Register Update Mode +pub const PWM_1_CTL_DEBUG: u32 = 0x00000004; // Debug Mode +pub const PWM_1_CTL_MODE: u32 = 0x00000002; // Counter Mode +pub const PWM_1_CTL_ENABLE: u32 = 0x00000001; // PWM Block Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_INTEN register. +// +//***************************************************************************** +pub const PWM_1_INTEN_TRCMPBD: u32 = 0x00002000; // Trigger for Counter=PWMnCMPB + // Down +pub const PWM_1_INTEN_TRCMPBU: u32 = 0x00001000; // Trigger for Counter=PWMnCMPB Up +pub const PWM_1_INTEN_TRCMPAD: u32 = 0x00000800; // Trigger for Counter=PWMnCMPA + // Down +pub const PWM_1_INTEN_TRCMPAU: u32 = 0x00000400; // Trigger for Counter=PWMnCMPA Up +pub const PWM_1_INTEN_TRCNTLOAD: u32 = 0x00000200; // Trigger for Counter=PWMnLOAD +pub const PWM_1_INTEN_TRCNTZERO: u32 = 0x00000100; // Trigger for Counter=0 +pub const PWM_1_INTEN_INTCMPBD: u32 = 0x00000020; // Interrupt for Counter=PWMnCMPB + // Down +pub const PWM_1_INTEN_INTCMPBU: u32 = 0x00000010; // Interrupt for Counter=PWMnCMPB + // Up +pub const PWM_1_INTEN_INTCMPAD: u32 = 0x00000008; // Interrupt for Counter=PWMnCMPA + // Down +pub const PWM_1_INTEN_INTCMPAU: u32 = 0x00000004; // Interrupt for Counter=PWMnCMPA + // Up +pub const PWM_1_INTEN_INTCNTLOAD: u32 = 0x00000002; // Interrupt for Counter=PWMnLOAD +pub const PWM_1_INTEN_INTCNTZERO: u32 = 0x00000001; // Interrupt for Counter=0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_RIS register. +// +//***************************************************************************** +pub const PWM_1_RIS_INTCMPBD: u32 = 0x00000020; // Comparator B Down Interrupt + // Status +pub const PWM_1_RIS_INTCMPBU: u32 = 0x00000010; // Comparator B Up Interrupt Status +pub const PWM_1_RIS_INTCMPAD: u32 = 0x00000008; // Comparator A Down Interrupt + // Status +pub const PWM_1_RIS_INTCMPAU: u32 = 0x00000004; // Comparator A Up Interrupt Status +pub const PWM_1_RIS_INTCNTLOAD: u32 = 0x00000002; // Counter=Load Interrupt Status +pub const PWM_1_RIS_INTCNTZERO: u32 = 0x00000001; // Counter=0 Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_ISC register. +// +//***************************************************************************** +pub const PWM_1_ISC_INTCMPBD: u32 = 0x00000020; // Comparator B Down Interrupt +pub const PWM_1_ISC_INTCMPBU: u32 = 0x00000010; // Comparator B Up Interrupt +pub const PWM_1_ISC_INTCMPAD: u32 = 0x00000008; // Comparator A Down Interrupt +pub const PWM_1_ISC_INTCMPAU: u32 = 0x00000004; // Comparator A Up Interrupt +pub const PWM_1_ISC_INTCNTLOAD: u32 = 0x00000002; // Counter=Load Interrupt +pub const PWM_1_ISC_INTCNTZERO: u32 = 0x00000001; // Counter=0 Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_LOAD register. +// +//***************************************************************************** +pub const PWM_1_LOAD_LOAD_M: u32 = 0x0000FFFF; // Counter Load Value +pub const PWM_1_LOAD_LOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_COUNT register. +// +//***************************************************************************** +pub const PWM_1_COUNT_COUNT_M: u32 = 0x0000FFFF; // Counter Value +pub const PWM_1_COUNT_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPA register. +// +//***************************************************************************** +pub const PWM_1_CMPA_COMPA_M: u32 = 0x0000FFFF; // Comparator A Value +pub const PWM_1_CMPA_COMPA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPB register. +// +//***************************************************************************** +pub const PWM_1_CMPB_COMPB_M: u32 = 0x0000FFFF; // Comparator B Value +pub const PWM_1_CMPB_COMPB_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENA register. +// +//***************************************************************************** +pub const PWM_1_GENA_ACTCMPBD_M: u32 = 0x00000C00; // Action for Comparator B Down +pub const PWM_1_GENA_ACTCMPBD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENA_ACTCMPBD_INV: u32 = 0x00000400; // Invert pwmA +pub const PWM_1_GENA_ACTCMPBD_ZERO: u32 = 0x00000800; // Drive pwmA Low +pub const PWM_1_GENA_ACTCMPBD_ONE: u32 = 0x00000C00; // Drive pwmA High +pub const PWM_1_GENA_ACTCMPBU_M: u32 = 0x00000300; // Action for Comparator B Up +pub const PWM_1_GENA_ACTCMPBU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENA_ACTCMPBU_INV: u32 = 0x00000100; // Invert pwmA +pub const PWM_1_GENA_ACTCMPBU_ZERO: u32 = 0x00000200; // Drive pwmA Low +pub const PWM_1_GENA_ACTCMPBU_ONE: u32 = 0x00000300; // Drive pwmA High +pub const PWM_1_GENA_ACTCMPAD_M: u32 = 0x000000C0; // Action for Comparator A Down +pub const PWM_1_GENA_ACTCMPAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENA_ACTCMPAD_INV: u32 = 0x00000040; // Invert pwmA +pub const PWM_1_GENA_ACTCMPAD_ZERO: u32 = 0x00000080; // Drive pwmA Low +pub const PWM_1_GENA_ACTCMPAD_ONE: u32 = 0x000000C0; // Drive pwmA High +pub const PWM_1_GENA_ACTCMPAU_M: u32 = 0x00000030; // Action for Comparator A Up +pub const PWM_1_GENA_ACTCMPAU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENA_ACTCMPAU_INV: u32 = 0x00000010; // Invert pwmA +pub const PWM_1_GENA_ACTCMPAU_ZERO: u32 = 0x00000020; // Drive pwmA Low +pub const PWM_1_GENA_ACTCMPAU_ONE: u32 = 0x00000030; // Drive pwmA High +pub const PWM_1_GENA_ACTLOAD_M: u32 = 0x0000000C; // Action for Counter=LOAD +pub const PWM_1_GENA_ACTLOAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENA_ACTLOAD_INV: u32 = 0x00000004; // Invert pwmA +pub const PWM_1_GENA_ACTLOAD_ZERO: u32 = 0x00000008; // Drive pwmA Low +pub const PWM_1_GENA_ACTLOAD_ONE: u32 = 0x0000000C; // Drive pwmA High +pub const PWM_1_GENA_ACTZERO_M: u32 = 0x00000003; // Action for Counter=0 +pub const PWM_1_GENA_ACTZERO_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENA_ACTZERO_INV: u32 = 0x00000001; // Invert pwmA +pub const PWM_1_GENA_ACTZERO_ZERO: u32 = 0x00000002; // Drive pwmA Low +pub const PWM_1_GENA_ACTZERO_ONE: u32 = 0x00000003; // Drive pwmA High +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENB register. +// +//***************************************************************************** +pub const PWM_1_GENB_ACTCMPBD_M: u32 = 0x00000C00; // Action for Comparator B Down +pub const PWM_1_GENB_ACTCMPBD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENB_ACTCMPBD_INV: u32 = 0x00000400; // Invert pwmB +pub const PWM_1_GENB_ACTCMPBD_ZERO: u32 = 0x00000800; // Drive pwmB Low +pub const PWM_1_GENB_ACTCMPBD_ONE: u32 = 0x00000C00; // Drive pwmB High +pub const PWM_1_GENB_ACTCMPBU_M: u32 = 0x00000300; // Action for Comparator B Up +pub const PWM_1_GENB_ACTCMPBU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENB_ACTCMPBU_INV: u32 = 0x00000100; // Invert pwmB +pub const PWM_1_GENB_ACTCMPBU_ZERO: u32 = 0x00000200; // Drive pwmB Low +pub const PWM_1_GENB_ACTCMPBU_ONE: u32 = 0x00000300; // Drive pwmB High +pub const PWM_1_GENB_ACTCMPAD_M: u32 = 0x000000C0; // Action for Comparator A Down +pub const PWM_1_GENB_ACTCMPAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENB_ACTCMPAD_INV: u32 = 0x00000040; // Invert pwmB +pub const PWM_1_GENB_ACTCMPAD_ZERO: u32 = 0x00000080; // Drive pwmB Low +pub const PWM_1_GENB_ACTCMPAD_ONE: u32 = 0x000000C0; // Drive pwmB High +pub const PWM_1_GENB_ACTCMPAU_M: u32 = 0x00000030; // Action for Comparator A Up +pub const PWM_1_GENB_ACTCMPAU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENB_ACTCMPAU_INV: u32 = 0x00000010; // Invert pwmB +pub const PWM_1_GENB_ACTCMPAU_ZERO: u32 = 0x00000020; // Drive pwmB Low +pub const PWM_1_GENB_ACTCMPAU_ONE: u32 = 0x00000030; // Drive pwmB High +pub const PWM_1_GENB_ACTLOAD_M: u32 = 0x0000000C; // Action for Counter=LOAD +pub const PWM_1_GENB_ACTLOAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENB_ACTLOAD_INV: u32 = 0x00000004; // Invert pwmB +pub const PWM_1_GENB_ACTLOAD_ZERO: u32 = 0x00000008; // Drive pwmB Low +pub const PWM_1_GENB_ACTLOAD_ONE: u32 = 0x0000000C; // Drive pwmB High +pub const PWM_1_GENB_ACTZERO_M: u32 = 0x00000003; // Action for Counter=0 +pub const PWM_1_GENB_ACTZERO_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_1_GENB_ACTZERO_INV: u32 = 0x00000001; // Invert pwmB +pub const PWM_1_GENB_ACTZERO_ZERO: u32 = 0x00000002; // Drive pwmB Low +pub const PWM_1_GENB_ACTZERO_ONE: u32 = 0x00000003; // Drive pwmB High +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBCTL register. +// +//***************************************************************************** +pub const PWM_1_DBCTL_ENABLE: u32 = 0x00000001; // Dead-Band Generator Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBRISE register. +// +//***************************************************************************** +pub const PWM_1_DBRISE_RISEDELAY_M: u32 = 0x00000FFF; // Dead-Band Rise Delay +pub const PWM_1_DBRISE_RISEDELAY_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBFALL register. +// +//***************************************************************************** +pub const PWM_1_DBFALL_FALLDELAY_M: u32 = 0x00000FFF; // Dead-Band Fall Delay +pub const PWM_1_DBFALL_FALLDELAY_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC0 +// register. +// +//***************************************************************************** +pub const PWM_1_FLTSRC0_FAULT1: u32 = 0x00000002; // Fault1 Input +pub const PWM_1_FLTSRC0_FAULT0: u32 = 0x00000001; // Fault0 Input +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC1 +// register. +// +//***************************************************************************** +pub const PWM_1_FLTSRC1_DCMP7: u32 = 0x00000080; // Digital Comparator 7 +pub const PWM_1_FLTSRC1_DCMP6: u32 = 0x00000040; // Digital Comparator 6 +pub const PWM_1_FLTSRC1_DCMP5: u32 = 0x00000020; // Digital Comparator 5 +pub const PWM_1_FLTSRC1_DCMP4: u32 = 0x00000010; // Digital Comparator 4 +pub const PWM_1_FLTSRC1_DCMP3: u32 = 0x00000008; // Digital Comparator 3 +pub const PWM_1_FLTSRC1_DCMP2: u32 = 0x00000004; // Digital Comparator 2 +pub const PWM_1_FLTSRC1_DCMP1: u32 = 0x00000002; // Digital Comparator 1 +pub const PWM_1_FLTSRC1_DCMP0: u32 = 0x00000001; // Digital Comparator 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_MINFLTPER +// register. +// +//***************************************************************************** +pub const PWM_1_MINFLTPER_MFP_M: u32 = 0x0000FFFF; // Minimum Fault Period +pub const PWM_1_MINFLTPER_MFP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CTL register. +// +//***************************************************************************** +pub const PWM_2_CTL_LATCH: u32 = 0x00040000; // Latch Fault Input +pub const PWM_2_CTL_MINFLTPER: u32 = 0x00020000; // Minimum Fault Period +pub const PWM_2_CTL_FLTSRC: u32 = 0x00010000; // Fault Condition Source +pub const PWM_2_CTL_DBFALLUPD_M: u32 = 0x0000C000; // PWMnDBFALL Update Mode +pub const PWM_2_CTL_DBFALLUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_2_CTL_DBFALLUPD_LS: u32 = 0x00008000; // Locally Synchronized +pub const PWM_2_CTL_DBFALLUPD_GS: u32 = 0x0000C000; // Globally Synchronized +pub const PWM_2_CTL_DBRISEUPD_M: u32 = 0x00003000; // PWMnDBRISE Update Mode +pub const PWM_2_CTL_DBRISEUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_2_CTL_DBRISEUPD_LS: u32 = 0x00002000; // Locally Synchronized +pub const PWM_2_CTL_DBRISEUPD_GS: u32 = 0x00003000; // Globally Synchronized +pub const PWM_2_CTL_DBCTLUPD_M: u32 = 0x00000C00; // PWMnDBCTL Update Mode +pub const PWM_2_CTL_DBCTLUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_2_CTL_DBCTLUPD_LS: u32 = 0x00000800; // Locally Synchronized +pub const PWM_2_CTL_DBCTLUPD_GS: u32 = 0x00000C00; // Globally Synchronized +pub const PWM_2_CTL_GENBUPD_M: u32 = 0x00000300; // PWMnGENB Update Mode +pub const PWM_2_CTL_GENBUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_2_CTL_GENBUPD_LS: u32 = 0x00000200; // Locally Synchronized +pub const PWM_2_CTL_GENBUPD_GS: u32 = 0x00000300; // Globally Synchronized +pub const PWM_2_CTL_GENAUPD_M: u32 = 0x000000C0; // PWMnGENA Update Mode +pub const PWM_2_CTL_GENAUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_2_CTL_GENAUPD_LS: u32 = 0x00000080; // Locally Synchronized +pub const PWM_2_CTL_GENAUPD_GS: u32 = 0x000000C0; // Globally Synchronized +pub const PWM_2_CTL_CMPBUPD: u32 = 0x00000020; // Comparator B Update Mode +pub const PWM_2_CTL_CMPAUPD: u32 = 0x00000010; // Comparator A Update Mode +pub const PWM_2_CTL_LOADUPD: u32 = 0x00000008; // Load Register Update Mode +pub const PWM_2_CTL_DEBUG: u32 = 0x00000004; // Debug Mode +pub const PWM_2_CTL_MODE: u32 = 0x00000002; // Counter Mode +pub const PWM_2_CTL_ENABLE: u32 = 0x00000001; // PWM Block Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_INTEN register. +// +//***************************************************************************** +pub const PWM_2_INTEN_TRCMPBD: u32 = 0x00002000; // Trigger for Counter=PWMnCMPB + // Down +pub const PWM_2_INTEN_TRCMPBU: u32 = 0x00001000; // Trigger for Counter=PWMnCMPB Up +pub const PWM_2_INTEN_TRCMPAD: u32 = 0x00000800; // Trigger for Counter=PWMnCMPA + // Down +pub const PWM_2_INTEN_TRCMPAU: u32 = 0x00000400; // Trigger for Counter=PWMnCMPA Up +pub const PWM_2_INTEN_TRCNTLOAD: u32 = 0x00000200; // Trigger for Counter=PWMnLOAD +pub const PWM_2_INTEN_TRCNTZERO: u32 = 0x00000100; // Trigger for Counter=0 +pub const PWM_2_INTEN_INTCMPBD: u32 = 0x00000020; // Interrupt for Counter=PWMnCMPB + // Down +pub const PWM_2_INTEN_INTCMPBU: u32 = 0x00000010; // Interrupt for Counter=PWMnCMPB + // Up +pub const PWM_2_INTEN_INTCMPAD: u32 = 0x00000008; // Interrupt for Counter=PWMnCMPA + // Down +pub const PWM_2_INTEN_INTCMPAU: u32 = 0x00000004; // Interrupt for Counter=PWMnCMPA + // Up +pub const PWM_2_INTEN_INTCNTLOAD: u32 = 0x00000002; // Interrupt for Counter=PWMnLOAD +pub const PWM_2_INTEN_INTCNTZERO: u32 = 0x00000001; // Interrupt for Counter=0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_RIS register. +// +//***************************************************************************** +pub const PWM_2_RIS_INTCMPBD: u32 = 0x00000020; // Comparator B Down Interrupt + // Status +pub const PWM_2_RIS_INTCMPBU: u32 = 0x00000010; // Comparator B Up Interrupt Status +pub const PWM_2_RIS_INTCMPAD: u32 = 0x00000008; // Comparator A Down Interrupt + // Status +pub const PWM_2_RIS_INTCMPAU: u32 = 0x00000004; // Comparator A Up Interrupt Status +pub const PWM_2_RIS_INTCNTLOAD: u32 = 0x00000002; // Counter=Load Interrupt Status +pub const PWM_2_RIS_INTCNTZERO: u32 = 0x00000001; // Counter=0 Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_ISC register. +// +//***************************************************************************** +pub const PWM_2_ISC_INTCMPBD: u32 = 0x00000020; // Comparator B Down Interrupt +pub const PWM_2_ISC_INTCMPBU: u32 = 0x00000010; // Comparator B Up Interrupt +pub const PWM_2_ISC_INTCMPAD: u32 = 0x00000008; // Comparator A Down Interrupt +pub const PWM_2_ISC_INTCMPAU: u32 = 0x00000004; // Comparator A Up Interrupt +pub const PWM_2_ISC_INTCNTLOAD: u32 = 0x00000002; // Counter=Load Interrupt +pub const PWM_2_ISC_INTCNTZERO: u32 = 0x00000001; // Counter=0 Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_LOAD register. +// +//***************************************************************************** +pub const PWM_2_LOAD_LOAD_M: u32 = 0x0000FFFF; // Counter Load Value +pub const PWM_2_LOAD_LOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_COUNT register. +// +//***************************************************************************** +pub const PWM_2_COUNT_COUNT_M: u32 = 0x0000FFFF; // Counter Value +pub const PWM_2_COUNT_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPA register. +// +//***************************************************************************** +pub const PWM_2_CMPA_COMPA_M: u32 = 0x0000FFFF; // Comparator A Value +pub const PWM_2_CMPA_COMPA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPB register. +// +//***************************************************************************** +pub const PWM_2_CMPB_COMPB_M: u32 = 0x0000FFFF; // Comparator B Value +pub const PWM_2_CMPB_COMPB_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENA register. +// +//***************************************************************************** +pub const PWM_2_GENA_ACTCMPBD_M: u32 = 0x00000C00; // Action for Comparator B Down +pub const PWM_2_GENA_ACTCMPBD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENA_ACTCMPBD_INV: u32 = 0x00000400; // Invert pwmA +pub const PWM_2_GENA_ACTCMPBD_ZERO: u32 = 0x00000800; // Drive pwmA Low +pub const PWM_2_GENA_ACTCMPBD_ONE: u32 = 0x00000C00; // Drive pwmA High +pub const PWM_2_GENA_ACTCMPBU_M: u32 = 0x00000300; // Action for Comparator B Up +pub const PWM_2_GENA_ACTCMPBU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENA_ACTCMPBU_INV: u32 = 0x00000100; // Invert pwmA +pub const PWM_2_GENA_ACTCMPBU_ZERO: u32 = 0x00000200; // Drive pwmA Low +pub const PWM_2_GENA_ACTCMPBU_ONE: u32 = 0x00000300; // Drive pwmA High +pub const PWM_2_GENA_ACTCMPAD_M: u32 = 0x000000C0; // Action for Comparator A Down +pub const PWM_2_GENA_ACTCMPAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENA_ACTCMPAD_INV: u32 = 0x00000040; // Invert pwmA +pub const PWM_2_GENA_ACTCMPAD_ZERO: u32 = 0x00000080; // Drive pwmA Low +pub const PWM_2_GENA_ACTCMPAD_ONE: u32 = 0x000000C0; // Drive pwmA High +pub const PWM_2_GENA_ACTCMPAU_M: u32 = 0x00000030; // Action for Comparator A Up +pub const PWM_2_GENA_ACTCMPAU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENA_ACTCMPAU_INV: u32 = 0x00000010; // Invert pwmA +pub const PWM_2_GENA_ACTCMPAU_ZERO: u32 = 0x00000020; // Drive pwmA Low +pub const PWM_2_GENA_ACTCMPAU_ONE: u32 = 0x00000030; // Drive pwmA High +pub const PWM_2_GENA_ACTLOAD_M: u32 = 0x0000000C; // Action for Counter=LOAD +pub const PWM_2_GENA_ACTLOAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENA_ACTLOAD_INV: u32 = 0x00000004; // Invert pwmA +pub const PWM_2_GENA_ACTLOAD_ZERO: u32 = 0x00000008; // Drive pwmA Low +pub const PWM_2_GENA_ACTLOAD_ONE: u32 = 0x0000000C; // Drive pwmA High +pub const PWM_2_GENA_ACTZERO_M: u32 = 0x00000003; // Action for Counter=0 +pub const PWM_2_GENA_ACTZERO_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENA_ACTZERO_INV: u32 = 0x00000001; // Invert pwmA +pub const PWM_2_GENA_ACTZERO_ZERO: u32 = 0x00000002; // Drive pwmA Low +pub const PWM_2_GENA_ACTZERO_ONE: u32 = 0x00000003; // Drive pwmA High +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENB register. +// +//***************************************************************************** +pub const PWM_2_GENB_ACTCMPBD_M: u32 = 0x00000C00; // Action for Comparator B Down +pub const PWM_2_GENB_ACTCMPBD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENB_ACTCMPBD_INV: u32 = 0x00000400; // Invert pwmB +pub const PWM_2_GENB_ACTCMPBD_ZERO: u32 = 0x00000800; // Drive pwmB Low +pub const PWM_2_GENB_ACTCMPBD_ONE: u32 = 0x00000C00; // Drive pwmB High +pub const PWM_2_GENB_ACTCMPBU_M: u32 = 0x00000300; // Action for Comparator B Up +pub const PWM_2_GENB_ACTCMPBU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENB_ACTCMPBU_INV: u32 = 0x00000100; // Invert pwmB +pub const PWM_2_GENB_ACTCMPBU_ZERO: u32 = 0x00000200; // Drive pwmB Low +pub const PWM_2_GENB_ACTCMPBU_ONE: u32 = 0x00000300; // Drive pwmB High +pub const PWM_2_GENB_ACTCMPAD_M: u32 = 0x000000C0; // Action for Comparator A Down +pub const PWM_2_GENB_ACTCMPAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENB_ACTCMPAD_INV: u32 = 0x00000040; // Invert pwmB +pub const PWM_2_GENB_ACTCMPAD_ZERO: u32 = 0x00000080; // Drive pwmB Low +pub const PWM_2_GENB_ACTCMPAD_ONE: u32 = 0x000000C0; // Drive pwmB High +pub const PWM_2_GENB_ACTCMPAU_M: u32 = 0x00000030; // Action for Comparator A Up +pub const PWM_2_GENB_ACTCMPAU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENB_ACTCMPAU_INV: u32 = 0x00000010; // Invert pwmB +pub const PWM_2_GENB_ACTCMPAU_ZERO: u32 = 0x00000020; // Drive pwmB Low +pub const PWM_2_GENB_ACTCMPAU_ONE: u32 = 0x00000030; // Drive pwmB High +pub const PWM_2_GENB_ACTLOAD_M: u32 = 0x0000000C; // Action for Counter=LOAD +pub const PWM_2_GENB_ACTLOAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENB_ACTLOAD_INV: u32 = 0x00000004; // Invert pwmB +pub const PWM_2_GENB_ACTLOAD_ZERO: u32 = 0x00000008; // Drive pwmB Low +pub const PWM_2_GENB_ACTLOAD_ONE: u32 = 0x0000000C; // Drive pwmB High +pub const PWM_2_GENB_ACTZERO_M: u32 = 0x00000003; // Action for Counter=0 +pub const PWM_2_GENB_ACTZERO_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_2_GENB_ACTZERO_INV: u32 = 0x00000001; // Invert pwmB +pub const PWM_2_GENB_ACTZERO_ZERO: u32 = 0x00000002; // Drive pwmB Low +pub const PWM_2_GENB_ACTZERO_ONE: u32 = 0x00000003; // Drive pwmB High +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBCTL register. +// +//***************************************************************************** +pub const PWM_2_DBCTL_ENABLE: u32 = 0x00000001; // Dead-Band Generator Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBRISE register. +// +//***************************************************************************** +pub const PWM_2_DBRISE_RISEDELAY_M: u32 = 0x00000FFF; // Dead-Band Rise Delay +pub const PWM_2_DBRISE_RISEDELAY_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBFALL register. +// +//***************************************************************************** +pub const PWM_2_DBFALL_FALLDELAY_M: u32 = 0x00000FFF; // Dead-Band Fall Delay +pub const PWM_2_DBFALL_FALLDELAY_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC0 +// register. +// +//***************************************************************************** +pub const PWM_2_FLTSRC0_FAULT1: u32 = 0x00000002; // Fault1 Input +pub const PWM_2_FLTSRC0_FAULT0: u32 = 0x00000001; // Fault0 Input +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC1 +// register. +// +//***************************************************************************** +pub const PWM_2_FLTSRC1_DCMP7: u32 = 0x00000080; // Digital Comparator 7 +pub const PWM_2_FLTSRC1_DCMP6: u32 = 0x00000040; // Digital Comparator 6 +pub const PWM_2_FLTSRC1_DCMP5: u32 = 0x00000020; // Digital Comparator 5 +pub const PWM_2_FLTSRC1_DCMP4: u32 = 0x00000010; // Digital Comparator 4 +pub const PWM_2_FLTSRC1_DCMP3: u32 = 0x00000008; // Digital Comparator 3 +pub const PWM_2_FLTSRC1_DCMP2: u32 = 0x00000004; // Digital Comparator 2 +pub const PWM_2_FLTSRC1_DCMP1: u32 = 0x00000002; // Digital Comparator 1 +pub const PWM_2_FLTSRC1_DCMP0: u32 = 0x00000001; // Digital Comparator 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_MINFLTPER +// register. +// +//***************************************************************************** +pub const PWM_2_MINFLTPER_MFP_M: u32 = 0x0000FFFF; // Minimum Fault Period +pub const PWM_2_MINFLTPER_MFP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CTL register. +// +//***************************************************************************** +pub const PWM_3_CTL_LATCH: u32 = 0x00040000; // Latch Fault Input +pub const PWM_3_CTL_MINFLTPER: u32 = 0x00020000; // Minimum Fault Period +pub const PWM_3_CTL_FLTSRC: u32 = 0x00010000; // Fault Condition Source +pub const PWM_3_CTL_DBFALLUPD_M: u32 = 0x0000C000; // PWMnDBFALL Update Mode +pub const PWM_3_CTL_DBFALLUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_3_CTL_DBFALLUPD_LS: u32 = 0x00008000; // Locally Synchronized +pub const PWM_3_CTL_DBFALLUPD_GS: u32 = 0x0000C000; // Globally Synchronized +pub const PWM_3_CTL_DBRISEUPD_M: u32 = 0x00003000; // PWMnDBRISE Update Mode +pub const PWM_3_CTL_DBRISEUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_3_CTL_DBRISEUPD_LS: u32 = 0x00002000; // Locally Synchronized +pub const PWM_3_CTL_DBRISEUPD_GS: u32 = 0x00003000; // Globally Synchronized +pub const PWM_3_CTL_DBCTLUPD_M: u32 = 0x00000C00; // PWMnDBCTL Update Mode +pub const PWM_3_CTL_DBCTLUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_3_CTL_DBCTLUPD_LS: u32 = 0x00000800; // Locally Synchronized +pub const PWM_3_CTL_DBCTLUPD_GS: u32 = 0x00000C00; // Globally Synchronized +pub const PWM_3_CTL_GENBUPD_M: u32 = 0x00000300; // PWMnGENB Update Mode +pub const PWM_3_CTL_GENBUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_3_CTL_GENBUPD_LS: u32 = 0x00000200; // Locally Synchronized +pub const PWM_3_CTL_GENBUPD_GS: u32 = 0x00000300; // Globally Synchronized +pub const PWM_3_CTL_GENAUPD_M: u32 = 0x000000C0; // PWMnGENA Update Mode +pub const PWM_3_CTL_GENAUPD_I: u32 = 0x00000000; // Immediate +pub const PWM_3_CTL_GENAUPD_LS: u32 = 0x00000080; // Locally Synchronized +pub const PWM_3_CTL_GENAUPD_GS: u32 = 0x000000C0; // Globally Synchronized +pub const PWM_3_CTL_CMPBUPD: u32 = 0x00000020; // Comparator B Update Mode +pub const PWM_3_CTL_CMPAUPD: u32 = 0x00000010; // Comparator A Update Mode +pub const PWM_3_CTL_LOADUPD: u32 = 0x00000008; // Load Register Update Mode +pub const PWM_3_CTL_DEBUG: u32 = 0x00000004; // Debug Mode +pub const PWM_3_CTL_MODE: u32 = 0x00000002; // Counter Mode +pub const PWM_3_CTL_ENABLE: u32 = 0x00000001; // PWM Block Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_INTEN register. +// +//***************************************************************************** +pub const PWM_3_INTEN_TRCMPBD: u32 = 0x00002000; // Trigger for Counter=PWMnCMPB + // Down +pub const PWM_3_INTEN_TRCMPBU: u32 = 0x00001000; // Trigger for Counter=PWMnCMPB Up +pub const PWM_3_INTEN_TRCMPAD: u32 = 0x00000800; // Trigger for Counter=PWMnCMPA + // Down +pub const PWM_3_INTEN_TRCMPAU: u32 = 0x00000400; // Trigger for Counter=PWMnCMPA Up +pub const PWM_3_INTEN_TRCNTLOAD: u32 = 0x00000200; // Trigger for Counter=PWMnLOAD +pub const PWM_3_INTEN_TRCNTZERO: u32 = 0x00000100; // Trigger for Counter=0 +pub const PWM_3_INTEN_INTCMPBD: u32 = 0x00000020; // Interrupt for Counter=PWMnCMPB + // Down +pub const PWM_3_INTEN_INTCMPBU: u32 = 0x00000010; // Interrupt for Counter=PWMnCMPB + // Up +pub const PWM_3_INTEN_INTCMPAD: u32 = 0x00000008; // Interrupt for Counter=PWMnCMPA + // Down +pub const PWM_3_INTEN_INTCMPAU: u32 = 0x00000004; // Interrupt for Counter=PWMnCMPA + // Up +pub const PWM_3_INTEN_INTCNTLOAD: u32 = 0x00000002; // Interrupt for Counter=PWMnLOAD +pub const PWM_3_INTEN_INTCNTZERO: u32 = 0x00000001; // Interrupt for Counter=0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_RIS register. +// +//***************************************************************************** +pub const PWM_3_RIS_INTCMPBD: u32 = 0x00000020; // Comparator B Down Interrupt + // Status +pub const PWM_3_RIS_INTCMPBU: u32 = 0x00000010; // Comparator B Up Interrupt Status +pub const PWM_3_RIS_INTCMPAD: u32 = 0x00000008; // Comparator A Down Interrupt + // Status +pub const PWM_3_RIS_INTCMPAU: u32 = 0x00000004; // Comparator A Up Interrupt Status +pub const PWM_3_RIS_INTCNTLOAD: u32 = 0x00000002; // Counter=Load Interrupt Status +pub const PWM_3_RIS_INTCNTZERO: u32 = 0x00000001; // Counter=0 Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_ISC register. +// +//***************************************************************************** +pub const PWM_3_ISC_INTCMPBD: u32 = 0x00000020; // Comparator B Down Interrupt +pub const PWM_3_ISC_INTCMPBU: u32 = 0x00000010; // Comparator B Up Interrupt +pub const PWM_3_ISC_INTCMPAD: u32 = 0x00000008; // Comparator A Down Interrupt +pub const PWM_3_ISC_INTCMPAU: u32 = 0x00000004; // Comparator A Up Interrupt +pub const PWM_3_ISC_INTCNTLOAD: u32 = 0x00000002; // Counter=Load Interrupt +pub const PWM_3_ISC_INTCNTZERO: u32 = 0x00000001; // Counter=0 Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_LOAD register. +// +//***************************************************************************** +pub const PWM_3_LOAD_LOAD_M: u32 = 0x0000FFFF; // Counter Load Value +pub const PWM_3_LOAD_LOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_COUNT register. +// +//***************************************************************************** +pub const PWM_3_COUNT_COUNT_M: u32 = 0x0000FFFF; // Counter Value +pub const PWM_3_COUNT_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPA register. +// +//***************************************************************************** +pub const PWM_3_CMPA_COMPA_M: u32 = 0x0000FFFF; // Comparator A Value +pub const PWM_3_CMPA_COMPA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPB register. +// +//***************************************************************************** +pub const PWM_3_CMPB_COMPB_M: u32 = 0x0000FFFF; // Comparator B Value +pub const PWM_3_CMPB_COMPB_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENA register. +// +//***************************************************************************** +pub const PWM_3_GENA_ACTCMPBD_M: u32 = 0x00000C00; // Action for Comparator B Down +pub const PWM_3_GENA_ACTCMPBD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENA_ACTCMPBD_INV: u32 = 0x00000400; // Invert pwmA +pub const PWM_3_GENA_ACTCMPBD_ZERO: u32 = 0x00000800; // Drive pwmA Low +pub const PWM_3_GENA_ACTCMPBD_ONE: u32 = 0x00000C00; // Drive pwmA High +pub const PWM_3_GENA_ACTCMPBU_M: u32 = 0x00000300; // Action for Comparator B Up +pub const PWM_3_GENA_ACTCMPBU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENA_ACTCMPBU_INV: u32 = 0x00000100; // Invert pwmA +pub const PWM_3_GENA_ACTCMPBU_ZERO: u32 = 0x00000200; // Drive pwmA Low +pub const PWM_3_GENA_ACTCMPBU_ONE: u32 = 0x00000300; // Drive pwmA High +pub const PWM_3_GENA_ACTCMPAD_M: u32 = 0x000000C0; // Action for Comparator A Down +pub const PWM_3_GENA_ACTCMPAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENA_ACTCMPAD_INV: u32 = 0x00000040; // Invert pwmA +pub const PWM_3_GENA_ACTCMPAD_ZERO: u32 = 0x00000080; // Drive pwmA Low +pub const PWM_3_GENA_ACTCMPAD_ONE: u32 = 0x000000C0; // Drive pwmA High +pub const PWM_3_GENA_ACTCMPAU_M: u32 = 0x00000030; // Action for Comparator A Up +pub const PWM_3_GENA_ACTCMPAU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENA_ACTCMPAU_INV: u32 = 0x00000010; // Invert pwmA +pub const PWM_3_GENA_ACTCMPAU_ZERO: u32 = 0x00000020; // Drive pwmA Low +pub const PWM_3_GENA_ACTCMPAU_ONE: u32 = 0x00000030; // Drive pwmA High +pub const PWM_3_GENA_ACTLOAD_M: u32 = 0x0000000C; // Action for Counter=LOAD +pub const PWM_3_GENA_ACTLOAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENA_ACTLOAD_INV: u32 = 0x00000004; // Invert pwmA +pub const PWM_3_GENA_ACTLOAD_ZERO: u32 = 0x00000008; // Drive pwmA Low +pub const PWM_3_GENA_ACTLOAD_ONE: u32 = 0x0000000C; // Drive pwmA High +pub const PWM_3_GENA_ACTZERO_M: u32 = 0x00000003; // Action for Counter=0 +pub const PWM_3_GENA_ACTZERO_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENA_ACTZERO_INV: u32 = 0x00000001; // Invert pwmA +pub const PWM_3_GENA_ACTZERO_ZERO: u32 = 0x00000002; // Drive pwmA Low +pub const PWM_3_GENA_ACTZERO_ONE: u32 = 0x00000003; // Drive pwmA High +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENB register. +// +//***************************************************************************** +pub const PWM_3_GENB_ACTCMPBD_M: u32 = 0x00000C00; // Action for Comparator B Down +pub const PWM_3_GENB_ACTCMPBD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENB_ACTCMPBD_INV: u32 = 0x00000400; // Invert pwmB +pub const PWM_3_GENB_ACTCMPBD_ZERO: u32 = 0x00000800; // Drive pwmB Low +pub const PWM_3_GENB_ACTCMPBD_ONE: u32 = 0x00000C00; // Drive pwmB High +pub const PWM_3_GENB_ACTCMPBU_M: u32 = 0x00000300; // Action for Comparator B Up +pub const PWM_3_GENB_ACTCMPBU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENB_ACTCMPBU_INV: u32 = 0x00000100; // Invert pwmB +pub const PWM_3_GENB_ACTCMPBU_ZERO: u32 = 0x00000200; // Drive pwmB Low +pub const PWM_3_GENB_ACTCMPBU_ONE: u32 = 0x00000300; // Drive pwmB High +pub const PWM_3_GENB_ACTCMPAD_M: u32 = 0x000000C0; // Action for Comparator A Down +pub const PWM_3_GENB_ACTCMPAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENB_ACTCMPAD_INV: u32 = 0x00000040; // Invert pwmB +pub const PWM_3_GENB_ACTCMPAD_ZERO: u32 = 0x00000080; // Drive pwmB Low +pub const PWM_3_GENB_ACTCMPAD_ONE: u32 = 0x000000C0; // Drive pwmB High +pub const PWM_3_GENB_ACTCMPAU_M: u32 = 0x00000030; // Action for Comparator A Up +pub const PWM_3_GENB_ACTCMPAU_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENB_ACTCMPAU_INV: u32 = 0x00000010; // Invert pwmB +pub const PWM_3_GENB_ACTCMPAU_ZERO: u32 = 0x00000020; // Drive pwmB Low +pub const PWM_3_GENB_ACTCMPAU_ONE: u32 = 0x00000030; // Drive pwmB High +pub const PWM_3_GENB_ACTLOAD_M: u32 = 0x0000000C; // Action for Counter=LOAD +pub const PWM_3_GENB_ACTLOAD_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENB_ACTLOAD_INV: u32 = 0x00000004; // Invert pwmB +pub const PWM_3_GENB_ACTLOAD_ZERO: u32 = 0x00000008; // Drive pwmB Low +pub const PWM_3_GENB_ACTLOAD_ONE: u32 = 0x0000000C; // Drive pwmB High +pub const PWM_3_GENB_ACTZERO_M: u32 = 0x00000003; // Action for Counter=0 +pub const PWM_3_GENB_ACTZERO_NONE: u32 = 0x00000000; // Do nothing +pub const PWM_3_GENB_ACTZERO_INV: u32 = 0x00000001; // Invert pwmB +pub const PWM_3_GENB_ACTZERO_ZERO: u32 = 0x00000002; // Drive pwmB Low +pub const PWM_3_GENB_ACTZERO_ONE: u32 = 0x00000003; // Drive pwmB High +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBCTL register. +// +//***************************************************************************** +pub const PWM_3_DBCTL_ENABLE: u32 = 0x00000001; // Dead-Band Generator Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBRISE register. +// +//***************************************************************************** +pub const PWM_3_DBRISE_RISEDELAY_M: u32 = 0x00000FFF; // Dead-Band Rise Delay +pub const PWM_3_DBRISE_RISEDELAY_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBFALL register. +// +//***************************************************************************** +pub const PWM_3_DBFALL_FALLDELAY_M: u32 = 0x00000FFF; // Dead-Band Fall Delay +pub const PWM_3_DBFALL_FALLDELAY_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC0 +// register. +// +//***************************************************************************** +pub const PWM_3_FLTSRC0_FAULT1: u32 = 0x00000002; // Fault1 Input +pub const PWM_3_FLTSRC0_FAULT0: u32 = 0x00000001; // Fault0 Input +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC1 +// register. +// +//***************************************************************************** +pub const PWM_3_FLTSRC1_DCMP7: u32 = 0x00000080; // Digital Comparator 7 +pub const PWM_3_FLTSRC1_DCMP6: u32 = 0x00000040; // Digital Comparator 6 +pub const PWM_3_FLTSRC1_DCMP5: u32 = 0x00000020; // Digital Comparator 5 +pub const PWM_3_FLTSRC1_DCMP4: u32 = 0x00000010; // Digital Comparator 4 +pub const PWM_3_FLTSRC1_DCMP3: u32 = 0x00000008; // Digital Comparator 3 +pub const PWM_3_FLTSRC1_DCMP2: u32 = 0x00000004; // Digital Comparator 2 +pub const PWM_3_FLTSRC1_DCMP1: u32 = 0x00000002; // Digital Comparator 1 +pub const PWM_3_FLTSRC1_DCMP0: u32 = 0x00000001; // Digital Comparator 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_MINFLTPER +// register. +// +//***************************************************************************** +pub const PWM_3_MINFLTPER_MFP_M: u32 = 0x0000FFFF; // Minimum Fault Period +pub const PWM_3_MINFLTPER_MFP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSEN register. +// +//***************************************************************************** +pub const PWM_0_FLTSEN_FAULT1: u32 = 0x00000002; // Fault1 Sense +pub const PWM_0_FLTSEN_FAULT0: u32 = 0x00000001; // Fault0 Sense +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 +// register. +// +//***************************************************************************** +pub const PWM_0_FLTSTAT0_FAULT1: u32 = 0x00000002; // Fault Input 1 +pub const PWM_0_FLTSTAT0_FAULT0: u32 = 0x00000001; // Fault Input 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 +// register. +// +//***************************************************************************** +pub const PWM_0_FLTSTAT1_DCMP7: u32 = 0x00000080; // Digital Comparator 7 Trigger +pub const PWM_0_FLTSTAT1_DCMP6: u32 = 0x00000040; // Digital Comparator 6 Trigger +pub const PWM_0_FLTSTAT1_DCMP5: u32 = 0x00000020; // Digital Comparator 5 Trigger +pub const PWM_0_FLTSTAT1_DCMP4: u32 = 0x00000010; // Digital Comparator 4 Trigger +pub const PWM_0_FLTSTAT1_DCMP3: u32 = 0x00000008; // Digital Comparator 3 Trigger +pub const PWM_0_FLTSTAT1_DCMP2: u32 = 0x00000004; // Digital Comparator 2 Trigger +pub const PWM_0_FLTSTAT1_DCMP1: u32 = 0x00000002; // Digital Comparator 1 Trigger +pub const PWM_0_FLTSTAT1_DCMP0: u32 = 0x00000001; // Digital Comparator 0 Trigger +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSEN register. +// +//***************************************************************************** +pub const PWM_1_FLTSEN_FAULT1: u32 = 0x00000002; // Fault1 Sense +pub const PWM_1_FLTSEN_FAULT0: u32 = 0x00000001; // Fault0 Sense +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 +// register. +// +//***************************************************************************** +pub const PWM_1_FLTSTAT0_FAULT1: u32 = 0x00000002; // Fault Input 1 +pub const PWM_1_FLTSTAT0_FAULT0: u32 = 0x00000001; // Fault Input 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 +// register. +// +//***************************************************************************** +pub const PWM_1_FLTSTAT1_DCMP7: u32 = 0x00000080; // Digital Comparator 7 Trigger +pub const PWM_1_FLTSTAT1_DCMP6: u32 = 0x00000040; // Digital Comparator 6 Trigger +pub const PWM_1_FLTSTAT1_DCMP5: u32 = 0x00000020; // Digital Comparator 5 Trigger +pub const PWM_1_FLTSTAT1_DCMP4: u32 = 0x00000010; // Digital Comparator 4 Trigger +pub const PWM_1_FLTSTAT1_DCMP3: u32 = 0x00000008; // Digital Comparator 3 Trigger +pub const PWM_1_FLTSTAT1_DCMP2: u32 = 0x00000004; // Digital Comparator 2 Trigger +pub const PWM_1_FLTSTAT1_DCMP1: u32 = 0x00000002; // Digital Comparator 1 Trigger +pub const PWM_1_FLTSTAT1_DCMP0: u32 = 0x00000001; // Digital Comparator 0 Trigger +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 +// register. +// +//***************************************************************************** +pub const PWM_2_FLTSTAT0_FAULT1: u32 = 0x00000002; // Fault Input 1 +pub const PWM_2_FLTSTAT0_FAULT0: u32 = 0x00000001; // Fault Input 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 +// register. +// +//***************************************************************************** +pub const PWM_2_FLTSTAT1_DCMP7: u32 = 0x00000080; // Digital Comparator 7 Trigger +pub const PWM_2_FLTSTAT1_DCMP6: u32 = 0x00000040; // Digital Comparator 6 Trigger +pub const PWM_2_FLTSTAT1_DCMP5: u32 = 0x00000020; // Digital Comparator 5 Trigger +pub const PWM_2_FLTSTAT1_DCMP4: u32 = 0x00000010; // Digital Comparator 4 Trigger +pub const PWM_2_FLTSTAT1_DCMP3: u32 = 0x00000008; // Digital Comparator 3 Trigger +pub const PWM_2_FLTSTAT1_DCMP2: u32 = 0x00000004; // Digital Comparator 2 Trigger +pub const PWM_2_FLTSTAT1_DCMP1: u32 = 0x00000002; // Digital Comparator 1 Trigger +pub const PWM_2_FLTSTAT1_DCMP0: u32 = 0x00000001; // Digital Comparator 0 Trigger +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 +// register. +// +//***************************************************************************** +pub const PWM_3_FLTSTAT0_FAULT1: u32 = 0x00000002; // Fault Input 1 +pub const PWM_3_FLTSTAT0_FAULT0: u32 = 0x00000001; // Fault Input 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 +// register. +// +//***************************************************************************** +pub const PWM_3_FLTSTAT1_DCMP7: u32 = 0x00000080; // Digital Comparator 7 Trigger +pub const PWM_3_FLTSTAT1_DCMP6: u32 = 0x00000040; // Digital Comparator 6 Trigger +pub const PWM_3_FLTSTAT1_DCMP5: u32 = 0x00000020; // Digital Comparator 5 Trigger +pub const PWM_3_FLTSTAT1_DCMP4: u32 = 0x00000010; // Digital Comparator 4 Trigger +pub const PWM_3_FLTSTAT1_DCMP3: u32 = 0x00000008; // Digital Comparator 3 Trigger +pub const PWM_3_FLTSTAT1_DCMP2: u32 = 0x00000004; // Digital Comparator 2 Trigger +pub const PWM_3_FLTSTAT1_DCMP1: u32 = 0x00000002; // Digital Comparator 1 Trigger +pub const PWM_3_FLTSTAT1_DCMP0: u32 = 0x00000001; // Digital Comparator 0 Trigger +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_PP register. +// +//***************************************************************************** +pub const PWM_PP_ONE: u32 = 0x00000400; // One-Shot Mode +pub const PWM_PP_EFAULT: u32 = 0x00000200; // Extended Fault +pub const PWM_PP_ESYNC: u32 = 0x00000100; // Extended Synchronization +pub const PWM_PP_FCNT_M: u32 = 0x000000F0; // Fault Inputs (per PWM unit) +pub const PWM_PP_GCNT_M: u32 = 0x0000000F; // Generators +pub const PWM_PP_FCNT_S: u32 = 4; +pub const PWM_PP_GCNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_CTL register. +// +//***************************************************************************** +pub const QEI_CTL_FILTCNT_M: u32 = 0x000F0000; // Input Filter Prescale Count +pub const QEI_CTL_FILTEN: u32 = 0x00002000; // Enable Input Filter +pub const QEI_CTL_STALLEN: u32 = 0x00001000; // Stall QEI +pub const QEI_CTL_INVI: u32 = 0x00000800; // Invert Index Pulse +pub const QEI_CTL_INVB: u32 = 0x00000400; // Invert PhB +pub const QEI_CTL_INVA: u32 = 0x00000200; // Invert PhA +pub const QEI_CTL_VELDIV_M: u32 = 0x000001C0; // Predivide Velocity +pub const QEI_CTL_VELDIV_1: u32 = 0x00000000; // QEI clock /1 +pub const QEI_CTL_VELDIV_2: u32 = 0x00000040; // QEI clock /2 +pub const QEI_CTL_VELDIV_4: u32 = 0x00000080; // QEI clock /4 +pub const QEI_CTL_VELDIV_8: u32 = 0x000000C0; // QEI clock /8 +pub const QEI_CTL_VELDIV_16: u32 = 0x00000100; // QEI clock /16 +pub const QEI_CTL_VELDIV_32: u32 = 0x00000140; // QEI clock /32 +pub const QEI_CTL_VELDIV_64: u32 = 0x00000180; // QEI clock /64 +pub const QEI_CTL_VELDIV_128: u32 = 0x000001C0; // QEI clock /128 +pub const QEI_CTL_VELEN: u32 = 0x00000020; // Capture Velocity +pub const QEI_CTL_RESMODE: u32 = 0x00000010; // Reset Mode +pub const QEI_CTL_CAPMODE: u32 = 0x00000008; // Capture Mode +pub const QEI_CTL_SIGMODE: u32 = 0x00000004; // Signal Mode +pub const QEI_CTL_SWAP: u32 = 0x00000002; // Swap Signals +pub const QEI_CTL_ENABLE: u32 = 0x00000001; // Enable QEI +pub const QEI_CTL_FILTCNT_S: u32 = 16; +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_STAT register. +// +//***************************************************************************** +pub const QEI_STAT_DIRECTION: u32 = 0x00000002; // Direction of Rotation +pub const QEI_STAT_ERROR: u32 = 0x00000001; // Error Detected +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_POS register. +// +//***************************************************************************** +pub const QEI_POS_M: u32 = 0xFFFFFFFF; // Current Position Integrator + // Value +pub const QEI_POS_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_MAXPOS register. +// +//***************************************************************************** +pub const QEI_MAXPOS_M: u32 = 0xFFFFFFFF; // Maximum Position Integrator + // Value +pub const QEI_MAXPOS_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_LOAD register. +// +//***************************************************************************** +pub const QEI_LOAD_M: u32 = 0xFFFFFFFF; // Velocity Timer Load Value +pub const QEI_LOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_TIME register. +// +//***************************************************************************** +pub const QEI_TIME_M: u32 = 0xFFFFFFFF; // Velocity Timer Current Value +pub const QEI_TIME_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_COUNT register. +// +//***************************************************************************** +pub const QEI_COUNT_M: u32 = 0xFFFFFFFF; // Velocity Pulse Count +pub const QEI_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_SPEED register. +// +//***************************************************************************** +pub const QEI_SPEED_M: u32 = 0xFFFFFFFF; // Velocity +pub const QEI_SPEED_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_INTEN register. +// +//***************************************************************************** +pub const QEI_INTEN_ERROR: u32 = 0x00000008; // Phase Error Interrupt Enable +pub const QEI_INTEN_DIR: u32 = 0x00000004; // Direction Change Interrupt + // Enable +pub const QEI_INTEN_TIMER: u32 = 0x00000002; // Timer Expires Interrupt Enable +pub const QEI_INTEN_INDEX: u32 = 0x00000001; // Index Pulse Detected Interrupt + // Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_RIS register. +// +//***************************************************************************** +pub const QEI_RIS_ERROR: u32 = 0x00000008; // Phase Error Detected +pub const QEI_RIS_DIR: u32 = 0x00000004; // Direction Change Detected +pub const QEI_RIS_TIMER: u32 = 0x00000002; // Velocity Timer Expired +pub const QEI_RIS_INDEX: u32 = 0x00000001; // Index Pulse Asserted +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_ISC register. +// +//***************************************************************************** +pub const QEI_ISC_ERROR: u32 = 0x00000008; // Phase Error Interrupt +pub const QEI_ISC_DIR: u32 = 0x00000004; // Direction Change Interrupt +pub const QEI_ISC_TIMER: u32 = 0x00000002; // Velocity Timer Expired Interrupt +pub const QEI_ISC_INDEX: u32 = 0x00000001; // Index Pulse Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +pub const TIMER_CFG_M: u32 = 0x00000007; // GPTM Configuration +pub const TIMER_CFG_32_BIT_TIMER: u32 = 0x00000000; // For a 16/32-bit timer, this + // value selects the 32-bit timer + // configuration +pub const TIMER_CFG_32_BIT_RTC: u32 = 0x00000001; // For a 16/32-bit timer, this + // value selects the 32-bit + // real-time clock (RTC) counter + // configuration +pub const TIMER_CFG_16_BIT: u32 = 0x00000004; // For a 16/32-bit timer, this + // value selects the 16-bit timer + // configuration +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +pub const TIMER_TAMR_TAPLO: u32 = 0x00000800; // GPTM Timer A PWM Legacy + // Operation +pub const TIMER_TAMR_TAMRSU: u32 = 0x00000400; // GPTM Timer A Match Register + // Update +pub const TIMER_TAMR_TAPWMIE: u32 = 0x00000200; // GPTM Timer A PWM Interrupt + // Enable +pub const TIMER_TAMR_TAILD: u32 = 0x00000100; // GPTM Timer A Interval Load Write +pub const TIMER_TAMR_TASNAPS: u32 = 0x00000080; // GPTM Timer A Snap-Shot Mode +pub const TIMER_TAMR_TAWOT: u32 = 0x00000040; // GPTM Timer A Wait-on-Trigger +pub const TIMER_TAMR_TAMIE: u32 = 0x00000020; // GPTM Timer A Match Interrupt + // Enable +pub const TIMER_TAMR_TACDIR: u32 = 0x00000010; // GPTM Timer A Count Direction +pub const TIMER_TAMR_TAAMS: u32 = 0x00000008; // GPTM Timer A Alternate Mode + // Select +pub const TIMER_TAMR_TACMR: u32 = 0x00000004; // GPTM Timer A Capture Mode +pub const TIMER_TAMR_TAMR_M: u32 = 0x00000003; // GPTM Timer A Mode +pub const TIMER_TAMR_TAMR_1_SHOT: u32 = 0x00000001; // One-Shot Timer mode +pub const TIMER_TAMR_TAMR_PERIOD: u32 = 0x00000002; // Periodic Timer mode +pub const TIMER_TAMR_TAMR_CAP: u32 = 0x00000003; // Capture mode +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +pub const TIMER_TBMR_TBPLO: u32 = 0x00000800; // GPTM Timer B PWM Legacy + // Operation +pub const TIMER_TBMR_TBMRSU: u32 = 0x00000400; // GPTM Timer B Match Register + // Update +pub const TIMER_TBMR_TBPWMIE: u32 = 0x00000200; // GPTM Timer B PWM Interrupt + // Enable +pub const TIMER_TBMR_TBILD: u32 = 0x00000100; // GPTM Timer B Interval Load Write +pub const TIMER_TBMR_TBSNAPS: u32 = 0x00000080; // GPTM Timer B Snap-Shot Mode +pub const TIMER_TBMR_TBWOT: u32 = 0x00000040; // GPTM Timer B Wait-on-Trigger +pub const TIMER_TBMR_TBMIE: u32 = 0x00000020; // GPTM Timer B Match Interrupt + // Enable +pub const TIMER_TBMR_TBCDIR: u32 = 0x00000010; // GPTM Timer B Count Direction +pub const TIMER_TBMR_TBAMS: u32 = 0x00000008; // GPTM Timer B Alternate Mode + // Select +pub const TIMER_TBMR_TBCMR: u32 = 0x00000004; // GPTM Timer B Capture Mode +pub const TIMER_TBMR_TBMR_M: u32 = 0x00000003; // GPTM Timer B Mode +pub const TIMER_TBMR_TBMR_1_SHOT: u32 = 0x00000001; // One-Shot Timer mode +pub const TIMER_TBMR_TBMR_PERIOD: u32 = 0x00000002; // Periodic Timer mode +pub const TIMER_TBMR_TBMR_CAP: u32 = 0x00000003; // Capture mode +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +pub const TIMER_CTL_TBPWML: u32 = 0x00004000; // GPTM Timer B PWM Output Level +pub const TIMER_CTL_TBOTE: u32 = 0x00002000; // GPTM Timer B Output Trigger + // Enable +pub const TIMER_CTL_TBEVENT_M: u32 = 0x00000C00; // GPTM Timer B Event Mode +pub const TIMER_CTL_TBEVENT_POS: u32 = 0x00000000; // Positive edge +pub const TIMER_CTL_TBEVENT_NEG: u32 = 0x00000400; // Negative edge +pub const TIMER_CTL_TBEVENT_BOTH: u32 = 0x00000C00; // Both edges +pub const TIMER_CTL_TBSTALL: u32 = 0x00000200; // GPTM Timer B Stall Enable +pub const TIMER_CTL_TBEN: u32 = 0x00000100; // GPTM Timer B Enable +pub const TIMER_CTL_TAPWML: u32 = 0x00000040; // GPTM Timer A PWM Output Level +pub const TIMER_CTL_TAOTE: u32 = 0x00000020; // GPTM Timer A Output Trigger + // Enable +pub const TIMER_CTL_RTCEN: u32 = 0x00000010; // GPTM RTC Stall Enable +pub const TIMER_CTL_TAEVENT_M: u32 = 0x0000000C; // GPTM Timer A Event Mode +pub const TIMER_CTL_TAEVENT_POS: u32 = 0x00000000; // Positive edge +pub const TIMER_CTL_TAEVENT_NEG: u32 = 0x00000004; // Negative edge +pub const TIMER_CTL_TAEVENT_BOTH: u32 = 0x0000000C; // Both edges +pub const TIMER_CTL_TASTALL: u32 = 0x00000002; // GPTM Timer A Stall Enable +pub const TIMER_CTL_TAEN: u32 = 0x00000001; // GPTM Timer A Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +pub const TIMER_SYNC_SYNCWT5_M: u32 = 0x00C00000; // Synchronize GPTM 32/64-Bit Timer + // 5 +pub const TIMER_SYNC_SYNCWT5_NONE: u32 = 0x00000000; // GPTM 32/64-Bit Timer 5 is not + // affected +pub const TIMER_SYNC_SYNCWT5_TA: u32 = 0x00400000; // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 5 is + // triggered +pub const TIMER_SYNC_SYNCWT5_TB: u32 = 0x00800000; // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 5 is + // triggered +pub const TIMER_SYNC_SYNCWT5_TATB: u32 = 0x00C00000; // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 5 is triggered +pub const TIMER_SYNC_SYNCWT4_M: u32 = 0x00300000; // Synchronize GPTM 32/64-Bit Timer + // 4 +pub const TIMER_SYNC_SYNCWT4_NONE: u32 = 0x00000000; // GPTM 32/64-Bit Timer 4 is not + // affected +pub const TIMER_SYNC_SYNCWT4_TA: u32 = 0x00100000; // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 4 is + // triggered +pub const TIMER_SYNC_SYNCWT4_TB: u32 = 0x00200000; // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 4 is + // triggered +pub const TIMER_SYNC_SYNCWT4_TATB: u32 = 0x00300000; // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 4 is triggered +pub const TIMER_SYNC_SYNCWT3_M: u32 = 0x000C0000; // Synchronize GPTM 32/64-Bit Timer + // 3 +pub const TIMER_SYNC_SYNCWT3_NONE: u32 = 0x00000000; // GPTM 32/64-Bit Timer 3 is not + // affected +pub const TIMER_SYNC_SYNCWT3_TA: u32 = 0x00040000; // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 3 is + // triggered +pub const TIMER_SYNC_SYNCWT3_TB: u32 = 0x00080000; // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 3 is + // triggered +pub const TIMER_SYNC_SYNCWT3_TATB: u32 = 0x000C0000; // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 3 is triggered +pub const TIMER_SYNC_SYNCWT2_M: u32 = 0x00030000; // Synchronize GPTM 32/64-Bit Timer + // 2 +pub const TIMER_SYNC_SYNCWT2_NONE: u32 = 0x00000000; // GPTM 32/64-Bit Timer 2 is not + // affected +pub const TIMER_SYNC_SYNCWT2_TA: u32 = 0x00010000; // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 2 is + // triggered +pub const TIMER_SYNC_SYNCWT2_TB: u32 = 0x00020000; // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 2 is + // triggered +pub const TIMER_SYNC_SYNCWT2_TATB: u32 = 0x00030000; // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 2 is triggered +pub const TIMER_SYNC_SYNCWT1_M: u32 = 0x0000C000; // Synchronize GPTM 32/64-Bit Timer + // 1 +pub const TIMER_SYNC_SYNCWT1_NONE: u32 = 0x00000000; // GPTM 32/64-Bit Timer 1 is not + // affected +pub const TIMER_SYNC_SYNCWT1_TA: u32 = 0x00004000; // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 1 is + // triggered +pub const TIMER_SYNC_SYNCWT1_TB: u32 = 0x00008000; // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 1 is + // triggered +pub const TIMER_SYNC_SYNCWT1_TATB: u32 = 0x0000C000; // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 1 is triggered +pub const TIMER_SYNC_SYNCWT0_M: u32 = 0x00003000; // Synchronize GPTM 32/64-Bit Timer + // 0 +pub const TIMER_SYNC_SYNCWT0_NONE: u32 = 0x00000000; // GPTM 32/64-Bit Timer 0 is not + // affected +pub const TIMER_SYNC_SYNCWT0_TA: u32 = 0x00001000; // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 0 is + // triggered +pub const TIMER_SYNC_SYNCWT0_TB: u32 = 0x00002000; // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 0 is + // triggered +pub const TIMER_SYNC_SYNCWT0_TATB: u32 = 0x00003000; // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 0 is triggered +pub const TIMER_SYNC_SYNCT5_M: u32 = 0x00000C00; // Synchronize GPTM Timer 5 +pub const TIMER_SYNC_SYNCT5_NONE: u32 = 0x00000000; // GPTM5 is not affected +pub const TIMER_SYNC_SYNCT5_TA: u32 = 0x00000400; // A timeout event for Timer A of + // GPTM5 is triggered +pub const TIMER_SYNC_SYNCT5_TB: u32 = 0x00000800; // A timeout event for Timer B of + // GPTM5 is triggered +pub const TIMER_SYNC_SYNCT5_TATB: u32 = 0x00000C00; // A timeout event for both Timer A + // and Timer B of GPTM5 is + // triggered +pub const TIMER_SYNC_SYNCT4_M: u32 = 0x00000300; // Synchronize GPTM Timer 4 +pub const TIMER_SYNC_SYNCT4_NONE: u32 = 0x00000000; // GPTM4 is not affected +pub const TIMER_SYNC_SYNCT4_TA: u32 = 0x00000100; // A timeout event for Timer A of + // GPTM4 is triggered +pub const TIMER_SYNC_SYNCT4_TB: u32 = 0x00000200; // A timeout event for Timer B of + // GPTM4 is triggered +pub const TIMER_SYNC_SYNCT4_TATB: u32 = 0x00000300; // A timeout event for both Timer A + // and Timer B of GPTM4 is + // triggered +pub const TIMER_SYNC_SYNCT3_M: u32 = 0x000000C0; // Synchronize GPTM Timer 3 +pub const TIMER_SYNC_SYNCT3_NONE: u32 = 0x00000000; // GPTM3 is not affected +pub const TIMER_SYNC_SYNCT3_TA: u32 = 0x00000040; // A timeout event for Timer A of + // GPTM3 is triggered +pub const TIMER_SYNC_SYNCT3_TB: u32 = 0x00000080; // A timeout event for Timer B of + // GPTM3 is triggered +pub const TIMER_SYNC_SYNCT3_TATB: u32 = 0x000000C0; // A timeout event for both Timer A + // and Timer B of GPTM3 is + // triggered +pub const TIMER_SYNC_SYNCT2_M: u32 = 0x00000030; // Synchronize GPTM Timer 2 +pub const TIMER_SYNC_SYNCT2_NONE: u32 = 0x00000000; // GPTM2 is not affected +pub const TIMER_SYNC_SYNCT2_TA: u32 = 0x00000010; // A timeout event for Timer A of + // GPTM2 is triggered +pub const TIMER_SYNC_SYNCT2_TB: u32 = 0x00000020; // A timeout event for Timer B of + // GPTM2 is triggered +pub const TIMER_SYNC_SYNCT2_TATB: u32 = 0x00000030; // A timeout event for both Timer A + // and Timer B of GPTM2 is + // triggered +pub const TIMER_SYNC_SYNCT1_M: u32 = 0x0000000C; // Synchronize GPTM Timer 1 +pub const TIMER_SYNC_SYNCT1_NONE: u32 = 0x00000000; // GPTM1 is not affected +pub const TIMER_SYNC_SYNCT1_TA: u32 = 0x00000004; // A timeout event for Timer A of + // GPTM1 is triggered +pub const TIMER_SYNC_SYNCT1_TB: u32 = 0x00000008; // A timeout event for Timer B of + // GPTM1 is triggered +pub const TIMER_SYNC_SYNCT1_TATB: u32 = 0x0000000C; // A timeout event for both Timer A + // and Timer B of GPTM1 is + // triggered +pub const TIMER_SYNC_SYNCT0_M: u32 = 0x00000003; // Synchronize GPTM Timer 0 +pub const TIMER_SYNC_SYNCT0_NONE: u32 = 0x00000000; // GPTM0 is not affected +pub const TIMER_SYNC_SYNCT0_TA: u32 = 0x00000001; // A timeout event for Timer A of + // GPTM0 is triggered +pub const TIMER_SYNC_SYNCT0_TB: u32 = 0x00000002; // A timeout event for Timer B of + // GPTM0 is triggered +pub const TIMER_SYNC_SYNCT0_TATB: u32 = 0x00000003; // A timeout event for both Timer A + // and Timer B of GPTM0 is + // triggered +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +pub const TIMER_IMR_WUEIM: u32 = 0x00010000; // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Mask +pub const TIMER_IMR_TBMIM: u32 = 0x00000800; // GPTM Timer B Match Interrupt + // Mask +pub const TIMER_IMR_CBEIM: u32 = 0x00000400; // GPTM Timer B Capture Mode Event + // Interrupt Mask +pub const TIMER_IMR_CBMIM: u32 = 0x00000200; // GPTM Timer B Capture Mode Match + // Interrupt Mask +pub const TIMER_IMR_TBTOIM: u32 = 0x00000100; // GPTM Timer B Time-Out Interrupt + // Mask +pub const TIMER_IMR_TAMIM: u32 = 0x00000010; // GPTM Timer A Match Interrupt + // Mask +pub const TIMER_IMR_RTCIM: u32 = 0x00000008; // GPTM RTC Interrupt Mask +pub const TIMER_IMR_CAEIM: u32 = 0x00000004; // GPTM Timer A Capture Mode Event + // Interrupt Mask +pub const TIMER_IMR_CAMIM: u32 = 0x00000002; // GPTM Timer A Capture Mode Match + // Interrupt Mask +pub const TIMER_IMR_TATOIM: u32 = 0x00000001; // GPTM Timer A Time-Out Interrupt + // Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +pub const TIMER_RIS_WUERIS: u32 = 0x00010000; // 32/64-Bit Wide GPTM Write Update + // Error Raw Interrupt Status +pub const TIMER_RIS_TBMRIS: u32 = 0x00000800; // GPTM Timer B Match Raw Interrupt +pub const TIMER_RIS_CBERIS: u32 = 0x00000400; // GPTM Timer B Capture Mode Event + // Raw Interrupt +pub const TIMER_RIS_CBMRIS: u32 = 0x00000200; // GPTM Timer B Capture Mode Match + // Raw Interrupt +pub const TIMER_RIS_TBTORIS: u32 = 0x00000100; // GPTM Timer B Time-Out Raw + // Interrupt +pub const TIMER_RIS_TAMRIS: u32 = 0x00000010; // GPTM Timer A Match Raw Interrupt +pub const TIMER_RIS_RTCRIS: u32 = 0x00000008; // GPTM RTC Raw Interrupt +pub const TIMER_RIS_CAERIS: u32 = 0x00000004; // GPTM Timer A Capture Mode Event + // Raw Interrupt +pub const TIMER_RIS_CAMRIS: u32 = 0x00000002; // GPTM Timer A Capture Mode Match + // Raw Interrupt +pub const TIMER_RIS_TATORIS: u32 = 0x00000001; // GPTM Timer A Time-Out Raw + // Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +pub const TIMER_MIS_WUEMIS: u32 = 0x00010000; // 32/64-Bit Wide GPTM Write Update + // Error Masked Interrupt Status +pub const TIMER_MIS_TBMMIS: u32 = 0x00000800; // GPTM Timer B Match Masked + // Interrupt +pub const TIMER_MIS_CBEMIS: u32 = 0x00000400; // GPTM Timer B Capture Mode Event + // Masked Interrupt +pub const TIMER_MIS_CBMMIS: u32 = 0x00000200; // GPTM Timer B Capture Mode Match + // Masked Interrupt +pub const TIMER_MIS_TBTOMIS: u32 = 0x00000100; // GPTM Timer B Time-Out Masked + // Interrupt +pub const TIMER_MIS_TAMMIS: u32 = 0x00000010; // GPTM Timer A Match Masked + // Interrupt +pub const TIMER_MIS_RTCMIS: u32 = 0x00000008; // GPTM RTC Masked Interrupt +pub const TIMER_MIS_CAEMIS: u32 = 0x00000004; // GPTM Timer A Capture Mode Event + // Masked Interrupt +pub const TIMER_MIS_CAMMIS: u32 = 0x00000002; // GPTM Timer A Capture Mode Match + // Masked Interrupt +pub const TIMER_MIS_TATOMIS: u32 = 0x00000001; // GPTM Timer A Time-Out Masked + // Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +pub const TIMER_ICR_WUECINT: u32 = 0x00010000; // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Clear +pub const TIMER_ICR_TBMCINT: u32 = 0x00000800; // GPTM Timer B Match Interrupt + // Clear +pub const TIMER_ICR_CBECINT: u32 = 0x00000400; // GPTM Timer B Capture Mode Event + // Interrupt Clear +pub const TIMER_ICR_CBMCINT: u32 = 0x00000200; // GPTM Timer B Capture Mode Match + // Interrupt Clear +pub const TIMER_ICR_TBTOCINT: u32 = 0x00000100; // GPTM Timer B Time-Out Interrupt + // Clear +pub const TIMER_ICR_TAMCINT: u32 = 0x00000010; // GPTM Timer A Match Interrupt + // Clear +pub const TIMER_ICR_RTCCINT: u32 = 0x00000008; // GPTM RTC Interrupt Clear +pub const TIMER_ICR_CAECINT: u32 = 0x00000004; // GPTM Timer A Capture Mode Event + // Interrupt Clear +pub const TIMER_ICR_CAMCINT: u32 = 0x00000002; // GPTM Timer A Capture Mode Match + // Interrupt Clear +pub const TIMER_ICR_TATOCINT: u32 = 0x00000001; // GPTM Timer A Time-Out Raw + // Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +pub const TIMER_TAILR_M: u32 = 0xFFFFFFFF; // GPTM Timer A Interval Load + // Register +pub const TIMER_TAILR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +pub const TIMER_TBILR_M: u32 = 0xFFFFFFFF; // GPTM Timer B Interval Load + // Register +pub const TIMER_TBILR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +pub const TIMER_TAMATCHR_TAMR_M: u32 = 0xFFFFFFFF; // GPTM Timer A Match Register +pub const TIMER_TAMATCHR_TAMR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +pub const TIMER_TBMATCHR_TBMR_M: u32 = 0xFFFFFFFF; // GPTM Timer B Match Register +pub const TIMER_TBMATCHR_TBMR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +pub const TIMER_TAPR_TAPSRH_M: u32 = 0x0000FF00; // GPTM Timer A Prescale High Byte +pub const TIMER_TAPR_TAPSR_M: u32 = 0x000000FF; // GPTM Timer A Prescale +pub const TIMER_TAPR_TAPSRH_S: u32 = 8; +pub const TIMER_TAPR_TAPSR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +pub const TIMER_TBPR_TBPSRH_M: u32 = 0x0000FF00; // GPTM Timer B Prescale High Byte +pub const TIMER_TBPR_TBPSR_M: u32 = 0x000000FF; // GPTM Timer B Prescale +pub const TIMER_TBPR_TBPSRH_S: u32 = 8; +pub const TIMER_TBPR_TBPSR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +pub const TIMER_TAPMR_TAPSMRH_M: u32 = 0x0000FF00; // GPTM Timer A Prescale Match High + // Byte +pub const TIMER_TAPMR_TAPSMR_M: u32 = 0x000000FF; // GPTM TimerA Prescale Match +pub const TIMER_TAPMR_TAPSMRH_S: u32 = 8; +pub const TIMER_TAPMR_TAPSMR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +pub const TIMER_TBPMR_TBPSMRH_M: u32 = 0x0000FF00; // GPTM Timer B Prescale Match High + // Byte +pub const TIMER_TBPMR_TBPSMR_M: u32 = 0x000000FF; // GPTM TimerB Prescale Match +pub const TIMER_TBPMR_TBPSMRH_S: u32 = 8; +pub const TIMER_TBPMR_TBPSMR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +pub const TIMER_TAR_M: u32 = 0xFFFFFFFF; // GPTM Timer A Register +pub const TIMER_TAR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +pub const TIMER_TBR_M: u32 = 0xFFFFFFFF; // GPTM Timer B Register +pub const TIMER_TBR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +pub const TIMER_TAV_M: u32 = 0xFFFFFFFF; // GPTM Timer A Value +pub const TIMER_TAV_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +pub const TIMER_TBV_M: u32 = 0xFFFFFFFF; // GPTM Timer B Value +pub const TIMER_TBV_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +pub const TIMER_RTCPD_RTCPD_M: u32 = 0x0000FFFF; // RTC Predivide Counter Value +pub const TIMER_RTCPD_RTCPD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +pub const TIMER_TAPS_PSS_M: u32 = 0x0000FFFF; // GPTM Timer A Prescaler Snapshot +pub const TIMER_TAPS_PSS_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +pub const TIMER_TBPS_PSS_M: u32 = 0x0000FFFF; // GPTM Timer A Prescaler Value +pub const TIMER_TBPS_PSS_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +pub const TIMER_TAPV_PSV_M: u32 = 0x0000FFFF; // GPTM Timer A Prescaler Value +pub const TIMER_TAPV_PSV_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +pub const TIMER_TBPV_PSV_M: u32 = 0x0000FFFF; // GPTM Timer B Prescaler Value +pub const TIMER_TBPV_PSV_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +pub const TIMER_PP_SIZE_M: u32 = 0x0000000F; // Count Size +pub const TIMER_PP_SIZE_16: u32 = 0x00000000; // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +pub const TIMER_PP_SIZE_32: u32 = 0x00000001; // Timer A and Timer B counters are + // 32 bits each with a 16-bit + // prescale counter +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ACTSS register. +// +//***************************************************************************** +pub const ADC_ACTSS_BUSY: u32 = 0x00010000; // ADC Busy +pub const ADC_ACTSS_ASEN3: u32 = 0x00000008; // ADC SS3 Enable +pub const ADC_ACTSS_ASEN2: u32 = 0x00000004; // ADC SS2 Enable +pub const ADC_ACTSS_ASEN1: u32 = 0x00000002; // ADC SS1 Enable +pub const ADC_ACTSS_ASEN0: u32 = 0x00000001; // ADC SS0 Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_RIS register. +// +//***************************************************************************** +pub const ADC_RIS_INRDC: u32 = 0x00010000; // Digital Comparator Raw Interrupt + // Status +pub const ADC_RIS_INR3: u32 = 0x00000008; // SS3 Raw Interrupt Status +pub const ADC_RIS_INR2: u32 = 0x00000004; // SS2 Raw Interrupt Status +pub const ADC_RIS_INR1: u32 = 0x00000002; // SS1 Raw Interrupt Status +pub const ADC_RIS_INR0: u32 = 0x00000001; // SS0 Raw Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_IM register. +// +//***************************************************************************** +pub const ADC_IM_DCONSS3: u32 = 0x00080000; // Digital Comparator Interrupt on + // SS3 +pub const ADC_IM_DCONSS2: u32 = 0x00040000; // Digital Comparator Interrupt on + // SS2 +pub const ADC_IM_DCONSS1: u32 = 0x00020000; // Digital Comparator Interrupt on + // SS1 +pub const ADC_IM_DCONSS0: u32 = 0x00010000; // Digital Comparator Interrupt on + // SS0 +pub const ADC_IM_MASK3: u32 = 0x00000008; // SS3 Interrupt Mask +pub const ADC_IM_MASK2: u32 = 0x00000004; // SS2 Interrupt Mask +pub const ADC_IM_MASK1: u32 = 0x00000002; // SS1 Interrupt Mask +pub const ADC_IM_MASK0: u32 = 0x00000001; // SS0 Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ISC register. +// +//***************************************************************************** +pub const ADC_ISC_DCINSS3: u32 = 0x00080000; // Digital Comparator Interrupt + // Status on SS3 +pub const ADC_ISC_DCINSS2: u32 = 0x00040000; // Digital Comparator Interrupt + // Status on SS2 +pub const ADC_ISC_DCINSS1: u32 = 0x00020000; // Digital Comparator Interrupt + // Status on SS1 +pub const ADC_ISC_DCINSS0: u32 = 0x00010000; // Digital Comparator Interrupt + // Status on SS0 +pub const ADC_ISC_IN3: u32 = 0x00000008; // SS3 Interrupt Status and Clear +pub const ADC_ISC_IN2: u32 = 0x00000004; // SS2 Interrupt Status and Clear +pub const ADC_ISC_IN1: u32 = 0x00000002; // SS1 Interrupt Status and Clear +pub const ADC_ISC_IN0: u32 = 0x00000001; // SS0 Interrupt Status and Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_OSTAT register. +// +//***************************************************************************** +pub const ADC_OSTAT_OV3: u32 = 0x00000008; // SS3 FIFO Overflow +pub const ADC_OSTAT_OV2: u32 = 0x00000004; // SS2 FIFO Overflow +pub const ADC_OSTAT_OV1: u32 = 0x00000002; // SS1 FIFO Overflow +pub const ADC_OSTAT_OV0: u32 = 0x00000001; // SS0 FIFO Overflow +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_EMUX register. +// +//***************************************************************************** +pub const ADC_EMUX_EM3_M: u32 = 0x0000F000; // SS3 Trigger Select +pub const ADC_EMUX_EM3_PROCESSOR: u32 = 0x00000000; // Processor (default) +pub const ADC_EMUX_EM3_COMP0: u32 = 0x00001000; // Analog Comparator 0 +pub const ADC_EMUX_EM3_COMP1: u32 = 0x00002000; // Analog Comparator 1 +pub const ADC_EMUX_EM3_EXTERNAL: u32 = 0x00004000; // External (GPIO Pins) +pub const ADC_EMUX_EM3_TIMER: u32 = 0x00005000; // Timer +pub const ADC_EMUX_EM3_PWM0: u32 = 0x00006000; // PWM generator 0 +pub const ADC_EMUX_EM3_PWM1: u32 = 0x00007000; // PWM generator 1 +pub const ADC_EMUX_EM3_PWM2: u32 = 0x00008000; // PWM generator 2 +pub const ADC_EMUX_EM3_PWM3: u32 = 0x00009000; // PWM generator 3 +pub const ADC_EMUX_EM3_ALWAYS: u32 = 0x0000F000; // Always (continuously sample) +pub const ADC_EMUX_EM2_M: u32 = 0x00000F00; // SS2 Trigger Select +pub const ADC_EMUX_EM2_PROCESSOR: u32 = 0x00000000; // Processor (default) +pub const ADC_EMUX_EM2_COMP0: u32 = 0x00000100; // Analog Comparator 0 +pub const ADC_EMUX_EM2_COMP1: u32 = 0x00000200; // Analog Comparator 1 +pub const ADC_EMUX_EM2_EXTERNAL: u32 = 0x00000400; // External (GPIO Pins) +pub const ADC_EMUX_EM2_TIMER: u32 = 0x00000500; // Timer +pub const ADC_EMUX_EM2_PWM0: u32 = 0x00000600; // PWM generator 0 +pub const ADC_EMUX_EM2_PWM1: u32 = 0x00000700; // PWM generator 1 +pub const ADC_EMUX_EM2_PWM2: u32 = 0x00000800; // PWM generator 2 +pub const ADC_EMUX_EM2_PWM3: u32 = 0x00000900; // PWM generator 3 +pub const ADC_EMUX_EM2_ALWAYS: u32 = 0x00000F00; // Always (continuously sample) +pub const ADC_EMUX_EM1_M: u32 = 0x000000F0; // SS1 Trigger Select +pub const ADC_EMUX_EM1_PROCESSOR: u32 = 0x00000000; // Processor (default) +pub const ADC_EMUX_EM1_COMP0: u32 = 0x00000010; // Analog Comparator 0 +pub const ADC_EMUX_EM1_COMP1: u32 = 0x00000020; // Analog Comparator 1 +pub const ADC_EMUX_EM1_EXTERNAL: u32 = 0x00000040; // External (GPIO Pins) +pub const ADC_EMUX_EM1_TIMER: u32 = 0x00000050; // Timer +pub const ADC_EMUX_EM1_PWM0: u32 = 0x00000060; // PWM generator 0 +pub const ADC_EMUX_EM1_PWM1: u32 = 0x00000070; // PWM generator 1 +pub const ADC_EMUX_EM1_PWM2: u32 = 0x00000080; // PWM generator 2 +pub const ADC_EMUX_EM1_PWM3: u32 = 0x00000090; // PWM generator 3 +pub const ADC_EMUX_EM1_ALWAYS: u32 = 0x000000F0; // Always (continuously sample) +pub const ADC_EMUX_EM0_M: u32 = 0x0000000F; // SS0 Trigger Select +pub const ADC_EMUX_EM0_PROCESSOR: u32 = 0x00000000; // Processor (default) +pub const ADC_EMUX_EM0_COMP0: u32 = 0x00000001; // Analog Comparator 0 +pub const ADC_EMUX_EM0_COMP1: u32 = 0x00000002; // Analog Comparator 1 +pub const ADC_EMUX_EM0_EXTERNAL: u32 = 0x00000004; // External (GPIO Pins) +pub const ADC_EMUX_EM0_TIMER: u32 = 0x00000005; // Timer +pub const ADC_EMUX_EM0_PWM0: u32 = 0x00000006; // PWM generator 0 +pub const ADC_EMUX_EM0_PWM1: u32 = 0x00000007; // PWM generator 1 +pub const ADC_EMUX_EM0_PWM2: u32 = 0x00000008; // PWM generator 2 +pub const ADC_EMUX_EM0_PWM3: u32 = 0x00000009; // PWM generator 3 +pub const ADC_EMUX_EM0_ALWAYS: u32 = 0x0000000F; // Always (continuously sample) +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_USTAT register. +// +//***************************************************************************** +pub const ADC_USTAT_UV3: u32 = 0x00000008; // SS3 FIFO Underflow +pub const ADC_USTAT_UV2: u32 = 0x00000004; // SS2 FIFO Underflow +pub const ADC_USTAT_UV1: u32 = 0x00000002; // SS1 FIFO Underflow +pub const ADC_USTAT_UV0: u32 = 0x00000001; // SS0 FIFO Underflow +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_TSSEL register. +// +//***************************************************************************** +pub const ADC_TSSEL_PS3_M: u32 = 0x30000000; // Generator 3 PWM Module Trigger + // Select +pub const ADC_TSSEL_PS3_0: u32 = 0x00000000; // Use Generator 3 (and its + // trigger) in PWM module 0 +pub const ADC_TSSEL_PS3_1: u32 = 0x10000000; // Use Generator 3 (and its + // trigger) in PWM module 1 +pub const ADC_TSSEL_PS2_M: u32 = 0x00300000; // Generator 2 PWM Module Trigger + // Select +pub const ADC_TSSEL_PS2_0: u32 = 0x00000000; // Use Generator 2 (and its + // trigger) in PWM module 0 +pub const ADC_TSSEL_PS2_1: u32 = 0x00100000; // Use Generator 2 (and its + // trigger) in PWM module 1 +pub const ADC_TSSEL_PS1_M: u32 = 0x00003000; // Generator 1 PWM Module Trigger + // Select +pub const ADC_TSSEL_PS1_0: u32 = 0x00000000; // Use Generator 1 (and its + // trigger) in PWM module 0 +pub const ADC_TSSEL_PS1_1: u32 = 0x00001000; // Use Generator 1 (and its + // trigger) in PWM module 1 +pub const ADC_TSSEL_PS0_M: u32 = 0x00000030; // Generator 0 PWM Module Trigger + // Select +pub const ADC_TSSEL_PS0_0: u32 = 0x00000000; // Use Generator 0 (and its + // trigger) in PWM module 0 +pub const ADC_TSSEL_PS0_1: u32 = 0x00000010; // Use Generator 0 (and its + // trigger) in PWM module 1 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSPRI register. +// +//***************************************************************************** +pub const ADC_SSPRI_SS3_M: u32 = 0x00003000; // SS3 Priority +pub const ADC_SSPRI_SS2_M: u32 = 0x00000300; // SS2 Priority +pub const ADC_SSPRI_SS1_M: u32 = 0x00000030; // SS1 Priority +pub const ADC_SSPRI_SS0_M: u32 = 0x00000003; // SS0 Priority +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SPC register. +// +//***************************************************************************** +pub const ADC_SPC_PHASE_M: u32 = 0x0000000F; // Phase Difference +pub const ADC_SPC_PHASE_0: u32 = 0x00000000; // ADC sample lags by 0.0 +pub const ADC_SPC_PHASE_22_5: u32 = 0x00000001; // ADC sample lags by 22.5 +pub const ADC_SPC_PHASE_45: u32 = 0x00000002; // ADC sample lags by 45.0 +pub const ADC_SPC_PHASE_67_5: u32 = 0x00000003; // ADC sample lags by 67.5 +pub const ADC_SPC_PHASE_90: u32 = 0x00000004; // ADC sample lags by 90.0 +pub const ADC_SPC_PHASE_112_5: u32 = 0x00000005; // ADC sample lags by 112.5 +pub const ADC_SPC_PHASE_135: u32 = 0x00000006; // ADC sample lags by 135.0 +pub const ADC_SPC_PHASE_157_5: u32 = 0x00000007; // ADC sample lags by 157.5 +pub const ADC_SPC_PHASE_180: u32 = 0x00000008; // ADC sample lags by 180.0 +pub const ADC_SPC_PHASE_202_5: u32 = 0x00000009; // ADC sample lags by 202.5 +pub const ADC_SPC_PHASE_225: u32 = 0x0000000A; // ADC sample lags by 225.0 +pub const ADC_SPC_PHASE_247_5: u32 = 0x0000000B; // ADC sample lags by 247.5 +pub const ADC_SPC_PHASE_270: u32 = 0x0000000C; // ADC sample lags by 270.0 +pub const ADC_SPC_PHASE_292_5: u32 = 0x0000000D; // ADC sample lags by 292.5 +pub const ADC_SPC_PHASE_315: u32 = 0x0000000E; // ADC sample lags by 315.0 +pub const ADC_SPC_PHASE_337_5: u32 = 0x0000000F; // ADC sample lags by 337.5 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PSSI register. +// +//***************************************************************************** +pub const ADC_PSSI_GSYNC: u32 = 0x80000000; // Global Synchronize +pub const ADC_PSSI_SYNCWAIT: u32 = 0x08000000; // Synchronize Wait +pub const ADC_PSSI_SS3: u32 = 0x00000008; // SS3 Initiate +pub const ADC_PSSI_SS2: u32 = 0x00000004; // SS2 Initiate +pub const ADC_PSSI_SS1: u32 = 0x00000002; // SS1 Initiate +pub const ADC_PSSI_SS0: u32 = 0x00000001; // SS0 Initiate +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SAC register. +// +//***************************************************************************** +pub const ADC_SAC_AVG_M: u32 = 0x00000007; // Hardware Averaging Control +pub const ADC_SAC_AVG_OFF: u32 = 0x00000000; // No hardware oversampling +pub const ADC_SAC_AVG_2X: u32 = 0x00000001; // 2x hardware oversampling +pub const ADC_SAC_AVG_4X: u32 = 0x00000002; // 4x hardware oversampling +pub const ADC_SAC_AVG_8X: u32 = 0x00000003; // 8x hardware oversampling +pub const ADC_SAC_AVG_16X: u32 = 0x00000004; // 16x hardware oversampling +pub const ADC_SAC_AVG_32X: u32 = 0x00000005; // 32x hardware oversampling +pub const ADC_SAC_AVG_64X: u32 = 0x00000006; // 64x hardware oversampling +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCISC register. +// +//***************************************************************************** +pub const ADC_DCISC_DCINT7: u32 = 0x00000080; // Digital Comparator 7 Interrupt + // Status and Clear +pub const ADC_DCISC_DCINT6: u32 = 0x00000040; // Digital Comparator 6 Interrupt + // Status and Clear +pub const ADC_DCISC_DCINT5: u32 = 0x00000020; // Digital Comparator 5 Interrupt + // Status and Clear +pub const ADC_DCISC_DCINT4: u32 = 0x00000010; // Digital Comparator 4 Interrupt + // Status and Clear +pub const ADC_DCISC_DCINT3: u32 = 0x00000008; // Digital Comparator 3 Interrupt + // Status and Clear +pub const ADC_DCISC_DCINT2: u32 = 0x00000004; // Digital Comparator 2 Interrupt + // Status and Clear +pub const ADC_DCISC_DCINT1: u32 = 0x00000002; // Digital Comparator 1 Interrupt + // Status and Clear +pub const ADC_DCISC_DCINT0: u32 = 0x00000001; // Digital Comparator 0 Interrupt + // Status and Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CTL register. +// +//***************************************************************************** +pub const ADC_CTL_DITHER: u32 = 0x00000040; // Dither Mode Enable +pub const ADC_CTL_VREF_M: u32 = 0x00000001; // Voltage Reference Select +pub const ADC_CTL_VREF_INTERNAL: u32 = 0x00000000; // VDDA and GNDA are the voltage + // references +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX0 register. +// +//***************************************************************************** +pub const ADC_SSMUX0_MUX7_M: u32 = 0xF0000000; // 8th Sample Input Select +pub const ADC_SSMUX0_MUX6_M: u32 = 0x0F000000; // 7th Sample Input Select +pub const ADC_SSMUX0_MUX5_M: u32 = 0x00F00000; // 6th Sample Input Select +pub const ADC_SSMUX0_MUX4_M: u32 = 0x000F0000; // 5th Sample Input Select +pub const ADC_SSMUX0_MUX3_M: u32 = 0x0000F000; // 4th Sample Input Select +pub const ADC_SSMUX0_MUX2_M: u32 = 0x00000F00; // 3rd Sample Input Select +pub const ADC_SSMUX0_MUX1_M: u32 = 0x000000F0; // 2nd Sample Input Select +pub const ADC_SSMUX0_MUX0_M: u32 = 0x0000000F; // 1st Sample Input Select +pub const ADC_SSMUX0_MUX7_S: u32 = 28; +pub const ADC_SSMUX0_MUX6_S: u32 = 24; +pub const ADC_SSMUX0_MUX5_S: u32 = 20; +pub const ADC_SSMUX0_MUX4_S: u32 = 16; +pub const ADC_SSMUX0_MUX3_S: u32 = 12; +pub const ADC_SSMUX0_MUX2_S: u32 = 8; +pub const ADC_SSMUX0_MUX1_S: u32 = 4; +pub const ADC_SSMUX0_MUX0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL0 register. +// +//***************************************************************************** +pub const ADC_SSCTL0_TS7: u32 = 0x80000000; // 8th Sample Temp Sensor Select +pub const ADC_SSCTL0_IE7: u32 = 0x40000000; // 8th Sample Interrupt Enable +pub const ADC_SSCTL0_END7: u32 = 0x20000000; // 8th Sample is End of Sequence +pub const ADC_SSCTL0_D7: u32 = 0x10000000; // 8th Sample Differential Input + // Select +pub const ADC_SSCTL0_TS6: u32 = 0x08000000; // 7th Sample Temp Sensor Select +pub const ADC_SSCTL0_IE6: u32 = 0x04000000; // 7th Sample Interrupt Enable +pub const ADC_SSCTL0_END6: u32 = 0x02000000; // 7th Sample is End of Sequence +pub const ADC_SSCTL0_D6: u32 = 0x01000000; // 7th Sample Differential Input + // Select +pub const ADC_SSCTL0_TS5: u32 = 0x00800000; // 6th Sample Temp Sensor Select +pub const ADC_SSCTL0_IE5: u32 = 0x00400000; // 6th Sample Interrupt Enable +pub const ADC_SSCTL0_END5: u32 = 0x00200000; // 6th Sample is End of Sequence +pub const ADC_SSCTL0_D5: u32 = 0x00100000; // 6th Sample Differential Input + // Select +pub const ADC_SSCTL0_TS4: u32 = 0x00080000; // 5th Sample Temp Sensor Select +pub const ADC_SSCTL0_IE4: u32 = 0x00040000; // 5th Sample Interrupt Enable +pub const ADC_SSCTL0_END4: u32 = 0x00020000; // 5th Sample is End of Sequence +pub const ADC_SSCTL0_D4: u32 = 0x00010000; // 5th Sample Differential Input + // Select +pub const ADC_SSCTL0_TS3: u32 = 0x00008000; // 4th Sample Temp Sensor Select +pub const ADC_SSCTL0_IE3: u32 = 0x00004000; // 4th Sample Interrupt Enable +pub const ADC_SSCTL0_END3: u32 = 0x00002000; // 4th Sample is End of Sequence +pub const ADC_SSCTL0_D3: u32 = 0x00001000; // 4th Sample Differential Input + // Select +pub const ADC_SSCTL0_TS2: u32 = 0x00000800; // 3rd Sample Temp Sensor Select +pub const ADC_SSCTL0_IE2: u32 = 0x00000400; // 3rd Sample Interrupt Enable +pub const ADC_SSCTL0_END2: u32 = 0x00000200; // 3rd Sample is End of Sequence +pub const ADC_SSCTL0_D2: u32 = 0x00000100; // 3rd Sample Differential Input + // Select +pub const ADC_SSCTL0_TS1: u32 = 0x00000080; // 2nd Sample Temp Sensor Select +pub const ADC_SSCTL0_IE1: u32 = 0x00000040; // 2nd Sample Interrupt Enable +pub const ADC_SSCTL0_END1: u32 = 0x00000020; // 2nd Sample is End of Sequence +pub const ADC_SSCTL0_D1: u32 = 0x00000010; // 2nd Sample Differential Input + // Select +pub const ADC_SSCTL0_TS0: u32 = 0x00000008; // 1st Sample Temp Sensor Select +pub const ADC_SSCTL0_IE0: u32 = 0x00000004; // 1st Sample Interrupt Enable +pub const ADC_SSCTL0_END0: u32 = 0x00000002; // 1st Sample is End of Sequence +pub const ADC_SSCTL0_D0: u32 = 0x00000001; // 1st Sample Differential Input + // Select +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. +// +//***************************************************************************** +pub const ADC_SSFIFO0_DATA_M: u32 = 0x00000FFF; // Conversion Result Data +pub const ADC_SSFIFO0_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. +// +//***************************************************************************** +pub const ADC_SSFSTAT0_FULL: u32 = 0x00001000; // FIFO Full +pub const ADC_SSFSTAT0_EMPTY: u32 = 0x00000100; // FIFO Empty +pub const ADC_SSFSTAT0_HPTR_M: u32 = 0x000000F0; // FIFO Head Pointer +pub const ADC_SSFSTAT0_TPTR_M: u32 = 0x0000000F; // FIFO Tail Pointer +pub const ADC_SSFSTAT0_HPTR_S: u32 = 4; +pub const ADC_SSFSTAT0_TPTR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP0 register. +// +//***************************************************************************** +pub const ADC_SSOP0_S7DCOP: u32 = 0x10000000; // Sample 7 Digital Comparator + // Operation +pub const ADC_SSOP0_S6DCOP: u32 = 0x01000000; // Sample 6 Digital Comparator + // Operation +pub const ADC_SSOP0_S5DCOP: u32 = 0x00100000; // Sample 5 Digital Comparator + // Operation +pub const ADC_SSOP0_S4DCOP: u32 = 0x00010000; // Sample 4 Digital Comparator + // Operation +pub const ADC_SSOP0_S3DCOP: u32 = 0x00001000; // Sample 3 Digital Comparator + // Operation +pub const ADC_SSOP0_S2DCOP: u32 = 0x00000100; // Sample 2 Digital Comparator + // Operation +pub const ADC_SSOP0_S1DCOP: u32 = 0x00000010; // Sample 1 Digital Comparator + // Operation +pub const ADC_SSOP0_S0DCOP: u32 = 0x00000001; // Sample 0 Digital Comparator + // Operation +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC0 register. +// +//***************************************************************************** +pub const ADC_SSDC0_S7DCSEL_M: u32 = 0xF0000000; // Sample 7 Digital Comparator + // Select +pub const ADC_SSDC0_S6DCSEL_M: u32 = 0x0F000000; // Sample 6 Digital Comparator + // Select +pub const ADC_SSDC0_S5DCSEL_M: u32 = 0x00F00000; // Sample 5 Digital Comparator + // Select +pub const ADC_SSDC0_S4DCSEL_M: u32 = 0x000F0000; // Sample 4 Digital Comparator + // Select +pub const ADC_SSDC0_S3DCSEL_M: u32 = 0x0000F000; // Sample 3 Digital Comparator + // Select +pub const ADC_SSDC0_S2DCSEL_M: u32 = 0x00000F00; // Sample 2 Digital Comparator + // Select +pub const ADC_SSDC0_S1DCSEL_M: u32 = 0x000000F0; // Sample 1 Digital Comparator + // Select +pub const ADC_SSDC0_S0DCSEL_M: u32 = 0x0000000F; // Sample 0 Digital Comparator + // Select +pub const ADC_SSDC0_S6DCSEL_S: u32 = 24; +pub const ADC_SSDC0_S5DCSEL_S: u32 = 20; +pub const ADC_SSDC0_S4DCSEL_S: u32 = 16; +pub const ADC_SSDC0_S3DCSEL_S: u32 = 12; +pub const ADC_SSDC0_S2DCSEL_S: u32 = 8; +pub const ADC_SSDC0_S1DCSEL_S: u32 = 4; +pub const ADC_SSDC0_S0DCSEL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX1 register. +// +//***************************************************************************** +pub const ADC_SSMUX1_MUX3_M: u32 = 0x0000F000; // 4th Sample Input Select +pub const ADC_SSMUX1_MUX2_M: u32 = 0x00000F00; // 3rd Sample Input Select +pub const ADC_SSMUX1_MUX1_M: u32 = 0x000000F0; // 2nd Sample Input Select +pub const ADC_SSMUX1_MUX0_M: u32 = 0x0000000F; // 1st Sample Input Select +pub const ADC_SSMUX1_MUX3_S: u32 = 12; +pub const ADC_SSMUX1_MUX2_S: u32 = 8; +pub const ADC_SSMUX1_MUX1_S: u32 = 4; +pub const ADC_SSMUX1_MUX0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL1 register. +// +//***************************************************************************** +pub const ADC_SSCTL1_TS3: u32 = 0x00008000; // 4th Sample Temp Sensor Select +pub const ADC_SSCTL1_IE3: u32 = 0x00004000; // 4th Sample Interrupt Enable +pub const ADC_SSCTL1_END3: u32 = 0x00002000; // 4th Sample is End of Sequence +pub const ADC_SSCTL1_D3: u32 = 0x00001000; // 4th Sample Differential Input + // Select +pub const ADC_SSCTL1_TS2: u32 = 0x00000800; // 3rd Sample Temp Sensor Select +pub const ADC_SSCTL1_IE2: u32 = 0x00000400; // 3rd Sample Interrupt Enable +pub const ADC_SSCTL1_END2: u32 = 0x00000200; // 3rd Sample is End of Sequence +pub const ADC_SSCTL1_D2: u32 = 0x00000100; // 3rd Sample Differential Input + // Select +pub const ADC_SSCTL1_TS1: u32 = 0x00000080; // 2nd Sample Temp Sensor Select +pub const ADC_SSCTL1_IE1: u32 = 0x00000040; // 2nd Sample Interrupt Enable +pub const ADC_SSCTL1_END1: u32 = 0x00000020; // 2nd Sample is End of Sequence +pub const ADC_SSCTL1_D1: u32 = 0x00000010; // 2nd Sample Differential Input + // Select +pub const ADC_SSCTL1_TS0: u32 = 0x00000008; // 1st Sample Temp Sensor Select +pub const ADC_SSCTL1_IE0: u32 = 0x00000004; // 1st Sample Interrupt Enable +pub const ADC_SSCTL1_END0: u32 = 0x00000002; // 1st Sample is End of Sequence +pub const ADC_SSCTL1_D0: u32 = 0x00000001; // 1st Sample Differential Input + // Select +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. +// +//***************************************************************************** +pub const ADC_SSFIFO1_DATA_M: u32 = 0x00000FFF; // Conversion Result Data +pub const ADC_SSFIFO1_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. +// +//***************************************************************************** +pub const ADC_SSFSTAT1_FULL: u32 = 0x00001000; // FIFO Full +pub const ADC_SSFSTAT1_EMPTY: u32 = 0x00000100; // FIFO Empty +pub const ADC_SSFSTAT1_HPTR_M: u32 = 0x000000F0; // FIFO Head Pointer +pub const ADC_SSFSTAT1_TPTR_M: u32 = 0x0000000F; // FIFO Tail Pointer +pub const ADC_SSFSTAT1_HPTR_S: u32 = 4; +pub const ADC_SSFSTAT1_TPTR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP1 register. +// +//***************************************************************************** +pub const ADC_SSOP1_S3DCOP: u32 = 0x00001000; // Sample 3 Digital Comparator + // Operation +pub const ADC_SSOP1_S2DCOP: u32 = 0x00000100; // Sample 2 Digital Comparator + // Operation +pub const ADC_SSOP1_S1DCOP: u32 = 0x00000010; // Sample 1 Digital Comparator + // Operation +pub const ADC_SSOP1_S0DCOP: u32 = 0x00000001; // Sample 0 Digital Comparator + // Operation +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC1 register. +// +//***************************************************************************** +pub const ADC_SSDC1_S3DCSEL_M: u32 = 0x0000F000; // Sample 3 Digital Comparator + // Select +pub const ADC_SSDC1_S2DCSEL_M: u32 = 0x00000F00; // Sample 2 Digital Comparator + // Select +pub const ADC_SSDC1_S1DCSEL_M: u32 = 0x000000F0; // Sample 1 Digital Comparator + // Select +pub const ADC_SSDC1_S0DCSEL_M: u32 = 0x0000000F; // Sample 0 Digital Comparator + // Select +pub const ADC_SSDC1_S2DCSEL_S: u32 = 8; +pub const ADC_SSDC1_S1DCSEL_S: u32 = 4; +pub const ADC_SSDC1_S0DCSEL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX2 register. +// +//***************************************************************************** +pub const ADC_SSMUX2_MUX3_M: u32 = 0x0000F000; // 4th Sample Input Select +pub const ADC_SSMUX2_MUX2_M: u32 = 0x00000F00; // 3rd Sample Input Select +pub const ADC_SSMUX2_MUX1_M: u32 = 0x000000F0; // 2nd Sample Input Select +pub const ADC_SSMUX2_MUX0_M: u32 = 0x0000000F; // 1st Sample Input Select +pub const ADC_SSMUX2_MUX3_S: u32 = 12; +pub const ADC_SSMUX2_MUX2_S: u32 = 8; +pub const ADC_SSMUX2_MUX1_S: u32 = 4; +pub const ADC_SSMUX2_MUX0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL2 register. +// +//***************************************************************************** +pub const ADC_SSCTL2_TS3: u32 = 0x00008000; // 4th Sample Temp Sensor Select +pub const ADC_SSCTL2_IE3: u32 = 0x00004000; // 4th Sample Interrupt Enable +pub const ADC_SSCTL2_END3: u32 = 0x00002000; // 4th Sample is End of Sequence +pub const ADC_SSCTL2_D3: u32 = 0x00001000; // 4th Sample Differential Input + // Select +pub const ADC_SSCTL2_TS2: u32 = 0x00000800; // 3rd Sample Temp Sensor Select +pub const ADC_SSCTL2_IE2: u32 = 0x00000400; // 3rd Sample Interrupt Enable +pub const ADC_SSCTL2_END2: u32 = 0x00000200; // 3rd Sample is End of Sequence +pub const ADC_SSCTL2_D2: u32 = 0x00000100; // 3rd Sample Differential Input + // Select +pub const ADC_SSCTL2_TS1: u32 = 0x00000080; // 2nd Sample Temp Sensor Select +pub const ADC_SSCTL2_IE1: u32 = 0x00000040; // 2nd Sample Interrupt Enable +pub const ADC_SSCTL2_END1: u32 = 0x00000020; // 2nd Sample is End of Sequence +pub const ADC_SSCTL2_D1: u32 = 0x00000010; // 2nd Sample Differential Input + // Select +pub const ADC_SSCTL2_TS0: u32 = 0x00000008; // 1st Sample Temp Sensor Select +pub const ADC_SSCTL2_IE0: u32 = 0x00000004; // 1st Sample Interrupt Enable +pub const ADC_SSCTL2_END0: u32 = 0x00000002; // 1st Sample is End of Sequence +pub const ADC_SSCTL2_D0: u32 = 0x00000001; // 1st Sample Differential Input + // Select +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. +// +//***************************************************************************** +pub const ADC_SSFIFO2_DATA_M: u32 = 0x00000FFF; // Conversion Result Data +pub const ADC_SSFIFO2_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. +// +//***************************************************************************** +pub const ADC_SSFSTAT2_FULL: u32 = 0x00001000; // FIFO Full +pub const ADC_SSFSTAT2_EMPTY: u32 = 0x00000100; // FIFO Empty +pub const ADC_SSFSTAT2_HPTR_M: u32 = 0x000000F0; // FIFO Head Pointer +pub const ADC_SSFSTAT2_TPTR_M: u32 = 0x0000000F; // FIFO Tail Pointer +pub const ADC_SSFSTAT2_HPTR_S: u32 = 4; +pub const ADC_SSFSTAT2_TPTR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP2 register. +// +//***************************************************************************** +pub const ADC_SSOP2_S3DCOP: u32 = 0x00001000; // Sample 3 Digital Comparator + // Operation +pub const ADC_SSOP2_S2DCOP: u32 = 0x00000100; // Sample 2 Digital Comparator + // Operation +pub const ADC_SSOP2_S1DCOP: u32 = 0x00000010; // Sample 1 Digital Comparator + // Operation +pub const ADC_SSOP2_S0DCOP: u32 = 0x00000001; // Sample 0 Digital Comparator + // Operation +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC2 register. +// +//***************************************************************************** +pub const ADC_SSDC2_S3DCSEL_M: u32 = 0x0000F000; // Sample 3 Digital Comparator + // Select +pub const ADC_SSDC2_S2DCSEL_M: u32 = 0x00000F00; // Sample 2 Digital Comparator + // Select +pub const ADC_SSDC2_S1DCSEL_M: u32 = 0x000000F0; // Sample 1 Digital Comparator + // Select +pub const ADC_SSDC2_S0DCSEL_M: u32 = 0x0000000F; // Sample 0 Digital Comparator + // Select +pub const ADC_SSDC2_S2DCSEL_S: u32 = 8; +pub const ADC_SSDC2_S1DCSEL_S: u32 = 4; +pub const ADC_SSDC2_S0DCSEL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX3 register. +// +//***************************************************************************** +pub const ADC_SSMUX3_MUX0_M: u32 = 0x0000000F; // 1st Sample Input Select +pub const ADC_SSMUX3_MUX0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL3 register. +// +//***************************************************************************** +pub const ADC_SSCTL3_TS0: u32 = 0x00000008; // 1st Sample Temp Sensor Select +pub const ADC_SSCTL3_IE0: u32 = 0x00000004; // Sample Interrupt Enable +pub const ADC_SSCTL3_END0: u32 = 0x00000002; // End of Sequence +pub const ADC_SSCTL3_D0: u32 = 0x00000001; // Sample Differential Input Select +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. +// +//***************************************************************************** +pub const ADC_SSFIFO3_DATA_M: u32 = 0x00000FFF; // Conversion Result Data +pub const ADC_SSFIFO3_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. +// +//***************************************************************************** +pub const ADC_SSFSTAT3_FULL: u32 = 0x00001000; // FIFO Full +pub const ADC_SSFSTAT3_EMPTY: u32 = 0x00000100; // FIFO Empty +pub const ADC_SSFSTAT3_HPTR_M: u32 = 0x000000F0; // FIFO Head Pointer +pub const ADC_SSFSTAT3_TPTR_M: u32 = 0x0000000F; // FIFO Tail Pointer +pub const ADC_SSFSTAT3_HPTR_S: u32 = 4; +pub const ADC_SSFSTAT3_TPTR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP3 register. +// +//***************************************************************************** +pub const ADC_SSOP3_S0DCOP: u32 = 0x00000001; // Sample 0 Digital Comparator + // Operation +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC3 register. +// +//***************************************************************************** +pub const ADC_SSDC3_S0DCSEL_M: u32 = 0x0000000F; // Sample 0 Digital Comparator + // Select +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCRIC register. +// +//***************************************************************************** +pub const ADC_DCRIC_DCTRIG7: u32 = 0x00800000; // Digital Comparator Trigger 7 +pub const ADC_DCRIC_DCTRIG6: u32 = 0x00400000; // Digital Comparator Trigger 6 +pub const ADC_DCRIC_DCTRIG5: u32 = 0x00200000; // Digital Comparator Trigger 5 +pub const ADC_DCRIC_DCTRIG4: u32 = 0x00100000; // Digital Comparator Trigger 4 +pub const ADC_DCRIC_DCTRIG3: u32 = 0x00080000; // Digital Comparator Trigger 3 +pub const ADC_DCRIC_DCTRIG2: u32 = 0x00040000; // Digital Comparator Trigger 2 +pub const ADC_DCRIC_DCTRIG1: u32 = 0x00020000; // Digital Comparator Trigger 1 +pub const ADC_DCRIC_DCTRIG0: u32 = 0x00010000; // Digital Comparator Trigger 0 +pub const ADC_DCRIC_DCINT7: u32 = 0x00000080; // Digital Comparator Interrupt 7 +pub const ADC_DCRIC_DCINT6: u32 = 0x00000040; // Digital Comparator Interrupt 6 +pub const ADC_DCRIC_DCINT5: u32 = 0x00000020; // Digital Comparator Interrupt 5 +pub const ADC_DCRIC_DCINT4: u32 = 0x00000010; // Digital Comparator Interrupt 4 +pub const ADC_DCRIC_DCINT3: u32 = 0x00000008; // Digital Comparator Interrupt 3 +pub const ADC_DCRIC_DCINT2: u32 = 0x00000004; // Digital Comparator Interrupt 2 +pub const ADC_DCRIC_DCINT1: u32 = 0x00000002; // Digital Comparator Interrupt 1 +pub const ADC_DCRIC_DCINT0: u32 = 0x00000001; // Digital Comparator Interrupt 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL0 register. +// +//***************************************************************************** +pub const ADC_DCCTL0_CTE: u32 = 0x00001000; // Comparison Trigger Enable +pub const ADC_DCCTL0_CTC_M: u32 = 0x00000C00; // Comparison Trigger Condition +pub const ADC_DCCTL0_CTC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL0_CTC_MID: u32 = 0x00000400; // Mid Band +pub const ADC_DCCTL0_CTC_HIGH: u32 = 0x00000C00; // High Band +pub const ADC_DCCTL0_CTM_M: u32 = 0x00000300; // Comparison Trigger Mode +pub const ADC_DCCTL0_CTM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL0_CTM_ONCE: u32 = 0x00000100; // Once +pub const ADC_DCCTL0_CTM_HALWAYS: u32 = 0x00000200; // Hysteresis Always +pub const ADC_DCCTL0_CTM_HONCE: u32 = 0x00000300; // Hysteresis Once +pub const ADC_DCCTL0_CIE: u32 = 0x00000010; // Comparison Interrupt Enable +pub const ADC_DCCTL0_CIC_M: u32 = 0x0000000C; // Comparison Interrupt Condition +pub const ADC_DCCTL0_CIC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL0_CIC_MID: u32 = 0x00000004; // Mid Band +pub const ADC_DCCTL0_CIC_HIGH: u32 = 0x0000000C; // High Band +pub const ADC_DCCTL0_CIM_M: u32 = 0x00000003; // Comparison Interrupt Mode +pub const ADC_DCCTL0_CIM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL0_CIM_ONCE: u32 = 0x00000001; // Once +pub const ADC_DCCTL0_CIM_HALWAYS: u32 = 0x00000002; // Hysteresis Always +pub const ADC_DCCTL0_CIM_HONCE: u32 = 0x00000003; // Hysteresis Once +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL1 register. +// +//***************************************************************************** +pub const ADC_DCCTL1_CTE: u32 = 0x00001000; // Comparison Trigger Enable +pub const ADC_DCCTL1_CTC_M: u32 = 0x00000C00; // Comparison Trigger Condition +pub const ADC_DCCTL1_CTC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL1_CTC_MID: u32 = 0x00000400; // Mid Band +pub const ADC_DCCTL1_CTC_HIGH: u32 = 0x00000C00; // High Band +pub const ADC_DCCTL1_CTM_M: u32 = 0x00000300; // Comparison Trigger Mode +pub const ADC_DCCTL1_CTM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL1_CTM_ONCE: u32 = 0x00000100; // Once +pub const ADC_DCCTL1_CTM_HALWAYS: u32 = 0x00000200; // Hysteresis Always +pub const ADC_DCCTL1_CTM_HONCE: u32 = 0x00000300; // Hysteresis Once +pub const ADC_DCCTL1_CIE: u32 = 0x00000010; // Comparison Interrupt Enable +pub const ADC_DCCTL1_CIC_M: u32 = 0x0000000C; // Comparison Interrupt Condition +pub const ADC_DCCTL1_CIC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL1_CIC_MID: u32 = 0x00000004; // Mid Band +pub const ADC_DCCTL1_CIC_HIGH: u32 = 0x0000000C; // High Band +pub const ADC_DCCTL1_CIM_M: u32 = 0x00000003; // Comparison Interrupt Mode +pub const ADC_DCCTL1_CIM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL1_CIM_ONCE: u32 = 0x00000001; // Once +pub const ADC_DCCTL1_CIM_HALWAYS: u32 = 0x00000002; // Hysteresis Always +pub const ADC_DCCTL1_CIM_HONCE: u32 = 0x00000003; // Hysteresis Once +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL2 register. +// +//***************************************************************************** +pub const ADC_DCCTL2_CTE: u32 = 0x00001000; // Comparison Trigger Enable +pub const ADC_DCCTL2_CTC_M: u32 = 0x00000C00; // Comparison Trigger Condition +pub const ADC_DCCTL2_CTC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL2_CTC_MID: u32 = 0x00000400; // Mid Band +pub const ADC_DCCTL2_CTC_HIGH: u32 = 0x00000C00; // High Band +pub const ADC_DCCTL2_CTM_M: u32 = 0x00000300; // Comparison Trigger Mode +pub const ADC_DCCTL2_CTM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL2_CTM_ONCE: u32 = 0x00000100; // Once +pub const ADC_DCCTL2_CTM_HALWAYS: u32 = 0x00000200; // Hysteresis Always +pub const ADC_DCCTL2_CTM_HONCE: u32 = 0x00000300; // Hysteresis Once +pub const ADC_DCCTL2_CIE: u32 = 0x00000010; // Comparison Interrupt Enable +pub const ADC_DCCTL2_CIC_M: u32 = 0x0000000C; // Comparison Interrupt Condition +pub const ADC_DCCTL2_CIC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL2_CIC_MID: u32 = 0x00000004; // Mid Band +pub const ADC_DCCTL2_CIC_HIGH: u32 = 0x0000000C; // High Band +pub const ADC_DCCTL2_CIM_M: u32 = 0x00000003; // Comparison Interrupt Mode +pub const ADC_DCCTL2_CIM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL2_CIM_ONCE: u32 = 0x00000001; // Once +pub const ADC_DCCTL2_CIM_HALWAYS: u32 = 0x00000002; // Hysteresis Always +pub const ADC_DCCTL2_CIM_HONCE: u32 = 0x00000003; // Hysteresis Once +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL3 register. +// +//***************************************************************************** +pub const ADC_DCCTL3_CTE: u32 = 0x00001000; // Comparison Trigger Enable +pub const ADC_DCCTL3_CTC_M: u32 = 0x00000C00; // Comparison Trigger Condition +pub const ADC_DCCTL3_CTC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL3_CTC_MID: u32 = 0x00000400; // Mid Band +pub const ADC_DCCTL3_CTC_HIGH: u32 = 0x00000C00; // High Band +pub const ADC_DCCTL3_CTM_M: u32 = 0x00000300; // Comparison Trigger Mode +pub const ADC_DCCTL3_CTM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL3_CTM_ONCE: u32 = 0x00000100; // Once +pub const ADC_DCCTL3_CTM_HALWAYS: u32 = 0x00000200; // Hysteresis Always +pub const ADC_DCCTL3_CTM_HONCE: u32 = 0x00000300; // Hysteresis Once +pub const ADC_DCCTL3_CIE: u32 = 0x00000010; // Comparison Interrupt Enable +pub const ADC_DCCTL3_CIC_M: u32 = 0x0000000C; // Comparison Interrupt Condition +pub const ADC_DCCTL3_CIC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL3_CIC_MID: u32 = 0x00000004; // Mid Band +pub const ADC_DCCTL3_CIC_HIGH: u32 = 0x0000000C; // High Band +pub const ADC_DCCTL3_CIM_M: u32 = 0x00000003; // Comparison Interrupt Mode +pub const ADC_DCCTL3_CIM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL3_CIM_ONCE: u32 = 0x00000001; // Once +pub const ADC_DCCTL3_CIM_HALWAYS: u32 = 0x00000002; // Hysteresis Always +pub const ADC_DCCTL3_CIM_HONCE: u32 = 0x00000003; // Hysteresis Once +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL4 register. +// +//***************************************************************************** +pub const ADC_DCCTL4_CTE: u32 = 0x00001000; // Comparison Trigger Enable +pub const ADC_DCCTL4_CTC_M: u32 = 0x00000C00; // Comparison Trigger Condition +pub const ADC_DCCTL4_CTC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL4_CTC_MID: u32 = 0x00000400; // Mid Band +pub const ADC_DCCTL4_CTC_HIGH: u32 = 0x00000C00; // High Band +pub const ADC_DCCTL4_CTM_M: u32 = 0x00000300; // Comparison Trigger Mode +pub const ADC_DCCTL4_CTM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL4_CTM_ONCE: u32 = 0x00000100; // Once +pub const ADC_DCCTL4_CTM_HALWAYS: u32 = 0x00000200; // Hysteresis Always +pub const ADC_DCCTL4_CTM_HONCE: u32 = 0x00000300; // Hysteresis Once +pub const ADC_DCCTL4_CIE: u32 = 0x00000010; // Comparison Interrupt Enable +pub const ADC_DCCTL4_CIC_M: u32 = 0x0000000C; // Comparison Interrupt Condition +pub const ADC_DCCTL4_CIC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL4_CIC_MID: u32 = 0x00000004; // Mid Band +pub const ADC_DCCTL4_CIC_HIGH: u32 = 0x0000000C; // High Band +pub const ADC_DCCTL4_CIM_M: u32 = 0x00000003; // Comparison Interrupt Mode +pub const ADC_DCCTL4_CIM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL4_CIM_ONCE: u32 = 0x00000001; // Once +pub const ADC_DCCTL4_CIM_HALWAYS: u32 = 0x00000002; // Hysteresis Always +pub const ADC_DCCTL4_CIM_HONCE: u32 = 0x00000003; // Hysteresis Once +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL5 register. +// +//***************************************************************************** +pub const ADC_DCCTL5_CTE: u32 = 0x00001000; // Comparison Trigger Enable +pub const ADC_DCCTL5_CTC_M: u32 = 0x00000C00; // Comparison Trigger Condition +pub const ADC_DCCTL5_CTC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL5_CTC_MID: u32 = 0x00000400; // Mid Band +pub const ADC_DCCTL5_CTC_HIGH: u32 = 0x00000C00; // High Band +pub const ADC_DCCTL5_CTM_M: u32 = 0x00000300; // Comparison Trigger Mode +pub const ADC_DCCTL5_CTM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL5_CTM_ONCE: u32 = 0x00000100; // Once +pub const ADC_DCCTL5_CTM_HALWAYS: u32 = 0x00000200; // Hysteresis Always +pub const ADC_DCCTL5_CTM_HONCE: u32 = 0x00000300; // Hysteresis Once +pub const ADC_DCCTL5_CIE: u32 = 0x00000010; // Comparison Interrupt Enable +pub const ADC_DCCTL5_CIC_M: u32 = 0x0000000C; // Comparison Interrupt Condition +pub const ADC_DCCTL5_CIC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL5_CIC_MID: u32 = 0x00000004; // Mid Band +pub const ADC_DCCTL5_CIC_HIGH: u32 = 0x0000000C; // High Band +pub const ADC_DCCTL5_CIM_M: u32 = 0x00000003; // Comparison Interrupt Mode +pub const ADC_DCCTL5_CIM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL5_CIM_ONCE: u32 = 0x00000001; // Once +pub const ADC_DCCTL5_CIM_HALWAYS: u32 = 0x00000002; // Hysteresis Always +pub const ADC_DCCTL5_CIM_HONCE: u32 = 0x00000003; // Hysteresis Once +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL6 register. +// +//***************************************************************************** +pub const ADC_DCCTL6_CTE: u32 = 0x00001000; // Comparison Trigger Enable +pub const ADC_DCCTL6_CTC_M: u32 = 0x00000C00; // Comparison Trigger Condition +pub const ADC_DCCTL6_CTC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL6_CTC_MID: u32 = 0x00000400; // Mid Band +pub const ADC_DCCTL6_CTC_HIGH: u32 = 0x00000C00; // High Band +pub const ADC_DCCTL6_CTM_M: u32 = 0x00000300; // Comparison Trigger Mode +pub const ADC_DCCTL6_CTM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL6_CTM_ONCE: u32 = 0x00000100; // Once +pub const ADC_DCCTL6_CTM_HALWAYS: u32 = 0x00000200; // Hysteresis Always +pub const ADC_DCCTL6_CTM_HONCE: u32 = 0x00000300; // Hysteresis Once +pub const ADC_DCCTL6_CIE: u32 = 0x00000010; // Comparison Interrupt Enable +pub const ADC_DCCTL6_CIC_M: u32 = 0x0000000C; // Comparison Interrupt Condition +pub const ADC_DCCTL6_CIC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL6_CIC_MID: u32 = 0x00000004; // Mid Band +pub const ADC_DCCTL6_CIC_HIGH: u32 = 0x0000000C; // High Band +pub const ADC_DCCTL6_CIM_M: u32 = 0x00000003; // Comparison Interrupt Mode +pub const ADC_DCCTL6_CIM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL6_CIM_ONCE: u32 = 0x00000001; // Once +pub const ADC_DCCTL6_CIM_HALWAYS: u32 = 0x00000002; // Hysteresis Always +pub const ADC_DCCTL6_CIM_HONCE: u32 = 0x00000003; // Hysteresis Once +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL7 register. +// +//***************************************************************************** +pub const ADC_DCCTL7_CTE: u32 = 0x00001000; // Comparison Trigger Enable +pub const ADC_DCCTL7_CTC_M: u32 = 0x00000C00; // Comparison Trigger Condition +pub const ADC_DCCTL7_CTC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL7_CTC_MID: u32 = 0x00000400; // Mid Band +pub const ADC_DCCTL7_CTC_HIGH: u32 = 0x00000C00; // High Band +pub const ADC_DCCTL7_CTM_M: u32 = 0x00000300; // Comparison Trigger Mode +pub const ADC_DCCTL7_CTM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL7_CTM_ONCE: u32 = 0x00000100; // Once +pub const ADC_DCCTL7_CTM_HALWAYS: u32 = 0x00000200; // Hysteresis Always +pub const ADC_DCCTL7_CTM_HONCE: u32 = 0x00000300; // Hysteresis Once +pub const ADC_DCCTL7_CIE: u32 = 0x00000010; // Comparison Interrupt Enable +pub const ADC_DCCTL7_CIC_M: u32 = 0x0000000C; // Comparison Interrupt Condition +pub const ADC_DCCTL7_CIC_LOW: u32 = 0x00000000; // Low Band +pub const ADC_DCCTL7_CIC_MID: u32 = 0x00000004; // Mid Band +pub const ADC_DCCTL7_CIC_HIGH: u32 = 0x0000000C; // High Band +pub const ADC_DCCTL7_CIM_M: u32 = 0x00000003; // Comparison Interrupt Mode +pub const ADC_DCCTL7_CIM_ALWAYS: u32 = 0x00000000; // Always +pub const ADC_DCCTL7_CIM_ONCE: u32 = 0x00000001; // Once +pub const ADC_DCCTL7_CIM_HALWAYS: u32 = 0x00000002; // Hysteresis Always +pub const ADC_DCCTL7_CIM_HONCE: u32 = 0x00000003; // Hysteresis Once +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP0 register. +// +//***************************************************************************** +pub const ADC_DCCMP0_COMP1_M: u32 = 0x0FFF0000; // Compare 1 +pub const ADC_DCCMP0_COMP0_M: u32 = 0x00000FFF; // Compare 0 +pub const ADC_DCCMP0_COMP1_S: u32 = 16; +pub const ADC_DCCMP0_COMP0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP1 register. +// +//***************************************************************************** +pub const ADC_DCCMP1_COMP1_M: u32 = 0x0FFF0000; // Compare 1 +pub const ADC_DCCMP1_COMP0_M: u32 = 0x00000FFF; // Compare 0 +pub const ADC_DCCMP1_COMP1_S: u32 = 16; +pub const ADC_DCCMP1_COMP0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP2 register. +// +//***************************************************************************** +pub const ADC_DCCMP2_COMP1_M: u32 = 0x0FFF0000; // Compare 1 +pub const ADC_DCCMP2_COMP0_M: u32 = 0x00000FFF; // Compare 0 +pub const ADC_DCCMP2_COMP1_S: u32 = 16; +pub const ADC_DCCMP2_COMP0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP3 register. +// +//***************************************************************************** +pub const ADC_DCCMP3_COMP1_M: u32 = 0x0FFF0000; // Compare 1 +pub const ADC_DCCMP3_COMP0_M: u32 = 0x00000FFF; // Compare 0 +pub const ADC_DCCMP3_COMP1_S: u32 = 16; +pub const ADC_DCCMP3_COMP0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP4 register. +// +//***************************************************************************** +pub const ADC_DCCMP4_COMP1_M: u32 = 0x0FFF0000; // Compare 1 +pub const ADC_DCCMP4_COMP0_M: u32 = 0x00000FFF; // Compare 0 +pub const ADC_DCCMP4_COMP1_S: u32 = 16; +pub const ADC_DCCMP4_COMP0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP5 register. +// +//***************************************************************************** +pub const ADC_DCCMP5_COMP1_M: u32 = 0x0FFF0000; // Compare 1 +pub const ADC_DCCMP5_COMP0_M: u32 = 0x00000FFF; // Compare 0 +pub const ADC_DCCMP5_COMP1_S: u32 = 16; +pub const ADC_DCCMP5_COMP0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP6 register. +// +//***************************************************************************** +pub const ADC_DCCMP6_COMP1_M: u32 = 0x0FFF0000; // Compare 1 +pub const ADC_DCCMP6_COMP0_M: u32 = 0x00000FFF; // Compare 0 +pub const ADC_DCCMP6_COMP1_S: u32 = 16; +pub const ADC_DCCMP6_COMP0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP7 register. +// +//***************************************************************************** +pub const ADC_DCCMP7_COMP1_M: u32 = 0x0FFF0000; // Compare 1 +pub const ADC_DCCMP7_COMP0_M: u32 = 0x00000FFF; // Compare 0 +pub const ADC_DCCMP7_COMP1_S: u32 = 16; +pub const ADC_DCCMP7_COMP0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PP register. +// +//***************************************************************************** +pub const ADC_PP_TS: u32 = 0x00800000; // Temperature Sensor +pub const ADC_PP_RSL_M: u32 = 0x007C0000; // Resolution +pub const ADC_PP_TYPE_M: u32 = 0x00030000; // ADC Architecture +pub const ADC_PP_TYPE_SAR: u32 = 0x00000000; // SAR +pub const ADC_PP_DC_M: u32 = 0x0000FC00; // Digital Comparator Count +pub const ADC_PP_CH_M: u32 = 0x000003F0; // ADC Channel Count +pub const ADC_PP_MSR_M: u32 = 0x0000000F; // Maximum ADC Sample Rate +pub const ADC_PP_MSR_125K: u32 = 0x00000001; // 125 ksps +pub const ADC_PP_MSR_250K: u32 = 0x00000003; // 250 ksps +pub const ADC_PP_MSR_500K: u32 = 0x00000005; // 500 ksps +pub const ADC_PP_MSR_1M: u32 = 0x00000007; // 1 Msps +pub const ADC_PP_RSL_S: u32 = 18; +pub const ADC_PP_DC_S: u32 = 10; +pub const ADC_PP_CH_S: u32 = 4; +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PC register. +// +//***************************************************************************** +pub const ADC_PC_SR_M: u32 = 0x0000000F; // ADC Sample Rate +pub const ADC_PC_SR_125K: u32 = 0x00000001; // 125 ksps +pub const ADC_PC_SR_250K: u32 = 0x00000003; // 250 ksps +pub const ADC_PC_SR_500K: u32 = 0x00000005; // 500 ksps +pub const ADC_PC_SR_1M: u32 = 0x00000007; // 1 Msps +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CC register. +// +//***************************************************************************** +pub const ADC_CC_CS_M: u32 = 0x0000000F; // ADC Clock Source +pub const ADC_CC_CS_SYSPLL: u32 = 0x00000000; // PLL VCO divided by CLKDIV +pub const ADC_CC_CS_PIOSC: u32 = 0x00000001; // PIOSC +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACMIS register. +// +//***************************************************************************** +pub const COMP_ACMIS_IN1: u32 = 0x00000002; // Comparator 1 Masked Interrupt + // Status +pub const COMP_ACMIS_IN0: u32 = 0x00000001; // Comparator 0 Masked Interrupt + // Status +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACRIS register. +// +//***************************************************************************** +pub const COMP_ACRIS_IN1: u32 = 0x00000002; // Comparator 1 Interrupt Status +pub const COMP_ACRIS_IN0: u32 = 0x00000001; // Comparator 0 Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACINTEN register. +// +//***************************************************************************** +pub const COMP_ACINTEN_IN1: u32 = 0x00000002; // Comparator 1 Interrupt Enable +pub const COMP_ACINTEN_IN0: u32 = 0x00000001; // Comparator 0 Interrupt Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACREFCTL +// register. +// +//***************************************************************************** +pub const COMP_ACREFCTL_EN: u32 = 0x00000200; // Resistor Ladder Enable +pub const COMP_ACREFCTL_RNG: u32 = 0x00000100; // Resistor Ladder Range +pub const COMP_ACREFCTL_VREF_M: u32 = 0x0000000F; // Resistor Ladder Voltage Ref +pub const COMP_ACREFCTL_VREF_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. +// +//***************************************************************************** +pub const COMP_ACSTAT0_OVAL: u32 = 0x00000002; // Comparator Output Value +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL0 register. +// +//***************************************************************************** +pub const COMP_ACCTL0_TOEN: u32 = 0x00000800; // Trigger Output Enable +pub const COMP_ACCTL0_ASRCP_M: u32 = 0x00000600; // Analog Source Positive +pub const COMP_ACCTL0_ASRCP_PIN: u32 = 0x00000000; // Pin value of Cn+ +pub const COMP_ACCTL0_ASRCP_PIN0: u32 = 0x00000200; // Pin value of C0+ +pub const COMP_ACCTL0_ASRCP_REF: u32 = 0x00000400; // Internal voltage reference +pub const COMP_ACCTL0_TSLVAL: u32 = 0x00000080; // Trigger Sense Level Value +pub const COMP_ACCTL0_TSEN_M: u32 = 0x00000060; // Trigger Sense +pub const COMP_ACCTL0_TSEN_LEVEL: u32 = 0x00000000; // Level sense, see TSLVAL +pub const COMP_ACCTL0_TSEN_FALL: u32 = 0x00000020; // Falling edge +pub const COMP_ACCTL0_TSEN_RISE: u32 = 0x00000040; // Rising edge +pub const COMP_ACCTL0_TSEN_BOTH: u32 = 0x00000060; // Either edge +pub const COMP_ACCTL0_ISLVAL: u32 = 0x00000010; // Interrupt Sense Level Value +pub const COMP_ACCTL0_ISEN_M: u32 = 0x0000000C; // Interrupt Sense +pub const COMP_ACCTL0_ISEN_LEVEL: u32 = 0x00000000; // Level sense, see ISLVAL +pub const COMP_ACCTL0_ISEN_FALL: u32 = 0x00000004; // Falling edge +pub const COMP_ACCTL0_ISEN_RISE: u32 = 0x00000008; // Rising edge +pub const COMP_ACCTL0_ISEN_BOTH: u32 = 0x0000000C; // Either edge +pub const COMP_ACCTL0_CINV: u32 = 0x00000002; // Comparator Output Invert +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. +// +//***************************************************************************** +pub const COMP_ACSTAT1_OVAL: u32 = 0x00000002; // Comparator Output Value +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL1 register. +// +//***************************************************************************** +pub const COMP_ACCTL1_TOEN: u32 = 0x00000800; // Trigger Output Enable +pub const COMP_ACCTL1_ASRCP_M: u32 = 0x00000600; // Analog Source Positive +pub const COMP_ACCTL1_ASRCP_PIN: u32 = 0x00000000; // Pin value of Cn+ +pub const COMP_ACCTL1_ASRCP_PIN0: u32 = 0x00000200; // Pin value of C0+ +pub const COMP_ACCTL1_ASRCP_REF: u32 = 0x00000400; // Internal voltage reference +pub const COMP_ACCTL1_TSLVAL: u32 = 0x00000080; // Trigger Sense Level Value +pub const COMP_ACCTL1_TSEN_M: u32 = 0x00000060; // Trigger Sense +pub const COMP_ACCTL1_TSEN_LEVEL: u32 = 0x00000000; // Level sense, see TSLVAL +pub const COMP_ACCTL1_TSEN_FALL: u32 = 0x00000020; // Falling edge +pub const COMP_ACCTL1_TSEN_RISE: u32 = 0x00000040; // Rising edge +pub const COMP_ACCTL1_TSEN_BOTH: u32 = 0x00000060; // Either edge +pub const COMP_ACCTL1_ISLVAL: u32 = 0x00000010; // Interrupt Sense Level Value +pub const COMP_ACCTL1_ISEN_M: u32 = 0x0000000C; // Interrupt Sense +pub const COMP_ACCTL1_ISEN_LEVEL: u32 = 0x00000000; // Level sense, see ISLVAL +pub const COMP_ACCTL1_ISEN_FALL: u32 = 0x00000004; // Falling edge +pub const COMP_ACCTL1_ISEN_RISE: u32 = 0x00000008; // Rising edge +pub const COMP_ACCTL1_ISEN_BOTH: u32 = 0x0000000C; // Either edge +pub const COMP_ACCTL1_CINV: u32 = 0x00000002; // Comparator Output Invert +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_PP register. +// +//***************************************************************************** +pub const COMP_PP_C1O: u32 = 0x00020000; // Comparator Output 1 Present +pub const COMP_PP_C0O: u32 = 0x00010000; // Comparator Output 0 Present +pub const COMP_PP_CMP1: u32 = 0x00000002; // Comparator 1 Present +pub const COMP_PP_CMP0: u32 = 0x00000001; // Comparator 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_CTL register. +// +//***************************************************************************** +pub const CAN_CTL_TEST: u32 = 0x00000080; // Test Mode Enable +pub const CAN_CTL_CCE: u32 = 0x00000040; // Configuration Change Enable +pub const CAN_CTL_DAR: u32 = 0x00000020; // Disable Automatic-Retransmission +pub const CAN_CTL_EIE: u32 = 0x00000008; // Error Interrupt Enable +pub const CAN_CTL_SIE: u32 = 0x00000004; // Status Interrupt Enable +pub const CAN_CTL_IE: u32 = 0x00000002; // CAN Interrupt Enable +pub const CAN_CTL_INIT: u32 = 0x00000001; // Initialization +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_STS register. +// +//***************************************************************************** +pub const CAN_STS_BOFF: u32 = 0x00000080; // Bus-Off Status +pub const CAN_STS_EWARN: u32 = 0x00000040; // Warning Status +pub const CAN_STS_EPASS: u32 = 0x00000020; // Error Passive +pub const CAN_STS_RXOK: u32 = 0x00000010; // Received a Message Successfully +pub const CAN_STS_TXOK: u32 = 0x00000008; // Transmitted a Message + // Successfully +pub const CAN_STS_LEC_M: u32 = 0x00000007; // Last Error Code +pub const CAN_STS_LEC_NONE: u32 = 0x00000000; // No Error +pub const CAN_STS_LEC_STUFF: u32 = 0x00000001; // Stuff Error +pub const CAN_STS_LEC_FORM: u32 = 0x00000002; // Format Error +pub const CAN_STS_LEC_ACK: u32 = 0x00000003; // ACK Error +pub const CAN_STS_LEC_BIT1: u32 = 0x00000004; // Bit 1 Error +pub const CAN_STS_LEC_BIT0: u32 = 0x00000005; // Bit 0 Error +pub const CAN_STS_LEC_CRC: u32 = 0x00000006; // CRC Error +pub const CAN_STS_LEC_NOEVENT: u32 = 0x00000007; // No Event +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_ERR register. +// +//***************************************************************************** +pub const CAN_ERR_RP: u32 = 0x00008000; // Received Error Passive +pub const CAN_ERR_REC_M: u32 = 0x00007F00; // Receive Error Counter +pub const CAN_ERR_TEC_M: u32 = 0x000000FF; // Transmit Error Counter +pub const CAN_ERR_REC_S: u32 = 8; +pub const CAN_ERR_TEC_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BIT register. +// +//***************************************************************************** +pub const CAN_BIT_TSEG2_M: u32 = 0x00007000; // Time Segment after Sample Point +pub const CAN_BIT_TSEG1_M: u32 = 0x00000F00; // Time Segment Before Sample Point +pub const CAN_BIT_SJW_M: u32 = 0x000000C0; // (Re)Synchronization Jump Width +pub const CAN_BIT_BRP_M: u32 = 0x0000003F; // Baud Rate Prescaler +pub const CAN_BIT_TSEG2_S: u32 = 12; +pub const CAN_BIT_TSEG1_S: u32 = 8; +pub const CAN_BIT_SJW_S: u32 = 6; +pub const CAN_BIT_BRP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_INT register. +// +//***************************************************************************** +pub const CAN_INT_INTID_M: u32 = 0x0000FFFF; // Interrupt Identifier +pub const CAN_INT_INTID_NONE: u32 = 0x00000000; // No interrupt pending +pub const CAN_INT_INTID_STATUS: u32 = 0x00008000; // Status Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TST register. +// +//***************************************************************************** +pub const CAN_TST_RX: u32 = 0x00000080; // Receive Observation +pub const CAN_TST_TX_M: u32 = 0x00000060; // Transmit Control +pub const CAN_TST_TX_CANCTL: u32 = 0x00000000; // CAN Module Control +pub const CAN_TST_TX_SAMPLE: u32 = 0x00000020; // Sample Point +pub const CAN_TST_TX_DOMINANT: u32 = 0x00000040; // Driven Low +pub const CAN_TST_TX_RECESSIVE: u32 = 0x00000060; // Driven High +pub const CAN_TST_LBACK: u32 = 0x00000010; // Loopback Mode +pub const CAN_TST_SILENT: u32 = 0x00000008; // Silent Mode +pub const CAN_TST_BASIC: u32 = 0x00000004; // Basic Mode +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BRPE register. +// +//***************************************************************************** +pub const CAN_BRPE_BRPE_M: u32 = 0x0000000F; // Baud Rate Prescaler Extension +pub const CAN_BRPE_BRPE_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CRQ register. +// +//***************************************************************************** +pub const CAN_IF1CRQ_BUSY: u32 = 0x00008000; // Busy Flag +pub const CAN_IF1CRQ_MNUM_M: u32 = 0x0000003F; // Message Number +pub const CAN_IF1CRQ_MNUM_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CMSK register. +// +//***************************************************************************** +pub const CAN_IF1CMSK_WRNRD: u32 = 0x00000080; // Write, Not Read +pub const CAN_IF1CMSK_MASK: u32 = 0x00000040; // Access Mask Bits +pub const CAN_IF1CMSK_ARB: u32 = 0x00000020; // Access Arbitration Bits +pub const CAN_IF1CMSK_CONTROL: u32 = 0x00000010; // Access Control Bits +pub const CAN_IF1CMSK_CLRINTPND: u32 = 0x00000008; // Clear Interrupt Pending Bit +pub const CAN_IF1CMSK_NEWDAT: u32 = 0x00000004; // Access New Data +pub const CAN_IF1CMSK_TXRQST: u32 = 0x00000004; // Access Transmission Request +pub const CAN_IF1CMSK_DATAA: u32 = 0x00000002; // Access Data Byte 0 to 3 +pub const CAN_IF1CMSK_DATAB: u32 = 0x00000001; // Access Data Byte 4 to 7 +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. +// +//***************************************************************************** +pub const CAN_IF1MSK1_IDMSK_M: u32 = 0x0000FFFF; // Identifier Mask +pub const CAN_IF1MSK1_IDMSK_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. +// +//***************************************************************************** +pub const CAN_IF1MSK2_MXTD: u32 = 0x00008000; // Mask Extended Identifier +pub const CAN_IF1MSK2_MDIR: u32 = 0x00004000; // Mask Message Direction +pub const CAN_IF1MSK2_IDMSK_M: u32 = 0x00001FFF; // Identifier Mask +pub const CAN_IF1MSK2_IDMSK_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. +// +//***************************************************************************** +pub const CAN_IF1ARB1_ID_M: u32 = 0x0000FFFF; // Message Identifier +pub const CAN_IF1ARB1_ID_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. +// +//***************************************************************************** +pub const CAN_IF1ARB2_MSGVAL: u32 = 0x00008000; // Message Valid +pub const CAN_IF1ARB2_XTD: u32 = 0x00004000; // Extended Identifier +pub const CAN_IF1ARB2_DIR: u32 = 0x00002000; // Message Direction +pub const CAN_IF1ARB2_ID_M: u32 = 0x00001FFF; // Message Identifier +pub const CAN_IF1ARB2_ID_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MCTL register. +// +//***************************************************************************** +pub const CAN_IF1MCTL_NEWDAT: u32 = 0x00008000; // New Data +pub const CAN_IF1MCTL_MSGLST: u32 = 0x00004000; // Message Lost +pub const CAN_IF1MCTL_INTPND: u32 = 0x00002000; // Interrupt Pending +pub const CAN_IF1MCTL_UMASK: u32 = 0x00001000; // Use Acceptance Mask +pub const CAN_IF1MCTL_TXIE: u32 = 0x00000800; // Transmit Interrupt Enable +pub const CAN_IF1MCTL_RXIE: u32 = 0x00000400; // Receive Interrupt Enable +pub const CAN_IF1MCTL_RMTEN: u32 = 0x00000200; // Remote Enable +pub const CAN_IF1MCTL_TXRQST: u32 = 0x00000100; // Transmit Request +pub const CAN_IF1MCTL_EOB: u32 = 0x00000080; // End of Buffer +pub const CAN_IF1MCTL_DLC_M: u32 = 0x0000000F; // Data Length Code +pub const CAN_IF1MCTL_DLC_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA1 register. +// +//***************************************************************************** +pub const CAN_IF1DA1_DATA_M: u32 = 0x0000FFFF; // Data +pub const CAN_IF1DA1_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA2 register. +// +//***************************************************************************** +pub const CAN_IF1DA2_DATA_M: u32 = 0x0000FFFF; // Data +pub const CAN_IF1DA2_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB1 register. +// +//***************************************************************************** +pub const CAN_IF1DB1_DATA_M: u32 = 0x0000FFFF; // Data +pub const CAN_IF1DB1_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB2 register. +// +//***************************************************************************** +pub const CAN_IF1DB2_DATA_M: u32 = 0x0000FFFF; // Data +pub const CAN_IF1DB2_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CRQ register. +// +//***************************************************************************** +pub const CAN_IF2CRQ_BUSY: u32 = 0x00008000; // Busy Flag +pub const CAN_IF2CRQ_MNUM_M: u32 = 0x0000003F; // Message Number +pub const CAN_IF2CRQ_MNUM_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CMSK register. +// +//***************************************************************************** +pub const CAN_IF2CMSK_WRNRD: u32 = 0x00000080; // Write, Not Read +pub const CAN_IF2CMSK_MASK: u32 = 0x00000040; // Access Mask Bits +pub const CAN_IF2CMSK_ARB: u32 = 0x00000020; // Access Arbitration Bits +pub const CAN_IF2CMSK_CONTROL: u32 = 0x00000010; // Access Control Bits +pub const CAN_IF2CMSK_CLRINTPND: u32 = 0x00000008; // Clear Interrupt Pending Bit +pub const CAN_IF2CMSK_NEWDAT: u32 = 0x00000004; // Access New Data +pub const CAN_IF2CMSK_TXRQST: u32 = 0x00000004; // Access Transmission Request +pub const CAN_IF2CMSK_DATAA: u32 = 0x00000002; // Access Data Byte 0 to 3 +pub const CAN_IF2CMSK_DATAB: u32 = 0x00000001; // Access Data Byte 4 to 7 +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. +// +//***************************************************************************** +pub const CAN_IF2MSK1_IDMSK_M: u32 = 0x0000FFFF; // Identifier Mask +pub const CAN_IF2MSK1_IDMSK_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. +// +//***************************************************************************** +pub const CAN_IF2MSK2_MXTD: u32 = 0x00008000; // Mask Extended Identifier +pub const CAN_IF2MSK2_MDIR: u32 = 0x00004000; // Mask Message Direction +pub const CAN_IF2MSK2_IDMSK_M: u32 = 0x00001FFF; // Identifier Mask +pub const CAN_IF2MSK2_IDMSK_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. +// +//***************************************************************************** +pub const CAN_IF2ARB1_ID_M: u32 = 0x0000FFFF; // Message Identifier +pub const CAN_IF2ARB1_ID_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. +// +//***************************************************************************** +pub const CAN_IF2ARB2_MSGVAL: u32 = 0x00008000; // Message Valid +pub const CAN_IF2ARB2_XTD: u32 = 0x00004000; // Extended Identifier +pub const CAN_IF2ARB2_DIR: u32 = 0x00002000; // Message Direction +pub const CAN_IF2ARB2_ID_M: u32 = 0x00001FFF; // Message Identifier +pub const CAN_IF2ARB2_ID_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MCTL register. +// +//***************************************************************************** +pub const CAN_IF2MCTL_NEWDAT: u32 = 0x00008000; // New Data +pub const CAN_IF2MCTL_MSGLST: u32 = 0x00004000; // Message Lost +pub const CAN_IF2MCTL_INTPND: u32 = 0x00002000; // Interrupt Pending +pub const CAN_IF2MCTL_UMASK: u32 = 0x00001000; // Use Acceptance Mask +pub const CAN_IF2MCTL_TXIE: u32 = 0x00000800; // Transmit Interrupt Enable +pub const CAN_IF2MCTL_RXIE: u32 = 0x00000400; // Receive Interrupt Enable +pub const CAN_IF2MCTL_RMTEN: u32 = 0x00000200; // Remote Enable +pub const CAN_IF2MCTL_TXRQST: u32 = 0x00000100; // Transmit Request +pub const CAN_IF2MCTL_EOB: u32 = 0x00000080; // End of Buffer +pub const CAN_IF2MCTL_DLC_M: u32 = 0x0000000F; // Data Length Code +pub const CAN_IF2MCTL_DLC_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA1 register. +// +//***************************************************************************** +pub const CAN_IF2DA1_DATA_M: u32 = 0x0000FFFF; // Data +pub const CAN_IF2DA1_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA2 register. +// +//***************************************************************************** +pub const CAN_IF2DA2_DATA_M: u32 = 0x0000FFFF; // Data +pub const CAN_IF2DA2_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB1 register. +// +//***************************************************************************** +pub const CAN_IF2DB1_DATA_M: u32 = 0x0000FFFF; // Data +pub const CAN_IF2DB1_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB2 register. +// +//***************************************************************************** +pub const CAN_IF2DB2_DATA_M: u32 = 0x0000FFFF; // Data +pub const CAN_IF2DB2_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ1 register. +// +//***************************************************************************** +pub const CAN_TXRQ1_TXRQST_M: u32 = 0x0000FFFF; // Transmission Request Bits +pub const CAN_TXRQ1_TXRQST_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ2 register. +// +//***************************************************************************** +pub const CAN_TXRQ2_TXRQST_M: u32 = 0x0000FFFF; // Transmission Request Bits +pub const CAN_TXRQ2_TXRQST_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA1 register. +// +//***************************************************************************** +pub const CAN_NWDA1_NEWDAT_M: u32 = 0x0000FFFF; // New Data Bits +pub const CAN_NWDA1_NEWDAT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA2 register. +// +//***************************************************************************** +pub const CAN_NWDA2_NEWDAT_M: u32 = 0x0000FFFF; // New Data Bits +pub const CAN_NWDA2_NEWDAT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1INT register. +// +//***************************************************************************** +pub const CAN_MSG1INT_INTPND_M: u32 = 0x0000FFFF; // Interrupt Pending Bits +pub const CAN_MSG1INT_INTPND_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2INT register. +// +//***************************************************************************** +pub const CAN_MSG2INT_INTPND_M: u32 = 0x0000FFFF; // Interrupt Pending Bits +pub const CAN_MSG2INT_INTPND_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1VAL register. +// +//***************************************************************************** +pub const CAN_MSG1VAL_MSGVAL_M: u32 = 0x0000FFFF; // Message Valid Bits +pub const CAN_MSG1VAL_MSGVAL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2VAL register. +// +//***************************************************************************** +pub const CAN_MSG2VAL_MSGVAL_M: u32 = 0x0000FFFF; // Message Valid Bits +pub const CAN_MSG2VAL_MSGVAL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +pub const USB_FADDR_M: u32 = 0x0000007F; // Function Address +pub const USB_FADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +pub const USB_POWER_ISOUP: u32 = 0x00000080; // Isochronous Update +pub const USB_POWER_SOFTCONN: u32 = 0x00000040; // Soft Connect/Disconnect +pub const USB_POWER_RESET: u32 = 0x00000008; // RESET Signaling +pub const USB_POWER_RESUME: u32 = 0x00000004; // RESUME Signaling +pub const USB_POWER_SUSPEND: u32 = 0x00000002; // SUSPEND Mode +pub const USB_POWER_PWRDNPHY: u32 = 0x00000001; // Power Down PHY +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +pub const USB_TXIS_EP7: u32 = 0x00000080; // TX Endpoint 7 Interrupt +pub const USB_TXIS_EP6: u32 = 0x00000040; // TX Endpoint 6 Interrupt +pub const USB_TXIS_EP5: u32 = 0x00000020; // TX Endpoint 5 Interrupt +pub const USB_TXIS_EP4: u32 = 0x00000010; // TX Endpoint 4 Interrupt +pub const USB_TXIS_EP3: u32 = 0x00000008; // TX Endpoint 3 Interrupt +pub const USB_TXIS_EP2: u32 = 0x00000004; // TX Endpoint 2 Interrupt +pub const USB_TXIS_EP1: u32 = 0x00000002; // TX Endpoint 1 Interrupt +pub const USB_TXIS_EP0: u32 = 0x00000001; // TX and RX Endpoint 0 Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +pub const USB_RXIS_EP7: u32 = 0x00000080; // RX Endpoint 7 Interrupt +pub const USB_RXIS_EP6: u32 = 0x00000040; // RX Endpoint 6 Interrupt +pub const USB_RXIS_EP5: u32 = 0x00000020; // RX Endpoint 5 Interrupt +pub const USB_RXIS_EP4: u32 = 0x00000010; // RX Endpoint 4 Interrupt +pub const USB_RXIS_EP3: u32 = 0x00000008; // RX Endpoint 3 Interrupt +pub const USB_RXIS_EP2: u32 = 0x00000004; // RX Endpoint 2 Interrupt +pub const USB_RXIS_EP1: u32 = 0x00000002; // RX Endpoint 1 Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +pub const USB_TXIE_EP7: u32 = 0x00000080; // TX Endpoint 7 Interrupt Enable +pub const USB_TXIE_EP6: u32 = 0x00000040; // TX Endpoint 6 Interrupt Enable +pub const USB_TXIE_EP5: u32 = 0x00000020; // TX Endpoint 5 Interrupt Enable +pub const USB_TXIE_EP4: u32 = 0x00000010; // TX Endpoint 4 Interrupt Enable +pub const USB_TXIE_EP3: u32 = 0x00000008; // TX Endpoint 3 Interrupt Enable +pub const USB_TXIE_EP2: u32 = 0x00000004; // TX Endpoint 2 Interrupt Enable +pub const USB_TXIE_EP1: u32 = 0x00000002; // TX Endpoint 1 Interrupt Enable +pub const USB_TXIE_EP0: u32 = 0x00000001; // TX and RX Endpoint 0 Interrupt + // Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +pub const USB_RXIE_EP7: u32 = 0x00000080; // RX Endpoint 7 Interrupt Enable +pub const USB_RXIE_EP6: u32 = 0x00000040; // RX Endpoint 6 Interrupt Enable +pub const USB_RXIE_EP5: u32 = 0x00000020; // RX Endpoint 5 Interrupt Enable +pub const USB_RXIE_EP4: u32 = 0x00000010; // RX Endpoint 4 Interrupt Enable +pub const USB_RXIE_EP3: u32 = 0x00000008; // RX Endpoint 3 Interrupt Enable +pub const USB_RXIE_EP2: u32 = 0x00000004; // RX Endpoint 2 Interrupt Enable +pub const USB_RXIE_EP1: u32 = 0x00000002; // RX Endpoint 1 Interrupt Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +pub const USB_IS_VBUSERR: u32 = 0x00000080; // VBUS Error (OTG only) +pub const USB_IS_SESREQ: u32 = 0x00000040; // SESSION REQUEST (OTG only) +pub const USB_IS_DISCON: u32 = 0x00000020; // Session Disconnect (OTG only) +pub const USB_IS_CONN: u32 = 0x00000010; // Session Connect +pub const USB_IS_SOF: u32 = 0x00000008; // Start of Frame +pub const USB_IS_BABBLE: u32 = 0x00000004; // Babble Detected +pub const USB_IS_RESET: u32 = 0x00000004; // RESET Signaling Detected +pub const USB_IS_RESUME: u32 = 0x00000002; // RESUME Signaling Detected +pub const USB_IS_SUSPEND: u32 = 0x00000001; // SUSPEND Signaling Detected +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +pub const USB_IE_VBUSERR: u32 = 0x00000080; // Enable VBUS Error Interrupt (OTG + // only) +pub const USB_IE_SESREQ: u32 = 0x00000040; // Enable Session Request (OTG + // only) +pub const USB_IE_DISCON: u32 = 0x00000020; // Enable Disconnect Interrupt +pub const USB_IE_CONN: u32 = 0x00000010; // Enable Connect Interrupt +pub const USB_IE_SOF: u32 = 0x00000008; // Enable Start-of-Frame Interrupt +pub const USB_IE_BABBLE: u32 = 0x00000004; // Enable Babble Interrupt +pub const USB_IE_RESET: u32 = 0x00000004; // Enable RESET Interrupt +pub const USB_IE_RESUME: u32 = 0x00000002; // Enable RESUME Interrupt +pub const USB_IE_SUSPND: u32 = 0x00000001; // Enable SUSPEND Interrupt +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +pub const USB_FRAME_M: u32 = 0x000007FF; // Frame Number +pub const USB_FRAME_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +pub const USB_EPIDX_EPIDX_M: u32 = 0x0000000F; // Endpoint Index +pub const USB_EPIDX_EPIDX_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +pub const USB_TEST_FORCEH: u32 = 0x00000080; // Force Host Mode +pub const USB_TEST_FIFOACC: u32 = 0x00000040; // FIFO Access +pub const USB_TEST_FORCEFS: u32 = 0x00000020; // Force Full-Speed Mode +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +pub const USB_FIFO0_EPDATA_M: u32 = 0xFFFFFFFF; // Endpoint Data +pub const USB_FIFO0_EPDATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +pub const USB_FIFO1_EPDATA_M: u32 = 0xFFFFFFFF; // Endpoint Data +pub const USB_FIFO1_EPDATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +pub const USB_FIFO2_EPDATA_M: u32 = 0xFFFFFFFF; // Endpoint Data +pub const USB_FIFO2_EPDATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +pub const USB_FIFO3_EPDATA_M: u32 = 0xFFFFFFFF; // Endpoint Data +pub const USB_FIFO3_EPDATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +pub const USB_FIFO4_EPDATA_M: u32 = 0xFFFFFFFF; // Endpoint Data +pub const USB_FIFO4_EPDATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +pub const USB_FIFO5_EPDATA_M: u32 = 0xFFFFFFFF; // Endpoint Data +pub const USB_FIFO5_EPDATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +pub const USB_FIFO6_EPDATA_M: u32 = 0xFFFFFFFF; // Endpoint Data +pub const USB_FIFO6_EPDATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +pub const USB_FIFO7_EPDATA_M: u32 = 0xFFFFFFFF; // Endpoint Data +pub const USB_FIFO7_EPDATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +pub const USB_DEVCTL_DEV: u32 = 0x00000080; // Device Mode (OTG only) +pub const USB_DEVCTL_FSDEV: u32 = 0x00000040; // Full-Speed Device Detected +pub const USB_DEVCTL_LSDEV: u32 = 0x00000020; // Low-Speed Device Detected +pub const USB_DEVCTL_VBUS_M: u32 = 0x00000018; // VBUS Level (OTG only) +pub const USB_DEVCTL_VBUS_NONE: u32 = 0x00000000; // Below SessionEnd +pub const USB_DEVCTL_VBUS_SEND: u32 = 0x00000008; // Above SessionEnd, below AValid +pub const USB_DEVCTL_VBUS_AVALID: u32 = 0x00000010; // Above AValid, below VBUSValid +pub const USB_DEVCTL_VBUS_VALID: u32 = 0x00000018; // Above VBUSValid +pub const USB_DEVCTL_HOST: u32 = 0x00000004; // Host Mode +pub const USB_DEVCTL_HOSTREQ: u32 = 0x00000002; // Host Request (OTG only) +pub const USB_DEVCTL_SESSION: u32 = 0x00000001; // Session Start/End (OTG only) +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +pub const USB_TXFIFOSZ_DPB: u32 = 0x00000010; // Double Packet Buffer Support +pub const USB_TXFIFOSZ_SIZE_M: u32 = 0x0000000F; // Max Packet Size +pub const USB_TXFIFOSZ_SIZE_8: u32 = 0x00000000; // 8 +pub const USB_TXFIFOSZ_SIZE_16: u32 = 0x00000001; // 16 +pub const USB_TXFIFOSZ_SIZE_32: u32 = 0x00000002; // 32 +pub const USB_TXFIFOSZ_SIZE_64: u32 = 0x00000003; // 64 +pub const USB_TXFIFOSZ_SIZE_128: u32 = 0x00000004; // 128 +pub const USB_TXFIFOSZ_SIZE_256: u32 = 0x00000005; // 256 +pub const USB_TXFIFOSZ_SIZE_512: u32 = 0x00000006; // 512 +pub const USB_TXFIFOSZ_SIZE_1024: u32 = 0x00000007; // 1024 +pub const USB_TXFIFOSZ_SIZE_2048: u32 = 0x00000008; // 2048 +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +pub const USB_RXFIFOSZ_DPB: u32 = 0x00000010; // Double Packet Buffer Support +pub const USB_RXFIFOSZ_SIZE_M: u32 = 0x0000000F; // Max Packet Size +pub const USB_RXFIFOSZ_SIZE_8: u32 = 0x00000000; // 8 +pub const USB_RXFIFOSZ_SIZE_16: u32 = 0x00000001; // 16 +pub const USB_RXFIFOSZ_SIZE_32: u32 = 0x00000002; // 32 +pub const USB_RXFIFOSZ_SIZE_64: u32 = 0x00000003; // 64 +pub const USB_RXFIFOSZ_SIZE_128: u32 = 0x00000004; // 128 +pub const USB_RXFIFOSZ_SIZE_256: u32 = 0x00000005; // 256 +pub const USB_RXFIFOSZ_SIZE_512: u32 = 0x00000006; // 512 +pub const USB_RXFIFOSZ_SIZE_1024: u32 = 0x00000007; // 1024 +pub const USB_RXFIFOSZ_SIZE_2048: u32 = 0x00000008; // 2048 +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +pub const USB_TXFIFOADD_ADDR_M: u32 = 0x000001FF; // Transmit/Receive Start Address +pub const USB_TXFIFOADD_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +pub const USB_RXFIFOADD_ADDR_M: u32 = 0x000001FF; // Transmit/Receive Start Address +pub const USB_RXFIFOADD_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +pub const USB_CONTIM_WTCON_M: u32 = 0x000000F0; // Connect Wait +pub const USB_CONTIM_WTID_M: u32 = 0x0000000F; // Wait ID +pub const USB_CONTIM_WTCON_S: u32 = 4; +pub const USB_CONTIM_WTID_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +pub const USB_VPLEN_VPLEN_M: u32 = 0x000000FF; // VBUS Pulse Length +pub const USB_VPLEN_VPLEN_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +pub const USB_FSEOF_FSEOFG_M: u32 = 0x000000FF; // Full-Speed End-of-Frame Gap +pub const USB_FSEOF_FSEOFG_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +pub const USB_LSEOF_LSEOFG_M: u32 = 0x000000FF; // Low-Speed End-of-Frame Gap +pub const USB_LSEOF_LSEOFG_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +pub const USB_TXFUNCADDR0_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_TXFUNCADDR0_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +pub const USB_TXHUBADDR0_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_TXHUBADDR0_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +pub const USB_TXHUBPORT0_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_TXHUBPORT0_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +pub const USB_TXFUNCADDR1_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_TXFUNCADDR1_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +pub const USB_TXHUBADDR1_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_TXHUBADDR1_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +pub const USB_TXHUBPORT1_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_TXHUBPORT1_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +pub const USB_RXFUNCADDR1_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_RXFUNCADDR1_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +pub const USB_RXHUBADDR1_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_RXHUBADDR1_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +pub const USB_RXHUBPORT1_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_RXHUBPORT1_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +pub const USB_TXFUNCADDR2_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_TXFUNCADDR2_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +pub const USB_TXHUBADDR2_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_TXHUBADDR2_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +pub const USB_TXHUBPORT2_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_TXHUBPORT2_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +pub const USB_RXFUNCADDR2_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_RXFUNCADDR2_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +pub const USB_RXHUBADDR2_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_RXHUBADDR2_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +pub const USB_RXHUBPORT2_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_RXHUBPORT2_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +pub const USB_TXFUNCADDR3_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_TXFUNCADDR3_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +pub const USB_TXHUBADDR3_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_TXHUBADDR3_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +pub const USB_TXHUBPORT3_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_TXHUBPORT3_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +pub const USB_RXFUNCADDR3_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_RXFUNCADDR3_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +pub const USB_RXHUBADDR3_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_RXHUBADDR3_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +pub const USB_RXHUBPORT3_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_RXHUBPORT3_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +pub const USB_TXFUNCADDR4_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_TXFUNCADDR4_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +pub const USB_TXHUBADDR4_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_TXHUBADDR4_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +pub const USB_TXHUBPORT4_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_TXHUBPORT4_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +pub const USB_RXFUNCADDR4_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_RXFUNCADDR4_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +pub const USB_RXHUBADDR4_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_RXHUBADDR4_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +pub const USB_RXHUBPORT4_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_RXHUBPORT4_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +pub const USB_TXFUNCADDR5_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_TXFUNCADDR5_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +pub const USB_TXHUBADDR5_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_TXHUBADDR5_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +pub const USB_TXHUBPORT5_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_TXHUBPORT5_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +pub const USB_RXFUNCADDR5_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_RXFUNCADDR5_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +pub const USB_RXHUBADDR5_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_RXHUBADDR5_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +pub const USB_RXHUBPORT5_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_RXHUBPORT5_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +pub const USB_TXFUNCADDR6_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_TXFUNCADDR6_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +pub const USB_TXHUBADDR6_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_TXHUBADDR6_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +pub const USB_TXHUBPORT6_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_TXHUBPORT6_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +pub const USB_RXFUNCADDR6_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_RXFUNCADDR6_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +pub const USB_RXHUBADDR6_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_RXHUBADDR6_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +pub const USB_RXHUBPORT6_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_RXHUBPORT6_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +pub const USB_TXFUNCADDR7_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_TXFUNCADDR7_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +pub const USB_TXHUBADDR7_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_TXHUBADDR7_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +pub const USB_TXHUBPORT7_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_TXHUBPORT7_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +pub const USB_RXFUNCADDR7_ADDR_M: u32 = 0x0000007F; // Device Address +pub const USB_RXFUNCADDR7_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +pub const USB_RXHUBADDR7_ADDR_M: u32 = 0x0000007F; // Hub Address +pub const USB_RXHUBADDR7_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +pub const USB_RXHUBPORT7_PORT_M: u32 = 0x0000007F; // Hub Port +pub const USB_RXHUBPORT7_PORT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +pub const USB_CSRL0_NAKTO: u32 = 0x00000080; // NAK Timeout +pub const USB_CSRL0_SETENDC: u32 = 0x00000080; // Setup End Clear +pub const USB_CSRL0_STATUS: u32 = 0x00000040; // STATUS Packet +pub const USB_CSRL0_RXRDYC: u32 = 0x00000040; // RXRDY Clear +pub const USB_CSRL0_REQPKT: u32 = 0x00000020; // Request Packet +pub const USB_CSRL0_STALL: u32 = 0x00000020; // Send Stall +pub const USB_CSRL0_SETEND: u32 = 0x00000010; // Setup End +pub const USB_CSRL0_ERROR: u32 = 0x00000010; // Error +pub const USB_CSRL0_DATAEND: u32 = 0x00000008; // Data End +pub const USB_CSRL0_SETUP: u32 = 0x00000008; // Setup Packet +pub const USB_CSRL0_STALLED: u32 = 0x00000004; // Endpoint Stalled +pub const USB_CSRL0_TXRDY: u32 = 0x00000002; // Transmit Packet Ready +pub const USB_CSRL0_RXRDY: u32 = 0x00000001; // Receive Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +pub const USB_CSRH0_DTWE: u32 = 0x00000004; // Data Toggle Write Enable +pub const USB_CSRH0_DT: u32 = 0x00000002; // Data Toggle +pub const USB_CSRH0_FLUSH: u32 = 0x00000001; // Flush FIFO +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +pub const USB_COUNT0_COUNT_M: u32 = 0x0000007F; // FIFO Count +pub const USB_COUNT0_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +pub const USB_TYPE0_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_TYPE0_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_TYPE0_SPEED_LOW: u32 = 0x000000C0; // Low +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +pub const USB_NAKLMT_NAKLMT_M: u32 = 0x0000001F; // EP0 NAK Limit +pub const USB_NAKLMT_NAKLMT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +pub const USB_TXMAXP1_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_TXMAXP1_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +pub const USB_TXCSRL1_NAKTO: u32 = 0x00000080; // NAK Timeout +pub const USB_TXCSRL1_CLRDT: u32 = 0x00000040; // Clear Data Toggle +pub const USB_TXCSRL1_STALLED: u32 = 0x00000020; // Endpoint Stalled +pub const USB_TXCSRL1_STALL: u32 = 0x00000010; // Send STALL +pub const USB_TXCSRL1_SETUP: u32 = 0x00000010; // Setup Packet +pub const USB_TXCSRL1_FLUSH: u32 = 0x00000008; // Flush FIFO +pub const USB_TXCSRL1_ERROR: u32 = 0x00000004; // Error +pub const USB_TXCSRL1_UNDRN: u32 = 0x00000004; // Underrun +pub const USB_TXCSRL1_FIFONE: u32 = 0x00000002; // FIFO Not Empty +pub const USB_TXCSRL1_TXRDY: u32 = 0x00000001; // Transmit Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +pub const USB_TXCSRH1_AUTOSET: u32 = 0x00000080; // Auto Set +pub const USB_TXCSRH1_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_TXCSRH1_MODE: u32 = 0x00000020; // Mode +pub const USB_TXCSRH1_DMAEN: u32 = 0x00000010; // DMA Request Enable +pub const USB_TXCSRH1_FDT: u32 = 0x00000008; // Force Data Toggle +pub const USB_TXCSRH1_DMAMOD: u32 = 0x00000004; // DMA Request Mode +pub const USB_TXCSRH1_DTWE: u32 = 0x00000002; // Data Toggle Write Enable +pub const USB_TXCSRH1_DT: u32 = 0x00000001; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +pub const USB_RXMAXP1_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_RXMAXP1_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +pub const USB_RXCSRL1_CLRDT: u32 = 0x00000080; // Clear Data Toggle +pub const USB_RXCSRL1_STALLED: u32 = 0x00000040; // Endpoint Stalled +pub const USB_RXCSRL1_STALL: u32 = 0x00000020; // Send STALL +pub const USB_RXCSRL1_REQPKT: u32 = 0x00000020; // Request Packet +pub const USB_RXCSRL1_FLUSH: u32 = 0x00000010; // Flush FIFO +pub const USB_RXCSRL1_DATAERR: u32 = 0x00000008; // Data Error +pub const USB_RXCSRL1_NAKTO: u32 = 0x00000008; // NAK Timeout +pub const USB_RXCSRL1_OVER: u32 = 0x00000004; // Overrun +pub const USB_RXCSRL1_ERROR: u32 = 0x00000004; // Error +pub const USB_RXCSRL1_FULL: u32 = 0x00000002; // FIFO Full +pub const USB_RXCSRL1_RXRDY: u32 = 0x00000001; // Receive Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +pub const USB_RXCSRH1_AUTOCL: u32 = 0x00000080; // Auto Clear +pub const USB_RXCSRH1_AUTORQ: u32 = 0x00000040; // Auto Request +pub const USB_RXCSRH1_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_RXCSRH1_DMAEN: u32 = 0x00000020; // DMA Request Enable +pub const USB_RXCSRH1_DISNYET: u32 = 0x00000010; // Disable NYET +pub const USB_RXCSRH1_PIDERR: u32 = 0x00000010; // PID Error +pub const USB_RXCSRH1_DMAMOD: u32 = 0x00000008; // DMA Request Mode +pub const USB_RXCSRH1_DTWE: u32 = 0x00000004; // Data Toggle Write Enable +pub const USB_RXCSRH1_DT: u32 = 0x00000002; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +pub const USB_RXCOUNT1_COUNT_M: u32 = 0x00001FFF; // Receive Packet Count +pub const USB_RXCOUNT1_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +pub const USB_TXTYPE1_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_TXTYPE1_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_TXTYPE1_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_TXTYPE1_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_TXTYPE1_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_TXTYPE1_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_TXTYPE1_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_TXTYPE1_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_TXTYPE1_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_TXTYPE1_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_TXTYPE1_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +pub const USB_TXINTERVAL1_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_TXINTERVAL1_TXPOLL_M: u32 = 0x000000FF; // TX Polling +pub const USB_TXINTERVAL1_TXPOLL_S: u32 = 0; +pub const USB_TXINTERVAL1_NAKLMT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +pub const USB_RXTYPE1_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_RXTYPE1_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_RXTYPE1_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_RXTYPE1_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_RXTYPE1_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_RXTYPE1_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_RXTYPE1_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_RXTYPE1_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_RXTYPE1_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_RXTYPE1_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_RXTYPE1_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +pub const USB_RXINTERVAL1_TXPOLL_M: u32 = 0x000000FF; // RX Polling +pub const USB_RXINTERVAL1_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_RXINTERVAL1_TXPOLL_S: u32 = 0; +pub const USB_RXINTERVAL1_NAKLMT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +pub const USB_TXMAXP2_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_TXMAXP2_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +pub const USB_TXCSRL2_NAKTO: u32 = 0x00000080; // NAK Timeout +pub const USB_TXCSRL2_CLRDT: u32 = 0x00000040; // Clear Data Toggle +pub const USB_TXCSRL2_STALLED: u32 = 0x00000020; // Endpoint Stalled +pub const USB_TXCSRL2_SETUP: u32 = 0x00000010; // Setup Packet +pub const USB_TXCSRL2_STALL: u32 = 0x00000010; // Send STALL +pub const USB_TXCSRL2_FLUSH: u32 = 0x00000008; // Flush FIFO +pub const USB_TXCSRL2_ERROR: u32 = 0x00000004; // Error +pub const USB_TXCSRL2_UNDRN: u32 = 0x00000004; // Underrun +pub const USB_TXCSRL2_FIFONE: u32 = 0x00000002; // FIFO Not Empty +pub const USB_TXCSRL2_TXRDY: u32 = 0x00000001; // Transmit Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +pub const USB_TXCSRH2_AUTOSET: u32 = 0x00000080; // Auto Set +pub const USB_TXCSRH2_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_TXCSRH2_MODE: u32 = 0x00000020; // Mode +pub const USB_TXCSRH2_DMAEN: u32 = 0x00000010; // DMA Request Enable +pub const USB_TXCSRH2_FDT: u32 = 0x00000008; // Force Data Toggle +pub const USB_TXCSRH2_DMAMOD: u32 = 0x00000004; // DMA Request Mode +pub const USB_TXCSRH2_DTWE: u32 = 0x00000002; // Data Toggle Write Enable +pub const USB_TXCSRH2_DT: u32 = 0x00000001; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +pub const USB_RXMAXP2_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_RXMAXP2_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +pub const USB_RXCSRL2_CLRDT: u32 = 0x00000080; // Clear Data Toggle +pub const USB_RXCSRL2_STALLED: u32 = 0x00000040; // Endpoint Stalled +pub const USB_RXCSRL2_REQPKT: u32 = 0x00000020; // Request Packet +pub const USB_RXCSRL2_STALL: u32 = 0x00000020; // Send STALL +pub const USB_RXCSRL2_FLUSH: u32 = 0x00000010; // Flush FIFO +pub const USB_RXCSRL2_DATAERR: u32 = 0x00000008; // Data Error +pub const USB_RXCSRL2_NAKTO: u32 = 0x00000008; // NAK Timeout +pub const USB_RXCSRL2_ERROR: u32 = 0x00000004; // Error +pub const USB_RXCSRL2_OVER: u32 = 0x00000004; // Overrun +pub const USB_RXCSRL2_FULL: u32 = 0x00000002; // FIFO Full +pub const USB_RXCSRL2_RXRDY: u32 = 0x00000001; // Receive Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +pub const USB_RXCSRH2_AUTOCL: u32 = 0x00000080; // Auto Clear +pub const USB_RXCSRH2_AUTORQ: u32 = 0x00000040; // Auto Request +pub const USB_RXCSRH2_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_RXCSRH2_DMAEN: u32 = 0x00000020; // DMA Request Enable +pub const USB_RXCSRH2_DISNYET: u32 = 0x00000010; // Disable NYET +pub const USB_RXCSRH2_PIDERR: u32 = 0x00000010; // PID Error +pub const USB_RXCSRH2_DMAMOD: u32 = 0x00000008; // DMA Request Mode +pub const USB_RXCSRH2_DTWE: u32 = 0x00000004; // Data Toggle Write Enable +pub const USB_RXCSRH2_DT: u32 = 0x00000002; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +pub const USB_RXCOUNT2_COUNT_M: u32 = 0x00001FFF; // Receive Packet Count +pub const USB_RXCOUNT2_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +pub const USB_TXTYPE2_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_TXTYPE2_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_TXTYPE2_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_TXTYPE2_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_TXTYPE2_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_TXTYPE2_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_TXTYPE2_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_TXTYPE2_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_TXTYPE2_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_TXTYPE2_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_TXTYPE2_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +pub const USB_TXINTERVAL2_TXPOLL_M: u32 = 0x000000FF; // TX Polling +pub const USB_TXINTERVAL2_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_TXINTERVAL2_NAKLMT_S: u32 = 0; +pub const USB_TXINTERVAL2_TXPOLL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +pub const USB_RXTYPE2_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_RXTYPE2_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_RXTYPE2_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_RXTYPE2_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_RXTYPE2_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_RXTYPE2_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_RXTYPE2_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_RXTYPE2_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_RXTYPE2_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_RXTYPE2_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_RXTYPE2_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +pub const USB_RXINTERVAL2_TXPOLL_M: u32 = 0x000000FF; // RX Polling +pub const USB_RXINTERVAL2_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_RXINTERVAL2_TXPOLL_S: u32 = 0; +pub const USB_RXINTERVAL2_NAKLMT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +pub const USB_TXMAXP3_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_TXMAXP3_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +pub const USB_TXCSRL3_NAKTO: u32 = 0x00000080; // NAK Timeout +pub const USB_TXCSRL3_CLRDT: u32 = 0x00000040; // Clear Data Toggle +pub const USB_TXCSRL3_STALLED: u32 = 0x00000020; // Endpoint Stalled +pub const USB_TXCSRL3_SETUP: u32 = 0x00000010; // Setup Packet +pub const USB_TXCSRL3_STALL: u32 = 0x00000010; // Send STALL +pub const USB_TXCSRL3_FLUSH: u32 = 0x00000008; // Flush FIFO +pub const USB_TXCSRL3_ERROR: u32 = 0x00000004; // Error +pub const USB_TXCSRL3_UNDRN: u32 = 0x00000004; // Underrun +pub const USB_TXCSRL3_FIFONE: u32 = 0x00000002; // FIFO Not Empty +pub const USB_TXCSRL3_TXRDY: u32 = 0x00000001; // Transmit Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +pub const USB_TXCSRH3_AUTOSET: u32 = 0x00000080; // Auto Set +pub const USB_TXCSRH3_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_TXCSRH3_MODE: u32 = 0x00000020; // Mode +pub const USB_TXCSRH3_DMAEN: u32 = 0x00000010; // DMA Request Enable +pub const USB_TXCSRH3_FDT: u32 = 0x00000008; // Force Data Toggle +pub const USB_TXCSRH3_DMAMOD: u32 = 0x00000004; // DMA Request Mode +pub const USB_TXCSRH3_DTWE: u32 = 0x00000002; // Data Toggle Write Enable +pub const USB_TXCSRH3_DT: u32 = 0x00000001; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +pub const USB_RXMAXP3_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_RXMAXP3_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +pub const USB_RXCSRL3_CLRDT: u32 = 0x00000080; // Clear Data Toggle +pub const USB_RXCSRL3_STALLED: u32 = 0x00000040; // Endpoint Stalled +pub const USB_RXCSRL3_STALL: u32 = 0x00000020; // Send STALL +pub const USB_RXCSRL3_REQPKT: u32 = 0x00000020; // Request Packet +pub const USB_RXCSRL3_FLUSH: u32 = 0x00000010; // Flush FIFO +pub const USB_RXCSRL3_DATAERR: u32 = 0x00000008; // Data Error +pub const USB_RXCSRL3_NAKTO: u32 = 0x00000008; // NAK Timeout +pub const USB_RXCSRL3_ERROR: u32 = 0x00000004; // Error +pub const USB_RXCSRL3_OVER: u32 = 0x00000004; // Overrun +pub const USB_RXCSRL3_FULL: u32 = 0x00000002; // FIFO Full +pub const USB_RXCSRL3_RXRDY: u32 = 0x00000001; // Receive Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +pub const USB_RXCSRH3_AUTOCL: u32 = 0x00000080; // Auto Clear +pub const USB_RXCSRH3_AUTORQ: u32 = 0x00000040; // Auto Request +pub const USB_RXCSRH3_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_RXCSRH3_DMAEN: u32 = 0x00000020; // DMA Request Enable +pub const USB_RXCSRH3_DISNYET: u32 = 0x00000010; // Disable NYET +pub const USB_RXCSRH3_PIDERR: u32 = 0x00000010; // PID Error +pub const USB_RXCSRH3_DMAMOD: u32 = 0x00000008; // DMA Request Mode +pub const USB_RXCSRH3_DTWE: u32 = 0x00000004; // Data Toggle Write Enable +pub const USB_RXCSRH3_DT: u32 = 0x00000002; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +pub const USB_RXCOUNT3_COUNT_M: u32 = 0x00001FFF; // Receive Packet Count +pub const USB_RXCOUNT3_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +pub const USB_TXTYPE3_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_TXTYPE3_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_TXTYPE3_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_TXTYPE3_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_TXTYPE3_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_TXTYPE3_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_TXTYPE3_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_TXTYPE3_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_TXTYPE3_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_TXTYPE3_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_TXTYPE3_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +pub const USB_TXINTERVAL3_TXPOLL_M: u32 = 0x000000FF; // TX Polling +pub const USB_TXINTERVAL3_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_TXINTERVAL3_TXPOLL_S: u32 = 0; +pub const USB_TXINTERVAL3_NAKLMT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +pub const USB_RXTYPE3_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_RXTYPE3_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_RXTYPE3_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_RXTYPE3_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_RXTYPE3_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_RXTYPE3_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_RXTYPE3_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_RXTYPE3_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_RXTYPE3_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_RXTYPE3_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_RXTYPE3_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +pub const USB_RXINTERVAL3_TXPOLL_M: u32 = 0x000000FF; // RX Polling +pub const USB_RXINTERVAL3_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_RXINTERVAL3_TXPOLL_S: u32 = 0; +pub const USB_RXINTERVAL3_NAKLMT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +pub const USB_TXMAXP4_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_TXMAXP4_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +pub const USB_TXCSRL4_NAKTO: u32 = 0x00000080; // NAK Timeout +pub const USB_TXCSRL4_CLRDT: u32 = 0x00000040; // Clear Data Toggle +pub const USB_TXCSRL4_STALLED: u32 = 0x00000020; // Endpoint Stalled +pub const USB_TXCSRL4_SETUP: u32 = 0x00000010; // Setup Packet +pub const USB_TXCSRL4_STALL: u32 = 0x00000010; // Send STALL +pub const USB_TXCSRL4_FLUSH: u32 = 0x00000008; // Flush FIFO +pub const USB_TXCSRL4_ERROR: u32 = 0x00000004; // Error +pub const USB_TXCSRL4_UNDRN: u32 = 0x00000004; // Underrun +pub const USB_TXCSRL4_FIFONE: u32 = 0x00000002; // FIFO Not Empty +pub const USB_TXCSRL4_TXRDY: u32 = 0x00000001; // Transmit Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +pub const USB_TXCSRH4_AUTOSET: u32 = 0x00000080; // Auto Set +pub const USB_TXCSRH4_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_TXCSRH4_MODE: u32 = 0x00000020; // Mode +pub const USB_TXCSRH4_DMAEN: u32 = 0x00000010; // DMA Request Enable +pub const USB_TXCSRH4_FDT: u32 = 0x00000008; // Force Data Toggle +pub const USB_TXCSRH4_DMAMOD: u32 = 0x00000004; // DMA Request Mode +pub const USB_TXCSRH4_DTWE: u32 = 0x00000002; // Data Toggle Write Enable +pub const USB_TXCSRH4_DT: u32 = 0x00000001; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +pub const USB_RXMAXP4_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_RXMAXP4_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +pub const USB_RXCSRL4_CLRDT: u32 = 0x00000080; // Clear Data Toggle +pub const USB_RXCSRL4_STALLED: u32 = 0x00000040; // Endpoint Stalled +pub const USB_RXCSRL4_STALL: u32 = 0x00000020; // Send STALL +pub const USB_RXCSRL4_REQPKT: u32 = 0x00000020; // Request Packet +pub const USB_RXCSRL4_FLUSH: u32 = 0x00000010; // Flush FIFO +pub const USB_RXCSRL4_NAKTO: u32 = 0x00000008; // NAK Timeout +pub const USB_RXCSRL4_DATAERR: u32 = 0x00000008; // Data Error +pub const USB_RXCSRL4_OVER: u32 = 0x00000004; // Overrun +pub const USB_RXCSRL4_ERROR: u32 = 0x00000004; // Error +pub const USB_RXCSRL4_FULL: u32 = 0x00000002; // FIFO Full +pub const USB_RXCSRL4_RXRDY: u32 = 0x00000001; // Receive Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +pub const USB_RXCSRH4_AUTOCL: u32 = 0x00000080; // Auto Clear +pub const USB_RXCSRH4_AUTORQ: u32 = 0x00000040; // Auto Request +pub const USB_RXCSRH4_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_RXCSRH4_DMAEN: u32 = 0x00000020; // DMA Request Enable +pub const USB_RXCSRH4_DISNYET: u32 = 0x00000010; // Disable NYET +pub const USB_RXCSRH4_PIDERR: u32 = 0x00000010; // PID Error +pub const USB_RXCSRH4_DMAMOD: u32 = 0x00000008; // DMA Request Mode +pub const USB_RXCSRH4_DTWE: u32 = 0x00000004; // Data Toggle Write Enable +pub const USB_RXCSRH4_DT: u32 = 0x00000002; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +pub const USB_RXCOUNT4_COUNT_M: u32 = 0x00001FFF; // Receive Packet Count +pub const USB_RXCOUNT4_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +pub const USB_TXTYPE4_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_TXTYPE4_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_TXTYPE4_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_TXTYPE4_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_TXTYPE4_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_TXTYPE4_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_TXTYPE4_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_TXTYPE4_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_TXTYPE4_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_TXTYPE4_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_TXTYPE4_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +pub const USB_TXINTERVAL4_TXPOLL_M: u32 = 0x000000FF; // TX Polling +pub const USB_TXINTERVAL4_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_TXINTERVAL4_NAKLMT_S: u32 = 0; +pub const USB_TXINTERVAL4_TXPOLL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +pub const USB_RXTYPE4_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_RXTYPE4_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_RXTYPE4_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_RXTYPE4_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_RXTYPE4_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_RXTYPE4_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_RXTYPE4_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_RXTYPE4_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_RXTYPE4_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_RXTYPE4_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_RXTYPE4_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +pub const USB_RXINTERVAL4_TXPOLL_M: u32 = 0x000000FF; // RX Polling +pub const USB_RXINTERVAL4_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_RXINTERVAL4_NAKLMT_S: u32 = 0; +pub const USB_RXINTERVAL4_TXPOLL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +pub const USB_TXMAXP5_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_TXMAXP5_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +pub const USB_TXCSRL5_NAKTO: u32 = 0x00000080; // NAK Timeout +pub const USB_TXCSRL5_CLRDT: u32 = 0x00000040; // Clear Data Toggle +pub const USB_TXCSRL5_STALLED: u32 = 0x00000020; // Endpoint Stalled +pub const USB_TXCSRL5_SETUP: u32 = 0x00000010; // Setup Packet +pub const USB_TXCSRL5_STALL: u32 = 0x00000010; // Send STALL +pub const USB_TXCSRL5_FLUSH: u32 = 0x00000008; // Flush FIFO +pub const USB_TXCSRL5_ERROR: u32 = 0x00000004; // Error +pub const USB_TXCSRL5_UNDRN: u32 = 0x00000004; // Underrun +pub const USB_TXCSRL5_FIFONE: u32 = 0x00000002; // FIFO Not Empty +pub const USB_TXCSRL5_TXRDY: u32 = 0x00000001; // Transmit Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +pub const USB_TXCSRH5_AUTOSET: u32 = 0x00000080; // Auto Set +pub const USB_TXCSRH5_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_TXCSRH5_MODE: u32 = 0x00000020; // Mode +pub const USB_TXCSRH5_DMAEN: u32 = 0x00000010; // DMA Request Enable +pub const USB_TXCSRH5_FDT: u32 = 0x00000008; // Force Data Toggle +pub const USB_TXCSRH5_DMAMOD: u32 = 0x00000004; // DMA Request Mode +pub const USB_TXCSRH5_DTWE: u32 = 0x00000002; // Data Toggle Write Enable +pub const USB_TXCSRH5_DT: u32 = 0x00000001; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +pub const USB_RXMAXP5_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_RXMAXP5_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +pub const USB_RXCSRL5_CLRDT: u32 = 0x00000080; // Clear Data Toggle +pub const USB_RXCSRL5_STALLED: u32 = 0x00000040; // Endpoint Stalled +pub const USB_RXCSRL5_STALL: u32 = 0x00000020; // Send STALL +pub const USB_RXCSRL5_REQPKT: u32 = 0x00000020; // Request Packet +pub const USB_RXCSRL5_FLUSH: u32 = 0x00000010; // Flush FIFO +pub const USB_RXCSRL5_NAKTO: u32 = 0x00000008; // NAK Timeout +pub const USB_RXCSRL5_DATAERR: u32 = 0x00000008; // Data Error +pub const USB_RXCSRL5_ERROR: u32 = 0x00000004; // Error +pub const USB_RXCSRL5_OVER: u32 = 0x00000004; // Overrun +pub const USB_RXCSRL5_FULL: u32 = 0x00000002; // FIFO Full +pub const USB_RXCSRL5_RXRDY: u32 = 0x00000001; // Receive Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +pub const USB_RXCSRH5_AUTOCL: u32 = 0x00000080; // Auto Clear +pub const USB_RXCSRH5_AUTORQ: u32 = 0x00000040; // Auto Request +pub const USB_RXCSRH5_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_RXCSRH5_DMAEN: u32 = 0x00000020; // DMA Request Enable +pub const USB_RXCSRH5_DISNYET: u32 = 0x00000010; // Disable NYET +pub const USB_RXCSRH5_PIDERR: u32 = 0x00000010; // PID Error +pub const USB_RXCSRH5_DMAMOD: u32 = 0x00000008; // DMA Request Mode +pub const USB_RXCSRH5_DTWE: u32 = 0x00000004; // Data Toggle Write Enable +pub const USB_RXCSRH5_DT: u32 = 0x00000002; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +pub const USB_RXCOUNT5_COUNT_M: u32 = 0x00001FFF; // Receive Packet Count +pub const USB_RXCOUNT5_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +pub const USB_TXTYPE5_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_TXTYPE5_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_TXTYPE5_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_TXTYPE5_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_TXTYPE5_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_TXTYPE5_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_TXTYPE5_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_TXTYPE5_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_TXTYPE5_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_TXTYPE5_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_TXTYPE5_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +pub const USB_TXINTERVAL5_TXPOLL_M: u32 = 0x000000FF; // TX Polling +pub const USB_TXINTERVAL5_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_TXINTERVAL5_NAKLMT_S: u32 = 0; +pub const USB_TXINTERVAL5_TXPOLL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +pub const USB_RXTYPE5_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_RXTYPE5_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_RXTYPE5_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_RXTYPE5_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_RXTYPE5_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_RXTYPE5_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_RXTYPE5_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_RXTYPE5_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_RXTYPE5_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_RXTYPE5_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_RXTYPE5_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +pub const USB_RXINTERVAL5_TXPOLL_M: u32 = 0x000000FF; // RX Polling +pub const USB_RXINTERVAL5_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_RXINTERVAL5_TXPOLL_S: u32 = 0; +pub const USB_RXINTERVAL5_NAKLMT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +pub const USB_TXMAXP6_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_TXMAXP6_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +pub const USB_TXCSRL6_NAKTO: u32 = 0x00000080; // NAK Timeout +pub const USB_TXCSRL6_CLRDT: u32 = 0x00000040; // Clear Data Toggle +pub const USB_TXCSRL6_STALLED: u32 = 0x00000020; // Endpoint Stalled +pub const USB_TXCSRL6_STALL: u32 = 0x00000010; // Send STALL +pub const USB_TXCSRL6_SETUP: u32 = 0x00000010; // Setup Packet +pub const USB_TXCSRL6_FLUSH: u32 = 0x00000008; // Flush FIFO +pub const USB_TXCSRL6_ERROR: u32 = 0x00000004; // Error +pub const USB_TXCSRL6_UNDRN: u32 = 0x00000004; // Underrun +pub const USB_TXCSRL6_FIFONE: u32 = 0x00000002; // FIFO Not Empty +pub const USB_TXCSRL6_TXRDY: u32 = 0x00000001; // Transmit Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +pub const USB_TXCSRH6_AUTOSET: u32 = 0x00000080; // Auto Set +pub const USB_TXCSRH6_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_TXCSRH6_MODE: u32 = 0x00000020; // Mode +pub const USB_TXCSRH6_DMAEN: u32 = 0x00000010; // DMA Request Enable +pub const USB_TXCSRH6_FDT: u32 = 0x00000008; // Force Data Toggle +pub const USB_TXCSRH6_DMAMOD: u32 = 0x00000004; // DMA Request Mode +pub const USB_TXCSRH6_DTWE: u32 = 0x00000002; // Data Toggle Write Enable +pub const USB_TXCSRH6_DT: u32 = 0x00000001; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +pub const USB_RXMAXP6_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_RXMAXP6_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +pub const USB_RXCSRL6_CLRDT: u32 = 0x00000080; // Clear Data Toggle +pub const USB_RXCSRL6_STALLED: u32 = 0x00000040; // Endpoint Stalled +pub const USB_RXCSRL6_REQPKT: u32 = 0x00000020; // Request Packet +pub const USB_RXCSRL6_STALL: u32 = 0x00000020; // Send STALL +pub const USB_RXCSRL6_FLUSH: u32 = 0x00000010; // Flush FIFO +pub const USB_RXCSRL6_NAKTO: u32 = 0x00000008; // NAK Timeout +pub const USB_RXCSRL6_DATAERR: u32 = 0x00000008; // Data Error +pub const USB_RXCSRL6_ERROR: u32 = 0x00000004; // Error +pub const USB_RXCSRL6_OVER: u32 = 0x00000004; // Overrun +pub const USB_RXCSRL6_FULL: u32 = 0x00000002; // FIFO Full +pub const USB_RXCSRL6_RXRDY: u32 = 0x00000001; // Receive Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +pub const USB_RXCSRH6_AUTOCL: u32 = 0x00000080; // Auto Clear +pub const USB_RXCSRH6_AUTORQ: u32 = 0x00000040; // Auto Request +pub const USB_RXCSRH6_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_RXCSRH6_DMAEN: u32 = 0x00000020; // DMA Request Enable +pub const USB_RXCSRH6_DISNYET: u32 = 0x00000010; // Disable NYET +pub const USB_RXCSRH6_PIDERR: u32 = 0x00000010; // PID Error +pub const USB_RXCSRH6_DMAMOD: u32 = 0x00000008; // DMA Request Mode +pub const USB_RXCSRH6_DTWE: u32 = 0x00000004; // Data Toggle Write Enable +pub const USB_RXCSRH6_DT: u32 = 0x00000002; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +pub const USB_RXCOUNT6_COUNT_M: u32 = 0x00001FFF; // Receive Packet Count +pub const USB_RXCOUNT6_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +pub const USB_TXTYPE6_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_TXTYPE6_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_TXTYPE6_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_TXTYPE6_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_TXTYPE6_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_TXTYPE6_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_TXTYPE6_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_TXTYPE6_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_TXTYPE6_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_TXTYPE6_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_TXTYPE6_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +pub const USB_TXINTERVAL6_TXPOLL_M: u32 = 0x000000FF; // TX Polling +pub const USB_TXINTERVAL6_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_TXINTERVAL6_TXPOLL_S: u32 = 0; +pub const USB_TXINTERVAL6_NAKLMT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +pub const USB_RXTYPE6_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_RXTYPE6_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_RXTYPE6_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_RXTYPE6_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_RXTYPE6_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_RXTYPE6_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_RXTYPE6_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_RXTYPE6_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_RXTYPE6_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_RXTYPE6_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_RXTYPE6_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +pub const USB_RXINTERVAL6_TXPOLL_M: u32 = 0x000000FF; // RX Polling +pub const USB_RXINTERVAL6_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_RXINTERVAL6_NAKLMT_S: u32 = 0; +pub const USB_RXINTERVAL6_TXPOLL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +pub const USB_TXMAXP7_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_TXMAXP7_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +pub const USB_TXCSRL7_NAKTO: u32 = 0x00000080; // NAK Timeout +pub const USB_TXCSRL7_CLRDT: u32 = 0x00000040; // Clear Data Toggle +pub const USB_TXCSRL7_STALLED: u32 = 0x00000020; // Endpoint Stalled +pub const USB_TXCSRL7_STALL: u32 = 0x00000010; // Send STALL +pub const USB_TXCSRL7_SETUP: u32 = 0x00000010; // Setup Packet +pub const USB_TXCSRL7_FLUSH: u32 = 0x00000008; // Flush FIFO +pub const USB_TXCSRL7_ERROR: u32 = 0x00000004; // Error +pub const USB_TXCSRL7_UNDRN: u32 = 0x00000004; // Underrun +pub const USB_TXCSRL7_FIFONE: u32 = 0x00000002; // FIFO Not Empty +pub const USB_TXCSRL7_TXRDY: u32 = 0x00000001; // Transmit Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +pub const USB_TXCSRH7_AUTOSET: u32 = 0x00000080; // Auto Set +pub const USB_TXCSRH7_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_TXCSRH7_MODE: u32 = 0x00000020; // Mode +pub const USB_TXCSRH7_DMAEN: u32 = 0x00000010; // DMA Request Enable +pub const USB_TXCSRH7_FDT: u32 = 0x00000008; // Force Data Toggle +pub const USB_TXCSRH7_DMAMOD: u32 = 0x00000004; // DMA Request Mode +pub const USB_TXCSRH7_DTWE: u32 = 0x00000002; // Data Toggle Write Enable +pub const USB_TXCSRH7_DT: u32 = 0x00000001; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +pub const USB_RXMAXP7_MAXLOAD_M: u32 = 0x000007FF; // Maximum Payload +pub const USB_RXMAXP7_MAXLOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +pub const USB_RXCSRL7_CLRDT: u32 = 0x00000080; // Clear Data Toggle +pub const USB_RXCSRL7_STALLED: u32 = 0x00000040; // Endpoint Stalled +pub const USB_RXCSRL7_REQPKT: u32 = 0x00000020; // Request Packet +pub const USB_RXCSRL7_STALL: u32 = 0x00000020; // Send STALL +pub const USB_RXCSRL7_FLUSH: u32 = 0x00000010; // Flush FIFO +pub const USB_RXCSRL7_DATAERR: u32 = 0x00000008; // Data Error +pub const USB_RXCSRL7_NAKTO: u32 = 0x00000008; // NAK Timeout +pub const USB_RXCSRL7_ERROR: u32 = 0x00000004; // Error +pub const USB_RXCSRL7_OVER: u32 = 0x00000004; // Overrun +pub const USB_RXCSRL7_FULL: u32 = 0x00000002; // FIFO Full +pub const USB_RXCSRL7_RXRDY: u32 = 0x00000001; // Receive Packet Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +pub const USB_RXCSRH7_AUTOCL: u32 = 0x00000080; // Auto Clear +pub const USB_RXCSRH7_ISO: u32 = 0x00000040; // Isochronous Transfers +pub const USB_RXCSRH7_AUTORQ: u32 = 0x00000040; // Auto Request +pub const USB_RXCSRH7_DMAEN: u32 = 0x00000020; // DMA Request Enable +pub const USB_RXCSRH7_PIDERR: u32 = 0x00000010; // PID Error +pub const USB_RXCSRH7_DISNYET: u32 = 0x00000010; // Disable NYET +pub const USB_RXCSRH7_DMAMOD: u32 = 0x00000008; // DMA Request Mode +pub const USB_RXCSRH7_DTWE: u32 = 0x00000004; // Data Toggle Write Enable +pub const USB_RXCSRH7_DT: u32 = 0x00000002; // Data Toggle +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +pub const USB_RXCOUNT7_COUNT_M: u32 = 0x00001FFF; // Receive Packet Count +pub const USB_RXCOUNT7_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +pub const USB_TXTYPE7_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_TXTYPE7_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_TXTYPE7_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_TXTYPE7_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_TXTYPE7_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_TXTYPE7_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_TXTYPE7_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_TXTYPE7_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_TXTYPE7_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_TXTYPE7_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_TXTYPE7_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +pub const USB_TXINTERVAL7_TXPOLL_M: u32 = 0x000000FF; // TX Polling +pub const USB_TXINTERVAL7_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_TXINTERVAL7_NAKLMT_S: u32 = 0; +pub const USB_TXINTERVAL7_TXPOLL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +pub const USB_RXTYPE7_SPEED_M: u32 = 0x000000C0; // Operating Speed +pub const USB_RXTYPE7_SPEED_DFLT: u32 = 0x00000000; // Default +pub const USB_RXTYPE7_SPEED_FULL: u32 = 0x00000080; // Full +pub const USB_RXTYPE7_SPEED_LOW: u32 = 0x000000C0; // Low +pub const USB_RXTYPE7_PROTO_M: u32 = 0x00000030; // Protocol +pub const USB_RXTYPE7_PROTO_CTRL: u32 = 0x00000000; // Control +pub const USB_RXTYPE7_PROTO_ISOC: u32 = 0x00000010; // Isochronous +pub const USB_RXTYPE7_PROTO_BULK: u32 = 0x00000020; // Bulk +pub const USB_RXTYPE7_PROTO_INT: u32 = 0x00000030; // Interrupt +pub const USB_RXTYPE7_TEP_M: u32 = 0x0000000F; // Target Endpoint Number +pub const USB_RXTYPE7_TEP_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +pub const USB_RXINTERVAL7_TXPOLL_M: u32 = 0x000000FF; // RX Polling +pub const USB_RXINTERVAL7_NAKLMT_M: u32 = 0x000000FF; // NAK Limit +pub const USB_RXINTERVAL7_NAKLMT_S: u32 = 0; +pub const USB_RXINTERVAL7_TXPOLL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +pub const USB_RQPKTCOUNT1_M: u32 = 0x0000FFFF; // Block Transfer Packet Count +pub const USB_RQPKTCOUNT1_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +pub const USB_RQPKTCOUNT2_M: u32 = 0x0000FFFF; // Block Transfer Packet Count +pub const USB_RQPKTCOUNT2_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +pub const USB_RQPKTCOUNT3_M: u32 = 0x0000FFFF; // Block Transfer Packet Count +pub const USB_RQPKTCOUNT3_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +pub const USB_RQPKTCOUNT4_COUNT_M: u32 = 0x0000FFFF; // Block Transfer Packet Count +pub const USB_RQPKTCOUNT4_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +pub const USB_RQPKTCOUNT5_COUNT_M: u32 = 0x0000FFFF; // Block Transfer Packet Count +pub const USB_RQPKTCOUNT5_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +pub const USB_RQPKTCOUNT6_COUNT_M: u32 = 0x0000FFFF; // Block Transfer Packet Count +pub const USB_RQPKTCOUNT6_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +pub const USB_RQPKTCOUNT7_COUNT_M: u32 = 0x0000FFFF; // Block Transfer Packet Count +pub const USB_RQPKTCOUNT7_COUNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +pub const USB_RXDPKTBUFDIS_EP7: u32 = 0x00000080; // EP7 RX Double-Packet Buffer + // Disable +pub const USB_RXDPKTBUFDIS_EP6: u32 = 0x00000040; // EP6 RX Double-Packet Buffer + // Disable +pub const USB_RXDPKTBUFDIS_EP5: u32 = 0x00000020; // EP5 RX Double-Packet Buffer + // Disable +pub const USB_RXDPKTBUFDIS_EP4: u32 = 0x00000010; // EP4 RX Double-Packet Buffer + // Disable +pub const USB_RXDPKTBUFDIS_EP3: u32 = 0x00000008; // EP3 RX Double-Packet Buffer + // Disable +pub const USB_RXDPKTBUFDIS_EP2: u32 = 0x00000004; // EP2 RX Double-Packet Buffer + // Disable +pub const USB_RXDPKTBUFDIS_EP1: u32 = 0x00000002; // EP1 RX Double-Packet Buffer + // Disable +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +pub const USB_TXDPKTBUFDIS_EP7: u32 = 0x00000080; // EP7 TX Double-Packet Buffer + // Disable +pub const USB_TXDPKTBUFDIS_EP6: u32 = 0x00000040; // EP6 TX Double-Packet Buffer + // Disable +pub const USB_TXDPKTBUFDIS_EP5: u32 = 0x00000020; // EP5 TX Double-Packet Buffer + // Disable +pub const USB_TXDPKTBUFDIS_EP4: u32 = 0x00000010; // EP4 TX Double-Packet Buffer + // Disable +pub const USB_TXDPKTBUFDIS_EP3: u32 = 0x00000008; // EP3 TX Double-Packet Buffer + // Disable +pub const USB_TXDPKTBUFDIS_EP2: u32 = 0x00000004; // EP2 TX Double-Packet Buffer + // Disable +pub const USB_TXDPKTBUFDIS_EP1: u32 = 0x00000002; // EP1 TX Double-Packet Buffer + // Disable +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +pub const USB_EPC_PFLTACT_M: u32 = 0x00000300; // Power Fault Action +pub const USB_EPC_PFLTACT_UNCHG: u32 = 0x00000000; // Unchanged +pub const USB_EPC_PFLTACT_TRIS: u32 = 0x00000100; // Tristate +pub const USB_EPC_PFLTACT_LOW: u32 = 0x00000200; // Low +pub const USB_EPC_PFLTACT_HIGH: u32 = 0x00000300; // High +pub const USB_EPC_PFLTAEN: u32 = 0x00000040; // Power Fault Action Enable +pub const USB_EPC_PFLTSEN_HIGH: u32 = 0x00000020; // Power Fault Sense +pub const USB_EPC_PFLTEN: u32 = 0x00000010; // Power Fault Input Enable +pub const USB_EPC_EPENDE: u32 = 0x00000004; // EPEN Drive Enable +pub const USB_EPC_EPEN_M: u32 = 0x00000003; // External Power Supply Enable + // Configuration +pub const USB_EPC_EPEN_LOW: u32 = 0x00000000; // Power Enable Active Low +pub const USB_EPC_EPEN_HIGH: u32 = 0x00000001; // Power Enable Active High +pub const USB_EPC_EPEN_VBLOW: u32 = 0x00000002; // Power Enable High if VBUS Low + // (OTG only) +pub const USB_EPC_EPEN_VBHIGH: u32 = 0x00000003; // Power Enable High if VBUS High + // (OTG only) +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +pub const USB_EPCRIS_PF: u32 = 0x00000001; // USB Power Fault Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +pub const USB_EPCIM_PF: u32 = 0x00000001; // USB Power Fault Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +pub const USB_EPCISC_PF: u32 = 0x00000001; // USB Power Fault Interrupt Status + // and Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +pub const USB_DRRIS_RESUME: u32 = 0x00000001; // RESUME Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +pub const USB_DRIM_RESUME: u32 = 0x00000001; // RESUME Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +pub const USB_DRISC_RESUME: u32 = 0x00000001; // RESUME Interrupt Status and + // Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +pub const USB_GPCS_DEVMODOTG: u32 = 0x00000002; // Enable Device Mode +pub const USB_GPCS_DEVMOD: u32 = 0x00000001; // Device Mode +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +pub const USB_VDC_VBDEN: u32 = 0x00000001; // VBUS Droop Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +pub const USB_VDCRIS_VD: u32 = 0x00000001; // VBUS Droop Raw Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +pub const USB_VDCIM_VD: u32 = 0x00000001; // VBUS Droop Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +pub const USB_VDCISC_VD: u32 = 0x00000001; // VBUS Droop Interrupt Status and + // Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +pub const USB_IDVRIS_ID: u32 = 0x00000001; // ID Valid Detect Raw Interrupt + // Status +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +pub const USB_IDVIM_ID: u32 = 0x00000001; // ID Valid Detect Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +pub const USB_IDVISC_ID: u32 = 0x00000001; // ID Valid Detect Interrupt Status + // and Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +pub const USB_DMASEL_DMACTX_M: u32 = 0x00F00000; // DMA C TX Select +pub const USB_DMASEL_DMACRX_M: u32 = 0x000F0000; // DMA C RX Select +pub const USB_DMASEL_DMABTX_M: u32 = 0x0000F000; // DMA B TX Select +pub const USB_DMASEL_DMABRX_M: u32 = 0x00000F00; // DMA B RX Select +pub const USB_DMASEL_DMAATX_M: u32 = 0x000000F0; // DMA A TX Select +pub const USB_DMASEL_DMAARX_M: u32 = 0x0000000F; // DMA A RX Select +pub const USB_DMASEL_DMACTX_S: u32 = 20; +pub const USB_DMASEL_DMACRX_S: u32 = 16; +pub const USB_DMASEL_DMABTX_S: u32 = 12; +pub const USB_DMASEL_DMABRX_S: u32 = 8; +pub const USB_DMASEL_DMAATX_S: u32 = 4; +pub const USB_DMASEL_DMAARX_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +pub const USB_PP_ECNT_M: u32 = 0x0000FF00; // Endpoint Count +pub const USB_PP_USB_M: u32 = 0x000000C0; // USB Capability +pub const USB_PP_USB_DEVICE: u32 = 0x00000040; // DEVICE +pub const USB_PP_USB_HOSTDEVICE: u32 = 0x00000080; // HOST +pub const USB_PP_USB_OTG: u32 = 0x000000C0; // OTG +pub const USB_PP_PHY: u32 = 0x00000010; // PHY Present +pub const USB_PP_TYPE_M: u32 = 0x0000000F; // Controller Type +pub const USB_PP_TYPE_0: u32 = 0x00000000; // The first-generation USB + // controller +pub const USB_PP_ECNT_S: u32 = 8; +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESIZE register. +// +//***************************************************************************** +pub const EEPROM_EESIZE_BLKCNT_M: u32 = 0x07FF0000; // Number of 16-Word Blocks +pub const EEPROM_EESIZE_WORDCNT_M: u32 = 0x0000FFFF; // Number of 32-Bit Words +pub const EEPROM_EESIZE_BLKCNT_S: u32 = 16; +pub const EEPROM_EESIZE_WORDCNT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEBLOCK register. +// +//***************************************************************************** +pub const EEPROM_EEBLOCK_BLOCK_M: u32 = 0x0000FFFF; // Current Block +pub const EEPROM_EEBLOCK_BLOCK_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEOFFSET +// register. +// +//***************************************************************************** +pub const EEPROM_EEOFFSET_OFFSET_M: u32 = 0x0000000F; // Current Address Offset +pub const EEPROM_EEOFFSET_OFFSET_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWR register. +// +//***************************************************************************** +pub const EEPROM_EERDWR_VALUE_M: u32 = 0xFFFFFFFF; // EEPROM Read or Write Data +pub const EEPROM_EERDWR_VALUE_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWRINC +// register. +// +//***************************************************************************** +pub const EEPROM_EERDWRINC_VALUE_M: u32 = 0xFFFFFFFF; // EEPROM Read or Write Data with + // Increment +pub const EEPROM_EERDWRINC_VALUE_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDONE register. +// +//***************************************************************************** +pub const EEPROM_EEDONE_WRBUSY: u32 = 0x00000020; // Write Busy +pub const EEPROM_EEDONE_NOPERM: u32 = 0x00000010; // Write Without Permission +pub const EEPROM_EEDONE_WKCOPY: u32 = 0x00000008; // Working on a Copy +pub const EEPROM_EEDONE_WKERASE: u32 = 0x00000004; // Working on an Erase +pub const EEPROM_EEDONE_WORKING: u32 = 0x00000001; // EEPROM Working +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESUPP register. +// +//***************************************************************************** +pub const EEPROM_EESUPP_PRETRY: u32 = 0x00000008; // Programming Must Be Retried +pub const EEPROM_EESUPP_ERETRY: u32 = 0x00000004; // Erase Must Be Retried +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEUNLOCK +// register. +// +//***************************************************************************** +pub const EEPROM_EEUNLOCK_UNLOCK_M: u32 = 0xFFFFFFFF; // EEPROM Unlock +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPROT register. +// +//***************************************************************************** +pub const EEPROM_EEPROT_ACC: u32 = 0x00000008; // Access Control +pub const EEPROM_EEPROT_PROT_M: u32 = 0x00000007; // Protection Control +pub const EEPROM_EEPROT_PROT_RWNPW: u32 = 0x00000000; // This setting is the default. If + // there is no password, the block + // is not protected and is readable + // and writable +pub const EEPROM_EEPROT_PROT_RWPW: u32 = 0x00000001; // If there is a password, the + // block is readable or writable + // only when unlocked +pub const EEPROM_EEPROT_PROT_RONPW: u32 = 0x00000002; // If there is no password, the + // block is readable, not writable +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS0 register. +// +//***************************************************************************** +pub const EEPROM_EEPASS0_PASS_M: u32 = 0xFFFFFFFF; // Password +pub const EEPROM_EEPASS0_PASS_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS1 register. +// +//***************************************************************************** +pub const EEPROM_EEPASS1_PASS_M: u32 = 0xFFFFFFFF; // Password +pub const EEPROM_EEPASS1_PASS_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS2 register. +// +//***************************************************************************** +pub const EEPROM_EEPASS2_PASS_M: u32 = 0xFFFFFFFF; // Password +pub const EEPROM_EEPASS2_PASS_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEINT register. +// +//***************************************************************************** +pub const EEPROM_EEINT_INT: u32 = 0x00000001; // Interrupt Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE register. +// +//***************************************************************************** +pub const EEPROM_EEHIDE_HN_M: u32 = 0xFFFFFFFE; // Hide Block +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDBGME register. +// +//***************************************************************************** +pub const EEPROM_EEDBGME_KEY_M: u32 = 0xFFFF0000; // Erase Key +pub const EEPROM_EEDBGME_ME: u32 = 0x00000001; // Mass Erase +pub const EEPROM_EEDBGME_KEY_S: u32 = 16; +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_PP register. +// +//***************************************************************************** +pub const EEPROM_PP_SIZE_M: u32 = 0x0000001F; // EEPROM Size +pub const EEPROM_PP_SIZE_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_RIS register. +// +//***************************************************************************** +pub const SYSEXC_RIS_FPIXCRIS: u32 = 0x00000020; // Floating-Point Inexact Exception + // Raw Interrupt Status +pub const SYSEXC_RIS_FPOFCRIS: u32 = 0x00000010; // Floating-Point Overflow + // Exception Raw Interrupt Status +pub const SYSEXC_RIS_FPUFCRIS: u32 = 0x00000008; // Floating-Point Underflow + // Exception Raw Interrupt Status +pub const SYSEXC_RIS_FPIOCRIS: u32 = 0x00000004; // Floating-Point Invalid Operation + // Raw Interrupt Status +pub const SYSEXC_RIS_FPDZCRIS: u32 = 0x00000002; // Floating-Point Divide By 0 + // Exception Raw Interrupt Status +pub const SYSEXC_RIS_FPIDCRIS: u32 = 0x00000001; // Floating-Point Input Denormal + // Exception Raw Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IM register. +// +//***************************************************************************** +pub const SYSEXC_IM_FPIXCIM: u32 = 0x00000020; // Floating-Point Inexact Exception + // Interrupt Mask +pub const SYSEXC_IM_FPOFCIM: u32 = 0x00000010; // Floating-Point Overflow + // Exception Interrupt Mask +pub const SYSEXC_IM_FPUFCIM: u32 = 0x00000008; // Floating-Point Underflow + // Exception Interrupt Mask +pub const SYSEXC_IM_FPIOCIM: u32 = 0x00000004; // Floating-Point Invalid Operation + // Interrupt Mask +pub const SYSEXC_IM_FPDZCIM: u32 = 0x00000002; // Floating-Point Divide By 0 + // Exception Interrupt Mask +pub const SYSEXC_IM_FPIDCIM: u32 = 0x00000001; // Floating-Point Input Denormal + // Exception Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_MIS register. +// +//***************************************************************************** +pub const SYSEXC_MIS_FPIXCMIS: u32 = 0x00000020; // Floating-Point Inexact Exception + // Masked Interrupt Status +pub const SYSEXC_MIS_FPOFCMIS: u32 = 0x00000010; // Floating-Point Overflow + // Exception Masked Interrupt + // Status +pub const SYSEXC_MIS_FPUFCMIS: u32 = 0x00000008; // Floating-Point Underflow + // Exception Masked Interrupt + // Status +pub const SYSEXC_MIS_FPIOCMIS: u32 = 0x00000004; // Floating-Point Invalid Operation + // Masked Interrupt Status +pub const SYSEXC_MIS_FPDZCMIS: u32 = 0x00000002; // Floating-Point Divide By 0 + // Exception Masked Interrupt + // Status +pub const SYSEXC_MIS_FPIDCMIS: u32 = 0x00000001; // Floating-Point Input Denormal + // Exception Masked Interrupt + // Status +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IC register. +// +//***************************************************************************** +pub const SYSEXC_IC_FPIXCIC: u32 = 0x00000020; // Floating-Point Inexact Exception + // Interrupt Clear +pub const SYSEXC_IC_FPOFCIC: u32 = 0x00000010; // Floating-Point Overflow + // Exception Interrupt Clear +pub const SYSEXC_IC_FPUFCIC: u32 = 0x00000008; // Floating-Point Underflow + // Exception Interrupt Clear +pub const SYSEXC_IC_FPIOCIC: u32 = 0x00000004; // Floating-Point Invalid Operation + // Interrupt Clear +pub const SYSEXC_IC_FPDZCIC: u32 = 0x00000002; // Floating-Point Divide By 0 + // Exception Interrupt Clear +pub const SYSEXC_IC_FPIDCIC: u32 = 0x00000001; // Floating-Point Input Denormal + // Exception Interrupt Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCC register. +// +//***************************************************************************** +pub const HIB_RTCC_M: u32 = 0xFFFFFFFF; // RTC Counter +pub const HIB_RTCC_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCM0 register. +// +//***************************************************************************** +pub const HIB_RTCM0_M: u32 = 0xFFFFFFFF; // RTC Match 0 +pub const HIB_RTCM0_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCLD register. +// +//***************************************************************************** +pub const HIB_RTCLD_M: u32 = 0xFFFFFFFF; // RTC Load +pub const HIB_RTCLD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CTL register. +// +//***************************************************************************** +pub const HIB_CTL_WRC: u32 = 0x80000000; // Write Complete/Capable +pub const HIB_CTL_OSCDRV: u32 = 0x00020000; // Oscillator Drive Capability +pub const HIB_CTL_OSCBYP: u32 = 0x00010000; // Oscillator Bypass +pub const HIB_CTL_VBATSEL_M: u32 = 0x00006000; // Select for Low-Battery + // Comparator +pub const HIB_CTL_VBATSEL_1_9V: u32 = 0x00000000; // 1.9 Volts +pub const HIB_CTL_VBATSEL_2_1V: u32 = 0x00002000; // 2.1 Volts (default) +pub const HIB_CTL_VBATSEL_2_3V: u32 = 0x00004000; // 2.3 Volts +pub const HIB_CTL_VBATSEL_2_5V: u32 = 0x00006000; // 2.5 Volts +pub const HIB_CTL_BATCHK: u32 = 0x00000400; // Check Battery Status +pub const HIB_CTL_BATWKEN: u32 = 0x00000200; // Wake on Low Battery +pub const HIB_CTL_VDD3ON: u32 = 0x00000100; // VDD Powered +pub const HIB_CTL_VABORT: u32 = 0x00000080; // Power Cut Abort Enable +pub const HIB_CTL_CLK32EN: u32 = 0x00000040; // Clocking Enable +pub const HIB_CTL_PINWEN: u32 = 0x00000010; // External Wake Pin Enable +pub const HIB_CTL_RTCWEN: u32 = 0x00000008; // RTC Wake-up Enable +pub const HIB_CTL_HIBREQ: u32 = 0x00000002; // Hibernation Request +pub const HIB_CTL_RTCEN: u32 = 0x00000001; // RTC Timer Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IM register. +// +//***************************************************************************** +pub const HIB_IM_WC: u32 = 0x00000010; // External Write Complete/Capable + // Interrupt Mask +pub const HIB_IM_EXTW: u32 = 0x00000008; // External Wake-Up Interrupt Mask +pub const HIB_IM_LOWBAT: u32 = 0x00000004; // Low Battery Voltage Interrupt + // Mask +pub const HIB_IM_RTCALT0: u32 = 0x00000001; // RTC Alert 0 Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RIS register. +// +//***************************************************************************** +pub const HIB_RIS_WC: u32 = 0x00000010; // Write Complete/Capable Raw + // Interrupt Status +pub const HIB_RIS_EXTW: u32 = 0x00000008; // External Wake-Up Raw Interrupt + // Status +pub const HIB_RIS_LOWBAT: u32 = 0x00000004; // Low Battery Voltage Raw + // Interrupt Status +pub const HIB_RIS_RTCALT0: u32 = 0x00000001; // RTC Alert 0 Raw Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_MIS register. +// +//***************************************************************************** +pub const HIB_MIS_WC: u32 = 0x00000010; // Write Complete/Capable Masked + // Interrupt Status +pub const HIB_MIS_EXTW: u32 = 0x00000008; // External Wake-Up Masked + // Interrupt Status +pub const HIB_MIS_LOWBAT: u32 = 0x00000004; // Low Battery Voltage Masked + // Interrupt Status +pub const HIB_MIS_RTCALT0: u32 = 0x00000001; // RTC Alert 0 Masked Interrupt + // Status +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IC register. +// +//***************************************************************************** +pub const HIB_IC_WC: u32 = 0x00000010; // Write Complete/Capable Interrupt + // Clear +pub const HIB_IC_EXTW: u32 = 0x00000008; // External Wake-Up Interrupt Clear +pub const HIB_IC_LOWBAT: u32 = 0x00000004; // Low Battery Voltage Interrupt + // Clear +pub const HIB_IC_RTCALT0: u32 = 0x00000001; // RTC Alert0 Masked Interrupt + // Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCT register. +// +//***************************************************************************** +pub const HIB_RTCT_TRIM_M: u32 = 0x0000FFFF; // RTC Trim Value +pub const HIB_RTCT_TRIM_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCSS register. +// +//***************************************************************************** +pub const HIB_RTCSS_RTCSSM_M: u32 = 0x7FFF0000; // RTC Sub Seconds Match +pub const HIB_RTCSS_RTCSSC_M: u32 = 0x00007FFF; // RTC Sub Seconds Count +pub const HIB_RTCSS_RTCSSM_S: u32 = 16; +pub const HIB_RTCSS_RTCSSC_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_DATA register. +// +//***************************************************************************** +pub const HIB_DATA_RTD_M: u32 = 0xFFFFFFFF; // Hibernation Module NV Data +pub const HIB_DATA_RTD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMA register. +// +//***************************************************************************** +pub const FLASH_FMA_OFFSET_M: u32 = 0x0003FFFF; // Address Offset +pub const FLASH_FMA_OFFSET_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMD register. +// +//***************************************************************************** +pub const FLASH_FMD_DATA_M: u32 = 0xFFFFFFFF; // Data Value +pub const FLASH_FMD_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +pub const FLASH_FMC_WRKEY: u32 = 0xA4420000; // FLASH write key +pub const FLASH_FMC_COMT: u32 = 0x00000008; // Commit Register Value +pub const FLASH_FMC_MERASE: u32 = 0x00000004; // Mass Erase Flash Memory +pub const FLASH_FMC_ERASE: u32 = 0x00000002; // Erase a Page of Flash Memory +pub const FLASH_FMC_WRITE: u32 = 0x00000001; // Write a Word into Flash Memory +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +pub const FLASH_FCRIS_PROGRIS: u32 = 0x00002000; // Program Verify Error Raw + // Interrupt Status +pub const FLASH_FCRIS_ERRIS: u32 = 0x00000800; // Erase Verify Error Raw Interrupt + // Status +pub const FLASH_FCRIS_INVDRIS: u32 = 0x00000400; // Invalid Data Raw Interrupt + // Status +pub const FLASH_FCRIS_VOLTRIS: u32 = 0x00000200; // Pump Voltage Raw Interrupt + // Status +pub const FLASH_FCRIS_ERIS: u32 = 0x00000004; // EEPROM Raw Interrupt Status +pub const FLASH_FCRIS_PRIS: u32 = 0x00000002; // Programming Raw Interrupt Status +pub const FLASH_FCRIS_ARIS: u32 = 0x00000001; // Access Raw Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +pub const FLASH_FCIM_PROGMASK: u32 = 0x00002000; // PROGVER Interrupt Mask +pub const FLASH_FCIM_ERMASK: u32 = 0x00000800; // ERVER Interrupt Mask +pub const FLASH_FCIM_INVDMASK: u32 = 0x00000400; // Invalid Data Interrupt Mask +pub const FLASH_FCIM_VOLTMASK: u32 = 0x00000200; // VOLT Interrupt Mask +pub const FLASH_FCIM_EMASK: u32 = 0x00000004; // EEPROM Interrupt Mask +pub const FLASH_FCIM_PMASK: u32 = 0x00000002; // Programming Interrupt Mask +pub const FLASH_FCIM_AMASK: u32 = 0x00000001; // Access Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCMISC register. +// +//***************************************************************************** +pub const FLASH_FCMISC_PROGMISC: u32 = 0x00002000; // PROGVER Masked Interrupt Status + // and Clear +pub const FLASH_FCMISC_ERMISC: u32 = 0x00000800; // ERVER Masked Interrupt Status + // and Clear +pub const FLASH_FCMISC_INVDMISC: u32 = 0x00000400; // Invalid Data Masked Interrupt + // Status and Clear +pub const FLASH_FCMISC_VOLTMISC: u32 = 0x00000200; // VOLT Masked Interrupt Status and + // Clear +pub const FLASH_FCMISC_EMISC: u32 = 0x00000004; // EEPROM Masked Interrupt Status + // and Clear +pub const FLASH_FCMISC_PMISC: u32 = 0x00000002; // Programming Masked Interrupt + // Status and Clear +pub const FLASH_FCMISC_AMISC: u32 = 0x00000001; // Access Masked Interrupt Status + // and Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC2 register. +// +//***************************************************************************** +pub const FLASH_FMC2_WRBUF: u32 = 0x00000001; // Buffered Flash Memory Write +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBVAL register. +// +//***************************************************************************** +pub const FLASH_FWBVAL_FWB_M: u32 = 0xFFFFFFFF; // Flash Memory Write Buffer +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBN register. +// +//***************************************************************************** +pub const FLASH_FWBN_DATA_M: u32 = 0xFFFFFFFF; // Data +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FSIZE register. +// +//***************************************************************************** +pub const FLASH_FSIZE_SIZE_M: u32 = 0x0000FFFF; // Flash Size +pub const FLASH_FSIZE_SIZE_256KB: u32 = 0x0000007F; // 256 KB of Flash +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_SSIZE register. +// +//***************************************************************************** +pub const FLASH_SSIZE_SIZE_M: u32 = 0x0000FFFF; // SRAM Size +pub const FLASH_SSIZE_SIZE_32KB: u32 = 0x0000007F; // 32 KB of SRAM +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_ROMSWMAP register. +// +//***************************************************************************** +pub const FLASH_ROMSWMAP_SAFERTOS: u32 = 0x00000001; // SafeRTOS Present +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RMCTL register. +// +//***************************************************************************** +pub const FLASH_RMCTL_BA: u32 = 0x00000001; // Boot Alias +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_BOOTCFG register. +// +//***************************************************************************** +pub const FLASH_BOOTCFG_NW: u32 = 0x80000000; // Not Written +pub const FLASH_BOOTCFG_PORT_M: u32 = 0x0000E000; // Boot GPIO Port +pub const FLASH_BOOTCFG_PORT_A: u32 = 0x00000000; // Port A +pub const FLASH_BOOTCFG_PORT_B: u32 = 0x00002000; // Port B +pub const FLASH_BOOTCFG_PORT_C: u32 = 0x00004000; // Port C +pub const FLASH_BOOTCFG_PORT_D: u32 = 0x00006000; // Port D +pub const FLASH_BOOTCFG_PORT_E: u32 = 0x00008000; // Port E +pub const FLASH_BOOTCFG_PORT_F: u32 = 0x0000A000; // Port F +pub const FLASH_BOOTCFG_PORT_G: u32 = 0x0000C000; // Port G +pub const FLASH_BOOTCFG_PORT_H: u32 = 0x0000E000; // Port H +pub const FLASH_BOOTCFG_PIN_M: u32 = 0x00001C00; // Boot GPIO Pin +pub const FLASH_BOOTCFG_PIN_0: u32 = 0x00000000; // Pin 0 +pub const FLASH_BOOTCFG_PIN_1: u32 = 0x00000400; // Pin 1 +pub const FLASH_BOOTCFG_PIN_2: u32 = 0x00000800; // Pin 2 +pub const FLASH_BOOTCFG_PIN_3: u32 = 0x00000C00; // Pin 3 +pub const FLASH_BOOTCFG_PIN_4: u32 = 0x00001000; // Pin 4 +pub const FLASH_BOOTCFG_PIN_5: u32 = 0x00001400; // Pin 5 +pub const FLASH_BOOTCFG_PIN_6: u32 = 0x00001800; // Pin 6 +pub const FLASH_BOOTCFG_PIN_7: u32 = 0x00001C00; // Pin 7 +pub const FLASH_BOOTCFG_POL: u32 = 0x00000200; // Boot GPIO Polarity +pub const FLASH_BOOTCFG_EN: u32 = 0x00000100; // Boot GPIO Enable +pub const FLASH_BOOTCFG_KEY: u32 = 0x00000010; // KEY Select +pub const FLASH_BOOTCFG_DBG1: u32 = 0x00000002; // Debug Control 1 +pub const FLASH_BOOTCFG_DBG0: u32 = 0x00000001; // Debug Control 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG0 register. +// +//***************************************************************************** +pub const FLASH_USERREG0_DATA_M: u32 = 0xFFFFFFFF; // User Data +pub const FLASH_USERREG0_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG1 register. +// +//***************************************************************************** +pub const FLASH_USERREG1_DATA_M: u32 = 0xFFFFFFFF; // User Data +pub const FLASH_USERREG1_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG2 register. +// +//***************************************************************************** +pub const FLASH_USERREG2_DATA_M: u32 = 0xFFFFFFFF; // User Data +pub const FLASH_USERREG2_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG3 register. +// +//***************************************************************************** +pub const FLASH_USERREG3_DATA_M: u32 = 0xFFFFFFFF; // User Data +pub const FLASH_USERREG3_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +pub const SYSCTL_DID0_VER_M: u32 = 0x70000000; // DID0 Version +pub const SYSCTL_DID0_VER_1: u32 = 0x10000000; // Second version of the DID0 + // register format. +pub const SYSCTL_DID0_CLASS_M: u32 = 0x00FF0000; // Device Class +pub const SYSCTL_DID0_CLASS_TM4C123: u32 = 0x00050000; // Tiva TM4C123x and TM4E123x + // microcontrollers +pub const SYSCTL_DID0_MAJ_M: u32 = 0x0000FF00; // Major Revision +pub const SYSCTL_DID0_MAJ_REVA: u32 = 0x00000000; // Revision A (initial device) +pub const SYSCTL_DID0_MAJ_REVB: u32 = 0x00000100; // Revision B (first base layer + // revision) +pub const SYSCTL_DID0_MAJ_REVC: u32 = 0x00000200; // Revision C (second base layer + // revision) +pub const SYSCTL_DID0_MIN_M: u32 = 0x000000FF; // Minor Revision +pub const SYSCTL_DID0_MIN_0: u32 = 0x00000000; // Initial device, or a major + // revision update +pub const SYSCTL_DID0_MIN_1: u32 = 0x00000001; // First metal layer change +pub const SYSCTL_DID0_MIN_2: u32 = 0x00000002; // Second metal layer change +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +pub const SYSCTL_DID1_VER_M: u32 = 0xF0000000; // DID1 Version +pub const SYSCTL_DID1_VER_1: u32 = 0x10000000; // fury_ib +pub const SYSCTL_DID1_FAM_M: u32 = 0x0F000000; // Family +pub const SYSCTL_DID1_FAM_TIVA: u32 = 0x00000000; // Tiva family of microcontollers +pub const SYSCTL_DID1_PRTNO_M: u32 = 0x00FF0000; // Part Number +pub const SYSCTL_DID1_PRTNO_TM4C123GH6PM: u32 = 0x00A10000; // TM4C123GH6PM +pub const SYSCTL_DID1_PINCNT_M: u32 = 0x0000E000; // Package Pin Count +pub const SYSCTL_DID1_PINCNT_100: u32 = 0x00004000; // 100-pin LQFP package +pub const SYSCTL_DID1_PINCNT_64: u32 = 0x00006000; // 64-pin LQFP package +pub const SYSCTL_DID1_PINCNT_144: u32 = 0x00008000; // 144-pin LQFP package +pub const SYSCTL_DID1_PINCNT_157: u32 = 0x0000A000; // 157-pin BGA package +pub const SYSCTL_DID1_PINCNT_128: u32 = 0x0000C000; // 128-pin TQFP package +pub const SYSCTL_DID1_TEMP_M: u32 = 0x000000E0; // Temperature Range +pub const SYSCTL_DID1_TEMP_I: u32 = 0x00000020; // Industrial temperature range +pub const SYSCTL_DID1_TEMP_E: u32 = 0x00000040; // Extended temperature range +pub const SYSCTL_DID1_TEMP_IE: u32 = 0x00000060; // Available in both industrial + // temperature range (-40C to 85C) + // and extended temperature range + // (-40C to 105C) devices. See +pub const SYSCTL_DID1_PKG_M: u32 = 0x00000018; // Package Type +pub const SYSCTL_DID1_PKG_QFP: u32 = 0x00000008; // QFP package +pub const SYSCTL_DID1_PKG_BGA: u32 = 0x00000010; // BGA package +pub const SYSCTL_DID1_ROHS: u32 = 0x00000004; // RoHS-Compliance +pub const SYSCTL_DID1_QUAL_M: u32 = 0x00000003; // Qualification Status +pub const SYSCTL_DID1_QUAL_ES: u32 = 0x00000000; // Engineering Sample (unqualified) +pub const SYSCTL_DID1_QUAL_PP: u32 = 0x00000001; // Pilot Production (unqualified) +pub const SYSCTL_DID1_QUAL_FQ: u32 = 0x00000002; // Fully Qualified +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +pub const SYSCTL_DC0_SRAMSZ_M: u32 = 0xFFFF0000; // SRAM Size +pub const SYSCTL_DC0_SRAMSZ_2KB: u32 = 0x00070000; // 2 KB of SRAM +pub const SYSCTL_DC0_SRAMSZ_4KB: u32 = 0x000F0000; // 4 KB of SRAM +pub const SYSCTL_DC0_SRAMSZ_6KB: u32 = 0x00170000; // 6 KB of SRAM +pub const SYSCTL_DC0_SRAMSZ_8KB: u32 = 0x001F0000; // 8 KB of SRAM +pub const SYSCTL_DC0_SRAMSZ_12KB: u32 = 0x002F0000; // 12 KB of SRAM +pub const SYSCTL_DC0_SRAMSZ_16KB: u32 = 0x003F0000; // 16 KB of SRAM +pub const SYSCTL_DC0_SRAMSZ_20KB: u32 = 0x004F0000; // 20 KB of SRAM +pub const SYSCTL_DC0_SRAMSZ_24KB: u32 = 0x005F0000; // 24 KB of SRAM +pub const SYSCTL_DC0_SRAMSZ_32KB: u32 = 0x007F0000; // 32 KB of SRAM +pub const SYSCTL_DC0_FLASHSZ_M: u32 = 0x0000FFFF; // Flash Size +pub const SYSCTL_DC0_FLASHSZ_8KB: u32 = 0x00000003; // 8 KB of Flash +pub const SYSCTL_DC0_FLASHSZ_16KB: u32 = 0x00000007; // 16 KB of Flash +pub const SYSCTL_DC0_FLASHSZ_32KB: u32 = 0x0000000F; // 32 KB of Flash +pub const SYSCTL_DC0_FLASHSZ_64KB: u32 = 0x0000001F; // 64 KB of Flash +pub const SYSCTL_DC0_FLASHSZ_96KB: u32 = 0x0000002F; // 96 KB of Flash +pub const SYSCTL_DC0_FLASHSZ_128K: u32 = 0x0000003F; // 128 KB of Flash +pub const SYSCTL_DC0_FLASHSZ_192K: u32 = 0x0000005F; // 192 KB of Flash +pub const SYSCTL_DC0_FLASHSZ_256K: u32 = 0x0000007F; // 256 KB of Flash +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +pub const SYSCTL_DC1_WDT1: u32 = 0x10000000; // Watchdog Timer1 Present +pub const SYSCTL_DC1_CAN1: u32 = 0x02000000; // CAN Module 1 Present +pub const SYSCTL_DC1_CAN0: u32 = 0x01000000; // CAN Module 0 Present +pub const SYSCTL_DC1_PWM1: u32 = 0x00200000; // PWM Module 1 Present +pub const SYSCTL_DC1_PWM0: u32 = 0x00100000; // PWM Module 0 Present +pub const SYSCTL_DC1_ADC1: u32 = 0x00020000; // ADC Module 1 Present +pub const SYSCTL_DC1_ADC0: u32 = 0x00010000; // ADC Module 0 Present +pub const SYSCTL_DC1_MINSYSDIV_M: u32 = 0x0000F000; // System Clock Divider +pub const SYSCTL_DC1_MINSYSDIV_80: u32 = 0x00001000; // Specifies an 80-MHz CPU clock + // with a PLL divider of 2.5 +pub const SYSCTL_DC1_MINSYSDIV_66: u32 = 0x00002000; // Specifies a 66-MHz CPU clock + // with a PLL divider of 3 +pub const SYSCTL_DC1_MINSYSDIV_50: u32 = 0x00003000; // Specifies a 50-MHz CPU clock + // with a PLL divider of 4 +pub const SYSCTL_DC1_MINSYSDIV_40: u32 = 0x00004000; // Specifies a 40-MHz CPU clock + // with a PLL divider of 5 +pub const SYSCTL_DC1_MINSYSDIV_25: u32 = 0x00007000; // Specifies a 25-MHz clock with a + // PLL divider of 8 +pub const SYSCTL_DC1_MINSYSDIV_20: u32 = 0x00009000; // Specifies a 20-MHz clock with a + // PLL divider of 10 +pub const SYSCTL_DC1_ADC1SPD_M: u32 = 0x00000C00; // Max ADC1 Speed +pub const SYSCTL_DC1_ADC1SPD_125K: u32 = 0x00000000; // 125K samples/second +pub const SYSCTL_DC1_ADC1SPD_250K: u32 = 0x00000400; // 250K samples/second +pub const SYSCTL_DC1_ADC1SPD_500K: u32 = 0x00000800; // 500K samples/second +pub const SYSCTL_DC1_ADC1SPD_1M: u32 = 0x00000C00; // 1M samples/second +pub const SYSCTL_DC1_ADC0SPD_M: u32 = 0x00000300; // Max ADC0 Speed +pub const SYSCTL_DC1_ADC0SPD_125K: u32 = 0x00000000; // 125K samples/second +pub const SYSCTL_DC1_ADC0SPD_250K: u32 = 0x00000100; // 250K samples/second +pub const SYSCTL_DC1_ADC0SPD_500K: u32 = 0x00000200; // 500K samples/second +pub const SYSCTL_DC1_ADC0SPD_1M: u32 = 0x00000300; // 1M samples/second +pub const SYSCTL_DC1_MPU: u32 = 0x00000080; // MPU Present +pub const SYSCTL_DC1_HIB: u32 = 0x00000040; // Hibernation Module Present +pub const SYSCTL_DC1_TEMP: u32 = 0x00000020; // Temp Sensor Present +pub const SYSCTL_DC1_PLL: u32 = 0x00000010; // PLL Present +pub const SYSCTL_DC1_WDT0: u32 = 0x00000008; // Watchdog Timer 0 Present +pub const SYSCTL_DC1_SWO: u32 = 0x00000004; // SWO Trace Port Present +pub const SYSCTL_DC1_SWD: u32 = 0x00000002; // SWD Present +pub const SYSCTL_DC1_JTAG: u32 = 0x00000001; // JTAG Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +pub const SYSCTL_DC2_EPI0: u32 = 0x40000000; // EPI Module 0 Present +pub const SYSCTL_DC2_I2S0: u32 = 0x10000000; // I2S Module 0 Present +pub const SYSCTL_DC2_COMP2: u32 = 0x04000000; // Analog Comparator 2 Present +pub const SYSCTL_DC2_COMP1: u32 = 0x02000000; // Analog Comparator 1 Present +pub const SYSCTL_DC2_COMP0: u32 = 0x01000000; // Analog Comparator 0 Present +pub const SYSCTL_DC2_TIMER3: u32 = 0x00080000; // Timer Module 3 Present +pub const SYSCTL_DC2_TIMER2: u32 = 0x00040000; // Timer Module 2 Present +pub const SYSCTL_DC2_TIMER1: u32 = 0x00020000; // Timer Module 1 Present +pub const SYSCTL_DC2_TIMER0: u32 = 0x00010000; // Timer Module 0 Present +pub const SYSCTL_DC2_I2C1HS: u32 = 0x00008000; // I2C Module 1 Speed +pub const SYSCTL_DC2_I2C1: u32 = 0x00004000; // I2C Module 1 Present +pub const SYSCTL_DC2_I2C0HS: u32 = 0x00002000; // I2C Module 0 Speed +pub const SYSCTL_DC2_I2C0: u32 = 0x00001000; // I2C Module 0 Present +pub const SYSCTL_DC2_QEI1: u32 = 0x00000200; // QEI Module 1 Present +pub const SYSCTL_DC2_QEI0: u32 = 0x00000100; // QEI Module 0 Present +pub const SYSCTL_DC2_SSI1: u32 = 0x00000020; // SSI Module 1 Present +pub const SYSCTL_DC2_SSI0: u32 = 0x00000010; // SSI Module 0 Present +pub const SYSCTL_DC2_UART2: u32 = 0x00000004; // UART Module 2 Present +pub const SYSCTL_DC2_UART1: u32 = 0x00000002; // UART Module 1 Present +pub const SYSCTL_DC2_UART0: u32 = 0x00000001; // UART Module 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +pub const SYSCTL_DC3_32KHZ: u32 = 0x80000000; // 32KHz Input Clock Available +pub const SYSCTL_DC3_CCP5: u32 = 0x20000000; // T2CCP1 Pin Present +pub const SYSCTL_DC3_CCP4: u32 = 0x10000000; // T2CCP0 Pin Present +pub const SYSCTL_DC3_CCP3: u32 = 0x08000000; // T1CCP1 Pin Present +pub const SYSCTL_DC3_CCP2: u32 = 0x04000000; // T1CCP0 Pin Present +pub const SYSCTL_DC3_CCP1: u32 = 0x02000000; // T0CCP1 Pin Present +pub const SYSCTL_DC3_CCP0: u32 = 0x01000000; // T0CCP0 Pin Present +pub const SYSCTL_DC3_ADC0AIN7: u32 = 0x00800000; // ADC Module 0 AIN7 Pin Present +pub const SYSCTL_DC3_ADC0AIN6: u32 = 0x00400000; // ADC Module 0 AIN6 Pin Present +pub const SYSCTL_DC3_ADC0AIN5: u32 = 0x00200000; // ADC Module 0 AIN5 Pin Present +pub const SYSCTL_DC3_ADC0AIN4: u32 = 0x00100000; // ADC Module 0 AIN4 Pin Present +pub const SYSCTL_DC3_ADC0AIN3: u32 = 0x00080000; // ADC Module 0 AIN3 Pin Present +pub const SYSCTL_DC3_ADC0AIN2: u32 = 0x00040000; // ADC Module 0 AIN2 Pin Present +pub const SYSCTL_DC3_ADC0AIN1: u32 = 0x00020000; // ADC Module 0 AIN1 Pin Present +pub const SYSCTL_DC3_ADC0AIN0: u32 = 0x00010000; // ADC Module 0 AIN0 Pin Present +pub const SYSCTL_DC3_PWMFAULT: u32 = 0x00008000; // PWM Fault Pin Present +pub const SYSCTL_DC3_C2O: u32 = 0x00004000; // C2o Pin Present +pub const SYSCTL_DC3_C2PLUS: u32 = 0x00002000; // C2+ Pin Present +pub const SYSCTL_DC3_C2MINUS: u32 = 0x00001000; // C2- Pin Present +pub const SYSCTL_DC3_C1O: u32 = 0x00000800; // C1o Pin Present +pub const SYSCTL_DC3_C1PLUS: u32 = 0x00000400; // C1+ Pin Present +pub const SYSCTL_DC3_C1MINUS: u32 = 0x00000200; // C1- Pin Present +pub const SYSCTL_DC3_C0O: u32 = 0x00000100; // C0o Pin Present +pub const SYSCTL_DC3_C0PLUS: u32 = 0x00000080; // C0+ Pin Present +pub const SYSCTL_DC3_C0MINUS: u32 = 0x00000040; // C0- Pin Present +pub const SYSCTL_DC3_PWM5: u32 = 0x00000020; // PWM5 Pin Present +pub const SYSCTL_DC3_PWM4: u32 = 0x00000010; // PWM4 Pin Present +pub const SYSCTL_DC3_PWM3: u32 = 0x00000008; // PWM3 Pin Present +pub const SYSCTL_DC3_PWM2: u32 = 0x00000004; // PWM2 Pin Present +pub const SYSCTL_DC3_PWM1: u32 = 0x00000002; // PWM1 Pin Present +pub const SYSCTL_DC3_PWM0: u32 = 0x00000001; // PWM0 Pin Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +pub const SYSCTL_DC4_EPHY0: u32 = 0x40000000; // Ethernet PHY Layer 0 Present +pub const SYSCTL_DC4_EMAC0: u32 = 0x10000000; // Ethernet MAC Layer 0 Present +pub const SYSCTL_DC4_E1588: u32 = 0x01000000; // 1588 Capable +pub const SYSCTL_DC4_PICAL: u32 = 0x00040000; // PIOSC Calibrate +pub const SYSCTL_DC4_CCP7: u32 = 0x00008000; // T3CCP1 Pin Present +pub const SYSCTL_DC4_CCP6: u32 = 0x00004000; // T3CCP0 Pin Present +pub const SYSCTL_DC4_UDMA: u32 = 0x00002000; // Micro-DMA Module Present +pub const SYSCTL_DC4_ROM: u32 = 0x00001000; // Internal Code ROM Present +pub const SYSCTL_DC4_GPIOJ: u32 = 0x00000100; // GPIO Port J Present +pub const SYSCTL_DC4_GPIOH: u32 = 0x00000080; // GPIO Port H Present +pub const SYSCTL_DC4_GPIOG: u32 = 0x00000040; // GPIO Port G Present +pub const SYSCTL_DC4_GPIOF: u32 = 0x00000020; // GPIO Port F Present +pub const SYSCTL_DC4_GPIOE: u32 = 0x00000010; // GPIO Port E Present +pub const SYSCTL_DC4_GPIOD: u32 = 0x00000008; // GPIO Port D Present +pub const SYSCTL_DC4_GPIOC: u32 = 0x00000004; // GPIO Port C Present +pub const SYSCTL_DC4_GPIOB: u32 = 0x00000002; // GPIO Port B Present +pub const SYSCTL_DC4_GPIOA: u32 = 0x00000001; // GPIO Port A Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC5 register. +// +//***************************************************************************** +pub const SYSCTL_DC5_PWMFAULT3: u32 = 0x08000000; // PWM Fault 3 Pin Present +pub const SYSCTL_DC5_PWMFAULT2: u32 = 0x04000000; // PWM Fault 2 Pin Present +pub const SYSCTL_DC5_PWMFAULT1: u32 = 0x02000000; // PWM Fault 1 Pin Present +pub const SYSCTL_DC5_PWMFAULT0: u32 = 0x01000000; // PWM Fault 0 Pin Present +pub const SYSCTL_DC5_PWMEFLT: u32 = 0x00200000; // PWM Extended Fault Active +pub const SYSCTL_DC5_PWMESYNC: u32 = 0x00100000; // PWM Extended SYNC Active +pub const SYSCTL_DC5_PWM7: u32 = 0x00000080; // PWM7 Pin Present +pub const SYSCTL_DC5_PWM6: u32 = 0x00000040; // PWM6 Pin Present +pub const SYSCTL_DC5_PWM5: u32 = 0x00000020; // PWM5 Pin Present +pub const SYSCTL_DC5_PWM4: u32 = 0x00000010; // PWM4 Pin Present +pub const SYSCTL_DC5_PWM3: u32 = 0x00000008; // PWM3 Pin Present +pub const SYSCTL_DC5_PWM2: u32 = 0x00000004; // PWM2 Pin Present +pub const SYSCTL_DC5_PWM1: u32 = 0x00000002; // PWM1 Pin Present +pub const SYSCTL_DC5_PWM0: u32 = 0x00000001; // PWM0 Pin Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC6 register. +// +//***************************************************************************** +pub const SYSCTL_DC6_USB0PHY: u32 = 0x00000010; // USB Module 0 PHY Present +pub const SYSCTL_DC6_USB0_M: u32 = 0x00000003; // USB Module 0 Present +pub const SYSCTL_DC6_USB0_DEV: u32 = 0x00000001; // USB0 is Device Only +pub const SYSCTL_DC6_USB0_HOSTDEV: u32 = 0x00000002; // USB is Device or Host +pub const SYSCTL_DC6_USB0_OTG: u32 = 0x00000003; // USB0 is OTG +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC7 register. +// +//***************************************************************************** +pub const SYSCTL_DC7_DMACH30: u32 = 0x40000000; // DMA Channel 30 +pub const SYSCTL_DC7_DMACH29: u32 = 0x20000000; // DMA Channel 29 +pub const SYSCTL_DC7_DMACH28: u32 = 0x10000000; // DMA Channel 28 +pub const SYSCTL_DC7_DMACH27: u32 = 0x08000000; // DMA Channel 27 +pub const SYSCTL_DC7_DMACH26: u32 = 0x04000000; // DMA Channel 26 +pub const SYSCTL_DC7_DMACH25: u32 = 0x02000000; // DMA Channel 25 +pub const SYSCTL_DC7_DMACH24: u32 = 0x01000000; // DMA Channel 24 +pub const SYSCTL_DC7_DMACH23: u32 = 0x00800000; // DMA Channel 23 +pub const SYSCTL_DC7_DMACH22: u32 = 0x00400000; // DMA Channel 22 +pub const SYSCTL_DC7_DMACH21: u32 = 0x00200000; // DMA Channel 21 +pub const SYSCTL_DC7_DMACH20: u32 = 0x00100000; // DMA Channel 20 +pub const SYSCTL_DC7_DMACH19: u32 = 0x00080000; // DMA Channel 19 +pub const SYSCTL_DC7_DMACH18: u32 = 0x00040000; // DMA Channel 18 +pub const SYSCTL_DC7_DMACH17: u32 = 0x00020000; // DMA Channel 17 +pub const SYSCTL_DC7_DMACH16: u32 = 0x00010000; // DMA Channel 16 +pub const SYSCTL_DC7_DMACH15: u32 = 0x00008000; // DMA Channel 15 +pub const SYSCTL_DC7_DMACH14: u32 = 0x00004000; // DMA Channel 14 +pub const SYSCTL_DC7_DMACH13: u32 = 0x00002000; // DMA Channel 13 +pub const SYSCTL_DC7_DMACH12: u32 = 0x00001000; // DMA Channel 12 +pub const SYSCTL_DC7_DMACH11: u32 = 0x00000800; // DMA Channel 11 +pub const SYSCTL_DC7_DMACH10: u32 = 0x00000400; // DMA Channel 10 +pub const SYSCTL_DC7_DMACH9: u32 = 0x00000200; // DMA Channel 9 +pub const SYSCTL_DC7_DMACH8: u32 = 0x00000100; // DMA Channel 8 +pub const SYSCTL_DC7_DMACH7: u32 = 0x00000080; // DMA Channel 7 +pub const SYSCTL_DC7_DMACH6: u32 = 0x00000040; // DMA Channel 6 +pub const SYSCTL_DC7_DMACH5: u32 = 0x00000020; // DMA Channel 5 +pub const SYSCTL_DC7_DMACH4: u32 = 0x00000010; // DMA Channel 4 +pub const SYSCTL_DC7_DMACH3: u32 = 0x00000008; // DMA Channel 3 +pub const SYSCTL_DC7_DMACH2: u32 = 0x00000004; // DMA Channel 2 +pub const SYSCTL_DC7_DMACH1: u32 = 0x00000002; // DMA Channel 1 +pub const SYSCTL_DC7_DMACH0: u32 = 0x00000001; // DMA Channel 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC8 register. +// +//***************************************************************************** +pub const SYSCTL_DC8_ADC1AIN15: u32 = 0x80000000; // ADC Module 1 AIN15 Pin Present +pub const SYSCTL_DC8_ADC1AIN14: u32 = 0x40000000; // ADC Module 1 AIN14 Pin Present +pub const SYSCTL_DC8_ADC1AIN13: u32 = 0x20000000; // ADC Module 1 AIN13 Pin Present +pub const SYSCTL_DC8_ADC1AIN12: u32 = 0x10000000; // ADC Module 1 AIN12 Pin Present +pub const SYSCTL_DC8_ADC1AIN11: u32 = 0x08000000; // ADC Module 1 AIN11 Pin Present +pub const SYSCTL_DC8_ADC1AIN10: u32 = 0x04000000; // ADC Module 1 AIN10 Pin Present +pub const SYSCTL_DC8_ADC1AIN9: u32 = 0x02000000; // ADC Module 1 AIN9 Pin Present +pub const SYSCTL_DC8_ADC1AIN8: u32 = 0x01000000; // ADC Module 1 AIN8 Pin Present +pub const SYSCTL_DC8_ADC1AIN7: u32 = 0x00800000; // ADC Module 1 AIN7 Pin Present +pub const SYSCTL_DC8_ADC1AIN6: u32 = 0x00400000; // ADC Module 1 AIN6 Pin Present +pub const SYSCTL_DC8_ADC1AIN5: u32 = 0x00200000; // ADC Module 1 AIN5 Pin Present +pub const SYSCTL_DC8_ADC1AIN4: u32 = 0x00100000; // ADC Module 1 AIN4 Pin Present +pub const SYSCTL_DC8_ADC1AIN3: u32 = 0x00080000; // ADC Module 1 AIN3 Pin Present +pub const SYSCTL_DC8_ADC1AIN2: u32 = 0x00040000; // ADC Module 1 AIN2 Pin Present +pub const SYSCTL_DC8_ADC1AIN1: u32 = 0x00020000; // ADC Module 1 AIN1 Pin Present +pub const SYSCTL_DC8_ADC1AIN0: u32 = 0x00010000; // ADC Module 1 AIN0 Pin Present +pub const SYSCTL_DC8_ADC0AIN15: u32 = 0x00008000; // ADC Module 0 AIN15 Pin Present +pub const SYSCTL_DC8_ADC0AIN14: u32 = 0x00004000; // ADC Module 0 AIN14 Pin Present +pub const SYSCTL_DC8_ADC0AIN13: u32 = 0x00002000; // ADC Module 0 AIN13 Pin Present +pub const SYSCTL_DC8_ADC0AIN12: u32 = 0x00001000; // ADC Module 0 AIN12 Pin Present +pub const SYSCTL_DC8_ADC0AIN11: u32 = 0x00000800; // ADC Module 0 AIN11 Pin Present +pub const SYSCTL_DC8_ADC0AIN10: u32 = 0x00000400; // ADC Module 0 AIN10 Pin Present +pub const SYSCTL_DC8_ADC0AIN9: u32 = 0x00000200; // ADC Module 0 AIN9 Pin Present +pub const SYSCTL_DC8_ADC0AIN8: u32 = 0x00000100; // ADC Module 0 AIN8 Pin Present +pub const SYSCTL_DC8_ADC0AIN7: u32 = 0x00000080; // ADC Module 0 AIN7 Pin Present +pub const SYSCTL_DC8_ADC0AIN6: u32 = 0x00000040; // ADC Module 0 AIN6 Pin Present +pub const SYSCTL_DC8_ADC0AIN5: u32 = 0x00000020; // ADC Module 0 AIN5 Pin Present +pub const SYSCTL_DC8_ADC0AIN4: u32 = 0x00000010; // ADC Module 0 AIN4 Pin Present +pub const SYSCTL_DC8_ADC0AIN3: u32 = 0x00000008; // ADC Module 0 AIN3 Pin Present +pub const SYSCTL_DC8_ADC0AIN2: u32 = 0x00000004; // ADC Module 0 AIN2 Pin Present +pub const SYSCTL_DC8_ADC0AIN1: u32 = 0x00000002; // ADC Module 0 AIN1 Pin Present +pub const SYSCTL_DC8_ADC0AIN0: u32 = 0x00000001; // ADC Module 0 AIN0 Pin Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +pub const SYSCTL_PBORCTL_BOR0: u32 = 0x00000004; // VDD under BOR0 Event Action +pub const SYSCTL_PBORCTL_BOR1: u32 = 0x00000002; // VDD under BOR1 Event Action +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR0 register. +// +//***************************************************************************** +pub const SYSCTL_SRCR0_WDT1: u32 = 0x10000000; // WDT1 Reset Control +pub const SYSCTL_SRCR0_CAN1: u32 = 0x02000000; // CAN1 Reset Control +pub const SYSCTL_SRCR0_CAN0: u32 = 0x01000000; // CAN0 Reset Control +pub const SYSCTL_SRCR0_PWM0: u32 = 0x00100000; // PWM Reset Control +pub const SYSCTL_SRCR0_ADC1: u32 = 0x00020000; // ADC1 Reset Control +pub const SYSCTL_SRCR0_ADC0: u32 = 0x00010000; // ADC0 Reset Control +pub const SYSCTL_SRCR0_HIB: u32 = 0x00000040; // HIB Reset Control +pub const SYSCTL_SRCR0_WDT0: u32 = 0x00000008; // WDT0 Reset Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR1 register. +// +//***************************************************************************** +pub const SYSCTL_SRCR1_COMP1: u32 = 0x02000000; // Analog Comp 1 Reset Control +pub const SYSCTL_SRCR1_COMP0: u32 = 0x01000000; // Analog Comp 0 Reset Control +pub const SYSCTL_SRCR1_TIMER3: u32 = 0x00080000; // Timer 3 Reset Control +pub const SYSCTL_SRCR1_TIMER2: u32 = 0x00040000; // Timer 2 Reset Control +pub const SYSCTL_SRCR1_TIMER1: u32 = 0x00020000; // Timer 1 Reset Control +pub const SYSCTL_SRCR1_TIMER0: u32 = 0x00010000; // Timer 0 Reset Control +pub const SYSCTL_SRCR1_I2C1: u32 = 0x00004000; // I2C1 Reset Control +pub const SYSCTL_SRCR1_I2C0: u32 = 0x00001000; // I2C0 Reset Control +pub const SYSCTL_SRCR1_QEI1: u32 = 0x00000200; // QEI1 Reset Control +pub const SYSCTL_SRCR1_QEI0: u32 = 0x00000100; // QEI0 Reset Control +pub const SYSCTL_SRCR1_SSI1: u32 = 0x00000020; // SSI1 Reset Control +pub const SYSCTL_SRCR1_SSI0: u32 = 0x00000010; // SSI0 Reset Control +pub const SYSCTL_SRCR1_UART2: u32 = 0x00000004; // UART2 Reset Control +pub const SYSCTL_SRCR1_UART1: u32 = 0x00000002; // UART1 Reset Control +pub const SYSCTL_SRCR1_UART0: u32 = 0x00000001; // UART0 Reset Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR2 register. +// +//***************************************************************************** +pub const SYSCTL_SRCR2_USB0: u32 = 0x00010000; // USB0 Reset Control +pub const SYSCTL_SRCR2_UDMA: u32 = 0x00002000; // Micro-DMA Reset Control +pub const SYSCTL_SRCR2_GPIOF: u32 = 0x00000020; // Port F Reset Control +pub const SYSCTL_SRCR2_GPIOE: u32 = 0x00000010; // Port E Reset Control +pub const SYSCTL_SRCR2_GPIOD: u32 = 0x00000008; // Port D Reset Control +pub const SYSCTL_SRCR2_GPIOC: u32 = 0x00000004; // Port C Reset Control +pub const SYSCTL_SRCR2_GPIOB: u32 = 0x00000002; // Port B Reset Control +pub const SYSCTL_SRCR2_GPIOA: u32 = 0x00000001; // Port A Reset Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RIS register. +// +//***************************************************************************** +pub const SYSCTL_RIS_BOR0RIS: u32 = 0x00000800; // VDD under BOR0 Raw Interrupt + // Status +pub const SYSCTL_RIS_VDDARIS: u32 = 0x00000400; // VDDA Power OK Event Raw + // Interrupt Status +pub const SYSCTL_RIS_MOSCPUPRIS: u32 = 0x00000100; // MOSC Power Up Raw Interrupt + // Status +pub const SYSCTL_RIS_USBPLLLRIS: u32 = 0x00000080; // USB PLL Lock Raw Interrupt + // Status +pub const SYSCTL_RIS_PLLLRIS: u32 = 0x00000040; // PLL Lock Raw Interrupt Status +pub const SYSCTL_RIS_MOFRIS: u32 = 0x00000008; // Main Oscillator Failure Raw + // Interrupt Status +pub const SYSCTL_RIS_BOR1RIS: u32 = 0x00000002; // VDD under BOR1 Raw Interrupt + // Status +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_IMC register. +// +//***************************************************************************** +pub const SYSCTL_IMC_BOR0IM: u32 = 0x00000800; // VDD under BOR0 Interrupt Mask +pub const SYSCTL_IMC_VDDAIM: u32 = 0x00000400; // VDDA Power OK Interrupt Mask +pub const SYSCTL_IMC_MOSCPUPIM: u32 = 0x00000100; // MOSC Power Up Interrupt Mask +pub const SYSCTL_IMC_USBPLLLIM: u32 = 0x00000080; // USB PLL Lock Interrupt Mask +pub const SYSCTL_IMC_PLLLIM: u32 = 0x00000040; // PLL Lock Interrupt Mask +pub const SYSCTL_IMC_MOFIM: u32 = 0x00000008; // Main Oscillator Failure + // Interrupt Mask +pub const SYSCTL_IMC_BOR1IM: u32 = 0x00000002; // VDD under BOR1 Interrupt Mask +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MISC register. +// +//***************************************************************************** +pub const SYSCTL_MISC_BOR0MIS: u32 = 0x00000800; // VDD under BOR0 Masked Interrupt + // Status +pub const SYSCTL_MISC_VDDAMIS: u32 = 0x00000400; // VDDA Power OK Masked Interrupt + // Status +pub const SYSCTL_MISC_MOSCPUPMIS: u32 = 0x00000100; // MOSC Power Up Masked Interrupt + // Status +pub const SYSCTL_MISC_USBPLLLMIS: u32 = 0x00000080; // USB PLL Lock Masked Interrupt + // Status +pub const SYSCTL_MISC_PLLLMIS: u32 = 0x00000040; // PLL Lock Masked Interrupt Status +pub const SYSCTL_MISC_MOFMIS: u32 = 0x00000008; // Main Oscillator Failure Masked + // Interrupt Status +pub const SYSCTL_MISC_BOR1MIS: u32 = 0x00000002; // VDD under BOR1 Masked Interrupt + // Status +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +pub const SYSCTL_RESC_MOSCFAIL: u32 = 0x00010000; // MOSC Failure Reset +pub const SYSCTL_RESC_WDT1: u32 = 0x00000020; // Watchdog Timer 1 Reset +pub const SYSCTL_RESC_SW: u32 = 0x00000010; // Software Reset +pub const SYSCTL_RESC_WDT0: u32 = 0x00000008; // Watchdog Timer 0 Reset +pub const SYSCTL_RESC_BOR: u32 = 0x00000004; // Brown-Out Reset +pub const SYSCTL_RESC_POR: u32 = 0x00000002; // Power-On Reset +pub const SYSCTL_RESC_EXT: u32 = 0x00000001; // External Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +pub const SYSCTL_RCC_ACG: u32 = 0x08000000; // Auto Clock Gating +pub const SYSCTL_RCC_SYSDIV_M: u32 = 0x07800000; // System Clock Divisor +pub const SYSCTL_RCC_USESYSDIV: u32 = 0x00400000; // Enable System Clock Divider +pub const SYSCTL_RCC_USEPWMDIV: u32 = 0x00100000; // Enable PWM Clock Divisor +pub const SYSCTL_RCC_PWMDIV_M: u32 = 0x000E0000; // PWM Unit Clock Divisor +pub const SYSCTL_RCC_PWMDIV_2: u32 = 0x00000000; // PWM clock /2 +pub const SYSCTL_RCC_PWMDIV_4: u32 = 0x00020000; // PWM clock /4 +pub const SYSCTL_RCC_PWMDIV_8: u32 = 0x00040000; // PWM clock /8 +pub const SYSCTL_RCC_PWMDIV_16: u32 = 0x00060000; // PWM clock /16 +pub const SYSCTL_RCC_PWMDIV_32: u32 = 0x00080000; // PWM clock /32 +pub const SYSCTL_RCC_PWMDIV_64: u32 = 0x000A0000; // PWM clock /64 +pub const SYSCTL_RCC_PWRDN: u32 = 0x00002000; // PLL Power Down +pub const SYSCTL_RCC_BYPASS: u32 = 0x00000800; // PLL Bypass +pub const SYSCTL_RCC_XTAL_M: u32 = 0x000007C0; // Crystal Value +pub const SYSCTL_RCC_XTAL_4MHZ: u32 = 0x00000180; // 4 MHz +pub const SYSCTL_RCC_XTAL_4_09MHZ: u32 = 0x000001C0; // 4.096 MHz +pub const SYSCTL_RCC_XTAL_4_91MHZ: u32 = 0x00000200; // 4.9152 MHz +pub const SYSCTL_RCC_XTAL_5MHZ: u32 = 0x00000240; // 5 MHz +pub const SYSCTL_RCC_XTAL_5_12MHZ: u32 = 0x00000280; // 5.12 MHz +pub const SYSCTL_RCC_XTAL_6MHZ: u32 = 0x000002C0; // 6 MHz +pub const SYSCTL_RCC_XTAL_6_14MHZ: u32 = 0x00000300; // 6.144 MHz +pub const SYSCTL_RCC_XTAL_7_37MHZ: u32 = 0x00000340; // 7.3728 MHz +pub const SYSCTL_RCC_XTAL_8MHZ: u32 = 0x00000380; // 8 MHz +pub const SYSCTL_RCC_XTAL_8_19MHZ: u32 = 0x000003C0; // 8.192 MHz +pub const SYSCTL_RCC_XTAL_10MHZ: u32 = 0x00000400; // 10 MHz +pub const SYSCTL_RCC_XTAL_12MHZ: u32 = 0x00000440; // 12 MHz +pub const SYSCTL_RCC_XTAL_12_2MHZ: u32 = 0x00000480; // 12.288 MHz +pub const SYSCTL_RCC_XTAL_13_5MHZ: u32 = 0x000004C0; // 13.56 MHz +pub const SYSCTL_RCC_XTAL_14_3MHZ: u32 = 0x00000500; // 14.31818 MHz +pub const SYSCTL_RCC_XTAL_16MHZ: u32 = 0x00000540; // 16 MHz +pub const SYSCTL_RCC_XTAL_16_3MHZ: u32 = 0x00000580; // 16.384 MHz +pub const SYSCTL_RCC_XTAL_18MHZ: u32 = 0x000005C0; // 18.0 MHz (USB) +pub const SYSCTL_RCC_XTAL_20MHZ: u32 = 0x00000600; // 20.0 MHz (USB) +pub const SYSCTL_RCC_XTAL_24MHZ: u32 = 0x00000640; // 24.0 MHz (USB) +pub const SYSCTL_RCC_XTAL_25MHZ: u32 = 0x00000680; // 25.0 MHz (USB) +pub const SYSCTL_RCC_OSCSRC_M: u32 = 0x00000030; // Oscillator Source +pub const SYSCTL_RCC_OSCSRC_MAIN: u32 = 0x00000000; // MOSC +pub const SYSCTL_RCC_OSCSRC_INT: u32 = 0x00000010; // IOSC +pub const SYSCTL_RCC_OSCSRC_INT4: u32 = 0x00000020; // IOSC/4 +pub const SYSCTL_RCC_OSCSRC_30: u32 = 0x00000030; // LFIOSC +pub const SYSCTL_RCC_MOSCDIS: u32 = 0x00000001; // Main Oscillator Disable +pub const SYSCTL_RCC_SYSDIV_S: u32 = 23; +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL +// register. +// +//***************************************************************************** +pub const SYSCTL_GPIOHBCTL_PORTF: u32 = 0x00000020; // Port F Advanced High-Performance + // Bus +pub const SYSCTL_GPIOHBCTL_PORTE: u32 = 0x00000010; // Port E Advanced High-Performance + // Bus +pub const SYSCTL_GPIOHBCTL_PORTD: u32 = 0x00000008; // Port D Advanced High-Performance + // Bus +pub const SYSCTL_GPIOHBCTL_PORTC: u32 = 0x00000004; // Port C Advanced High-Performance + // Bus +pub const SYSCTL_GPIOHBCTL_PORTB: u32 = 0x00000002; // Port B Advanced High-Performance + // Bus +pub const SYSCTL_GPIOHBCTL_PORTA: u32 = 0x00000001; // Port A Advanced High-Performance + // Bus +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC2 register. +// +//***************************************************************************** +pub const SYSCTL_RCC2_USERCC2: u32 = 0x80000000; // Use RCC2 +pub const SYSCTL_RCC2_DIV400: u32 = 0x40000000; // Divide PLL as 400 MHz vs. 200 + // MHz +pub const SYSCTL_RCC2_SYSDIV2_M: u32 = 0x1F800000; // System Clock Divisor 2 +pub const SYSCTL_RCC2_SYSDIV2LSB: u32 = 0x00400000; // Additional LSB for SYSDIV2 +pub const SYSCTL_RCC2_USBPWRDN: u32 = 0x00004000; // Power-Down USB PLL +pub const SYSCTL_RCC2_PWRDN2: u32 = 0x00002000; // Power-Down PLL 2 +pub const SYSCTL_RCC2_BYPASS2: u32 = 0x00000800; // PLL Bypass 2 +pub const SYSCTL_RCC2_OSCSRC2_M: u32 = 0x00000070; // Oscillator Source 2 +pub const SYSCTL_RCC2_OSCSRC2_MO: u32 = 0x00000000; // MOSC +pub const SYSCTL_RCC2_OSCSRC2_IO: u32 = 0x00000010; // PIOSC +pub const SYSCTL_RCC2_OSCSRC2_IO4: u32 = 0x00000020; // PIOSC/4 +pub const SYSCTL_RCC2_OSCSRC2_30: u32 = 0x00000030; // LFIOSC +pub const SYSCTL_RCC2_OSCSRC2_32: u32 = 0x00000070; // 32.768 kHz +pub const SYSCTL_RCC2_SYSDIV2_S: u32 = 23; +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. +// +//***************************************************************************** +pub const SYSCTL_MOSCCTL_NOXTAL: u32 = 0x00000004; // No Crystal Connected +pub const SYSCTL_MOSCCTL_MOSCIM: u32 = 0x00000002; // MOSC Failure Action +pub const SYSCTL_MOSCCTL_CVAL: u32 = 0x00000001; // Clock Validation for MOSC +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC0 register. +// +//***************************************************************************** +pub const SYSCTL_RCGC0_WDT1: u32 = 0x10000000; // WDT1 Clock Gating Control +pub const SYSCTL_RCGC0_CAN1: u32 = 0x02000000; // CAN1 Clock Gating Control +pub const SYSCTL_RCGC0_CAN0: u32 = 0x01000000; // CAN0 Clock Gating Control +pub const SYSCTL_RCGC0_PWM0: u32 = 0x00100000; // PWM Clock Gating Control +pub const SYSCTL_RCGC0_ADC1: u32 = 0x00020000; // ADC1 Clock Gating Control +pub const SYSCTL_RCGC0_ADC0: u32 = 0x00010000; // ADC0 Clock Gating Control +pub const SYSCTL_RCGC0_ADC1SPD_M: u32 = 0x00000C00; // ADC1 Sample Speed +pub const SYSCTL_RCGC0_ADC1SPD_125K: u32 = 0x00000000; // 125K samples/second +pub const SYSCTL_RCGC0_ADC1SPD_250K: u32 = 0x00000400; // 250K samples/second +pub const SYSCTL_RCGC0_ADC1SPD_500K: u32 = 0x00000800; // 500K samples/second +pub const SYSCTL_RCGC0_ADC1SPD_1M: u32 = 0x00000C00; // 1M samples/second +pub const SYSCTL_RCGC0_ADC0SPD_M: u32 = 0x00000300; // ADC0 Sample Speed +pub const SYSCTL_RCGC0_ADC0SPD_125K: u32 = 0x00000000; // 125K samples/second +pub const SYSCTL_RCGC0_ADC0SPD_250K: u32 = 0x00000100; // 250K samples/second +pub const SYSCTL_RCGC0_ADC0SPD_500K: u32 = 0x00000200; // 500K samples/second +pub const SYSCTL_RCGC0_ADC0SPD_1M: u32 = 0x00000300; // 1M samples/second +pub const SYSCTL_RCGC0_HIB: u32 = 0x00000040; // HIB Clock Gating Control +pub const SYSCTL_RCGC0_WDT0: u32 = 0x00000008; // WDT0 Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC1 register. +// +//***************************************************************************** +pub const SYSCTL_RCGC1_COMP1: u32 = 0x02000000; // Analog Comparator 1 Clock Gating +pub const SYSCTL_RCGC1_COMP0: u32 = 0x01000000; // Analog Comparator 0 Clock Gating +pub const SYSCTL_RCGC1_TIMER3: u32 = 0x00080000; // Timer 3 Clock Gating Control +pub const SYSCTL_RCGC1_TIMER2: u32 = 0x00040000; // Timer 2 Clock Gating Control +pub const SYSCTL_RCGC1_TIMER1: u32 = 0x00020000; // Timer 1 Clock Gating Control +pub const SYSCTL_RCGC1_TIMER0: u32 = 0x00010000; // Timer 0 Clock Gating Control +pub const SYSCTL_RCGC1_I2C1: u32 = 0x00004000; // I2C1 Clock Gating Control +pub const SYSCTL_RCGC1_I2C0: u32 = 0x00001000; // I2C0 Clock Gating Control +pub const SYSCTL_RCGC1_QEI1: u32 = 0x00000200; // QEI1 Clock Gating Control +pub const SYSCTL_RCGC1_QEI0: u32 = 0x00000100; // QEI0 Clock Gating Control +pub const SYSCTL_RCGC1_SSI1: u32 = 0x00000020; // SSI1 Clock Gating Control +pub const SYSCTL_RCGC1_SSI0: u32 = 0x00000010; // SSI0 Clock Gating Control +pub const SYSCTL_RCGC1_UART2: u32 = 0x00000004; // UART2 Clock Gating Control +pub const SYSCTL_RCGC1_UART1: u32 = 0x00000002; // UART1 Clock Gating Control +pub const SYSCTL_RCGC1_UART0: u32 = 0x00000001; // UART0 Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC2 register. +// +//***************************************************************************** +pub const SYSCTL_RCGC2_USB0: u32 = 0x00010000; // USB0 Clock Gating Control +pub const SYSCTL_RCGC2_UDMA: u32 = 0x00002000; // Micro-DMA Clock Gating Control +pub const SYSCTL_RCGC2_GPIOF: u32 = 0x00000020; // Port F Clock Gating Control +pub const SYSCTL_RCGC2_GPIOE: u32 = 0x00000010; // Port E Clock Gating Control +pub const SYSCTL_RCGC2_GPIOD: u32 = 0x00000008; // Port D Clock Gating Control +pub const SYSCTL_RCGC2_GPIOC: u32 = 0x00000004; // Port C Clock Gating Control +pub const SYSCTL_RCGC2_GPIOB: u32 = 0x00000002; // Port B Clock Gating Control +pub const SYSCTL_RCGC2_GPIOA: u32 = 0x00000001; // Port A Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC0 register. +// +//***************************************************************************** +pub const SYSCTL_SCGC0_WDT1: u32 = 0x10000000; // WDT1 Clock Gating Control +pub const SYSCTL_SCGC0_CAN1: u32 = 0x02000000; // CAN1 Clock Gating Control +pub const SYSCTL_SCGC0_CAN0: u32 = 0x01000000; // CAN0 Clock Gating Control +pub const SYSCTL_SCGC0_PWM0: u32 = 0x00100000; // PWM Clock Gating Control +pub const SYSCTL_SCGC0_ADC1: u32 = 0x00020000; // ADC1 Clock Gating Control +pub const SYSCTL_SCGC0_ADC0: u32 = 0x00010000; // ADC0 Clock Gating Control +pub const SYSCTL_SCGC0_HIB: u32 = 0x00000040; // HIB Clock Gating Control +pub const SYSCTL_SCGC0_WDT0: u32 = 0x00000008; // WDT0 Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC1 register. +// +//***************************************************************************** +pub const SYSCTL_SCGC1_COMP1: u32 = 0x02000000; // Analog Comparator 1 Clock Gating +pub const SYSCTL_SCGC1_COMP0: u32 = 0x01000000; // Analog Comparator 0 Clock Gating +pub const SYSCTL_SCGC1_TIMER3: u32 = 0x00080000; // Timer 3 Clock Gating Control +pub const SYSCTL_SCGC1_TIMER2: u32 = 0x00040000; // Timer 2 Clock Gating Control +pub const SYSCTL_SCGC1_TIMER1: u32 = 0x00020000; // Timer 1 Clock Gating Control +pub const SYSCTL_SCGC1_TIMER0: u32 = 0x00010000; // Timer 0 Clock Gating Control +pub const SYSCTL_SCGC1_I2C1: u32 = 0x00004000; // I2C1 Clock Gating Control +pub const SYSCTL_SCGC1_I2C0: u32 = 0x00001000; // I2C0 Clock Gating Control +pub const SYSCTL_SCGC1_QEI1: u32 = 0x00000200; // QEI1 Clock Gating Control +pub const SYSCTL_SCGC1_QEI0: u32 = 0x00000100; // QEI0 Clock Gating Control +pub const SYSCTL_SCGC1_SSI1: u32 = 0x00000020; // SSI1 Clock Gating Control +pub const SYSCTL_SCGC1_SSI0: u32 = 0x00000010; // SSI0 Clock Gating Control +pub const SYSCTL_SCGC1_UART2: u32 = 0x00000004; // UART2 Clock Gating Control +pub const SYSCTL_SCGC1_UART1: u32 = 0x00000002; // UART1 Clock Gating Control +pub const SYSCTL_SCGC1_UART0: u32 = 0x00000001; // UART0 Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC2 register. +// +//***************************************************************************** +pub const SYSCTL_SCGC2_USB0: u32 = 0x00010000; // USB0 Clock Gating Control +pub const SYSCTL_SCGC2_UDMA: u32 = 0x00002000; // Micro-DMA Clock Gating Control +pub const SYSCTL_SCGC2_GPIOF: u32 = 0x00000020; // Port F Clock Gating Control +pub const SYSCTL_SCGC2_GPIOE: u32 = 0x00000010; // Port E Clock Gating Control +pub const SYSCTL_SCGC2_GPIOD: u32 = 0x00000008; // Port D Clock Gating Control +pub const SYSCTL_SCGC2_GPIOC: u32 = 0x00000004; // Port C Clock Gating Control +pub const SYSCTL_SCGC2_GPIOB: u32 = 0x00000002; // Port B Clock Gating Control +pub const SYSCTL_SCGC2_GPIOA: u32 = 0x00000001; // Port A Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC0 register. +// +//***************************************************************************** +pub const SYSCTL_DCGC0_WDT1: u32 = 0x10000000; // WDT1 Clock Gating Control +pub const SYSCTL_DCGC0_CAN1: u32 = 0x02000000; // CAN1 Clock Gating Control +pub const SYSCTL_DCGC0_CAN0: u32 = 0x01000000; // CAN0 Clock Gating Control +pub const SYSCTL_DCGC0_PWM0: u32 = 0x00100000; // PWM Clock Gating Control +pub const SYSCTL_DCGC0_ADC1: u32 = 0x00020000; // ADC1 Clock Gating Control +pub const SYSCTL_DCGC0_ADC0: u32 = 0x00010000; // ADC0 Clock Gating Control +pub const SYSCTL_DCGC0_HIB: u32 = 0x00000040; // HIB Clock Gating Control +pub const SYSCTL_DCGC0_WDT0: u32 = 0x00000008; // WDT0 Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC1 register. +// +//***************************************************************************** +pub const SYSCTL_DCGC1_COMP1: u32 = 0x02000000; // Analog Comparator 1 Clock Gating +pub const SYSCTL_DCGC1_COMP0: u32 = 0x01000000; // Analog Comparator 0 Clock Gating +pub const SYSCTL_DCGC1_TIMER3: u32 = 0x00080000; // Timer 3 Clock Gating Control +pub const SYSCTL_DCGC1_TIMER2: u32 = 0x00040000; // Timer 2 Clock Gating Control +pub const SYSCTL_DCGC1_TIMER1: u32 = 0x00020000; // Timer 1 Clock Gating Control +pub const SYSCTL_DCGC1_TIMER0: u32 = 0x00010000; // Timer 0 Clock Gating Control +pub const SYSCTL_DCGC1_I2C1: u32 = 0x00004000; // I2C1 Clock Gating Control +pub const SYSCTL_DCGC1_I2C0: u32 = 0x00001000; // I2C0 Clock Gating Control +pub const SYSCTL_DCGC1_QEI1: u32 = 0x00000200; // QEI1 Clock Gating Control +pub const SYSCTL_DCGC1_QEI0: u32 = 0x00000100; // QEI0 Clock Gating Control +pub const SYSCTL_DCGC1_SSI1: u32 = 0x00000020; // SSI1 Clock Gating Control +pub const SYSCTL_DCGC1_SSI0: u32 = 0x00000010; // SSI0 Clock Gating Control +pub const SYSCTL_DCGC1_UART2: u32 = 0x00000004; // UART2 Clock Gating Control +pub const SYSCTL_DCGC1_UART1: u32 = 0x00000002; // UART1 Clock Gating Control +pub const SYSCTL_DCGC1_UART0: u32 = 0x00000001; // UART0 Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC2 register. +// +//***************************************************************************** +pub const SYSCTL_DCGC2_USB0: u32 = 0x00010000; // USB0 Clock Gating Control +pub const SYSCTL_DCGC2_UDMA: u32 = 0x00002000; // Micro-DMA Clock Gating Control +pub const SYSCTL_DCGC2_GPIOF: u32 = 0x00000020; // Port F Clock Gating Control +pub const SYSCTL_DCGC2_GPIOE: u32 = 0x00000010; // Port E Clock Gating Control +pub const SYSCTL_DCGC2_GPIOD: u32 = 0x00000008; // Port D Clock Gating Control +pub const SYSCTL_DCGC2_GPIOC: u32 = 0x00000004; // Port C Clock Gating Control +pub const SYSCTL_DCGC2_GPIOB: u32 = 0x00000002; // Port B Clock Gating Control +pub const SYSCTL_DCGC2_GPIOA: u32 = 0x00000001; // Port A Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG +// register. +// +//***************************************************************************** +pub const SYSCTL_DSLPCLKCFG_D_M: u32 = 0x1F800000; // Divider Field Override +pub const SYSCTL_DSLPCLKCFG_O_M: u32 = 0x00000070; // Clock Source +pub const SYSCTL_DSLPCLKCFG_O_IGN: u32 = 0x00000000; // MOSC +pub const SYSCTL_DSLPCLKCFG_O_IO: u32 = 0x00000010; // PIOSC +pub const SYSCTL_DSLPCLKCFG_O_30: u32 = 0x00000030; // LFIOSC +pub const SYSCTL_DSLPCLKCFG_O_32: u32 = 0x00000070; // 32.768 kHz +pub const SYSCTL_DSLPCLKCFG_PIOSCPD: u32 = 0x00000002; // PIOSC Power Down Request +pub const SYSCTL_DSLPCLKCFG_D_S: u32 = 23; +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SYSPROP register. +// +//***************************************************************************** +pub const SYSCTL_SYSPROP_FPU: u32 = 0x00000001; // FPU Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCCAL +// register. +// +//***************************************************************************** +pub const SYSCTL_PIOSCCAL_UTEN: u32 = 0x80000000; // Use User Trim Value +pub const SYSCTL_PIOSCCAL_CAL: u32 = 0x00000200; // Start Calibration +pub const SYSCTL_PIOSCCAL_UPDATE: u32 = 0x00000100; // Update Trim +pub const SYSCTL_PIOSCCAL_UT_M: u32 = 0x0000007F; // User Trim Value +pub const SYSCTL_PIOSCCAL_UT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT +// register. +// +//***************************************************************************** +pub const SYSCTL_PIOSCSTAT_DT_M: u32 = 0x007F0000; // Default Trim Value +pub const SYSCTL_PIOSCSTAT_CR_M: u32 = 0x00000300; // Calibration Result +pub const SYSCTL_PIOSCSTAT_CRNONE: u32 = 0x00000000; // Calibration has not been + // attempted +pub const SYSCTL_PIOSCSTAT_CRPASS: u32 = 0x00000100; // The last calibration operation + // completed to meet 1% accuracy +pub const SYSCTL_PIOSCSTAT_CRFAIL: u32 = 0x00000200; // The last calibration operation + // failed to meet 1% accuracy +pub const SYSCTL_PIOSCSTAT_CT_M: u32 = 0x0000007F; // Calibration Trim Value +pub const SYSCTL_PIOSCSTAT_DT_S: u32 = 16; +pub const SYSCTL_PIOSCSTAT_CT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 +// register. +// +//***************************************************************************** +pub const SYSCTL_PLLFREQ0_MFRAC_M: u32 = 0x000FFC00; // PLL M Fractional Value +pub const SYSCTL_PLLFREQ0_MINT_M: u32 = 0x000003FF; // PLL M Integer Value +pub const SYSCTL_PLLFREQ0_MFRAC_S: u32 = 10; +pub const SYSCTL_PLLFREQ0_MINT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 +// register. +// +//***************************************************************************** +pub const SYSCTL_PLLFREQ1_Q_M: u32 = 0x00001F00; // PLL Q Value +pub const SYSCTL_PLLFREQ1_N_M: u32 = 0x0000001F; // PLL N Value +pub const SYSCTL_PLLFREQ1_Q_S: u32 = 8; +pub const SYSCTL_PLLFREQ1_N_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. +// +//***************************************************************************** +pub const SYSCTL_PLLSTAT_LOCK: u32 = 0x00000001; // PLL Lock +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG +// register. +// +//***************************************************************************** +pub const SYSCTL_SLPPWRCFG_FLASHPM_M: u32 = 0x00000030; // Flash Power Modes +pub const SYSCTL_SLPPWRCFG_FLASHPM_NRM: u32 = 0x00000000; // Active Mode +pub const SYSCTL_SLPPWRCFG_FLASHPM_SLP: u32 = 0x00000020; // Low Power Mode +pub const SYSCTL_SLPPWRCFG_SRAMPM_M: u32 = 0x00000003; // SRAM Power Modes +pub const SYSCTL_SLPPWRCFG_SRAMPM_NRM: u32 = 0x00000000; // Active Mode +pub const SYSCTL_SLPPWRCFG_SRAMPM_SBY: u32 = 0x00000001; // Standby Mode +pub const SYSCTL_SLPPWRCFG_SRAMPM_LP: u32 = 0x00000003; // Low Power Mode +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG +// register. +// +//***************************************************************************** +pub const SYSCTL_DSLPPWRCFG_FLASHPM_M: u32 = 0x00000030; // Flash Power Modes +pub const SYSCTL_DSLPPWRCFG_FLASHPM_NRM: u32 = 0x00000000; // Active Mode +pub const SYSCTL_DSLPPWRCFG_FLASHPM_SLP: u32 = 0x00000020; // Low Power Mode +pub const SYSCTL_DSLPPWRCFG_SRAMPM_M: u32 = 0x00000003; // SRAM Power Modes +pub const SYSCTL_DSLPPWRCFG_SRAMPM_NRM: u32 = 0x00000000; // Active Mode +pub const SYSCTL_DSLPPWRCFG_SRAMPM_SBY: u32 = 0x00000001; // Standby Mode +pub const SYSCTL_DSLPPWRCFG_SRAMPM_LP: u32 = 0x00000003; // Low Power Mode +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC9 register. +// +//***************************************************************************** +pub const SYSCTL_DC9_ADC1DC7: u32 = 0x00800000; // ADC1 DC7 Present +pub const SYSCTL_DC9_ADC1DC6: u32 = 0x00400000; // ADC1 DC6 Present +pub const SYSCTL_DC9_ADC1DC5: u32 = 0x00200000; // ADC1 DC5 Present +pub const SYSCTL_DC9_ADC1DC4: u32 = 0x00100000; // ADC1 DC4 Present +pub const SYSCTL_DC9_ADC1DC3: u32 = 0x00080000; // ADC1 DC3 Present +pub const SYSCTL_DC9_ADC1DC2: u32 = 0x00040000; // ADC1 DC2 Present +pub const SYSCTL_DC9_ADC1DC1: u32 = 0x00020000; // ADC1 DC1 Present +pub const SYSCTL_DC9_ADC1DC0: u32 = 0x00010000; // ADC1 DC0 Present +pub const SYSCTL_DC9_ADC0DC7: u32 = 0x00000080; // ADC0 DC7 Present +pub const SYSCTL_DC9_ADC0DC6: u32 = 0x00000040; // ADC0 DC6 Present +pub const SYSCTL_DC9_ADC0DC5: u32 = 0x00000020; // ADC0 DC5 Present +pub const SYSCTL_DC9_ADC0DC4: u32 = 0x00000010; // ADC0 DC4 Present +pub const SYSCTL_DC9_ADC0DC3: u32 = 0x00000008; // ADC0 DC3 Present +pub const SYSCTL_DC9_ADC0DC2: u32 = 0x00000004; // ADC0 DC2 Present +pub const SYSCTL_DC9_ADC0DC1: u32 = 0x00000002; // ADC0 DC1 Present +pub const SYSCTL_DC9_ADC0DC0: u32 = 0x00000001; // ADC0 DC0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. +// +//***************************************************************************** +pub const SYSCTL_NVMSTAT_FWB: u32 = 0x00000001; // 32 Word Flash Write Buffer + // Available +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOSPCTL +// register. +// +//***************************************************************************** +pub const SYSCTL_LDOSPCTL_VADJEN: u32 = 0x80000000; // Voltage Adjust Enable +pub const SYSCTL_LDOSPCTL_VLDO_M: u32 = 0x000000FF; // LDO Output Voltage +pub const SYSCTL_LDOSPCTL_VLDO_0_90V: u32 = 0x00000012; // 0.90 V +pub const SYSCTL_LDOSPCTL_VLDO_0_95V: u32 = 0x00000013; // 0.95 V +pub const SYSCTL_LDOSPCTL_VLDO_1_00V: u32 = 0x00000014; // 1.00 V +pub const SYSCTL_LDOSPCTL_VLDO_1_05V: u32 = 0x00000015; // 1.05 V +pub const SYSCTL_LDOSPCTL_VLDO_1_10V: u32 = 0x00000016; // 1.10 V +pub const SYSCTL_LDOSPCTL_VLDO_1_15V: u32 = 0x00000017; // 1.15 V +pub const SYSCTL_LDOSPCTL_VLDO_1_20V: u32 = 0x00000018; // 1.20 V +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDODPCTL +// register. +// +//***************************************************************************** +pub const SYSCTL_LDODPCTL_VADJEN: u32 = 0x80000000; // Voltage Adjust Enable +pub const SYSCTL_LDODPCTL_VLDO_M: u32 = 0x000000FF; // LDO Output Voltage +pub const SYSCTL_LDODPCTL_VLDO_0_90V: u32 = 0x00000012; // 0.90 V +pub const SYSCTL_LDODPCTL_VLDO_0_95V: u32 = 0x00000013; // 0.95 V +pub const SYSCTL_LDODPCTL_VLDO_1_00V: u32 = 0x00000014; // 1.00 V +pub const SYSCTL_LDODPCTL_VLDO_1_05V: u32 = 0x00000015; // 1.05 V +pub const SYSCTL_LDODPCTL_VLDO_1_10V: u32 = 0x00000016; // 1.10 V +pub const SYSCTL_LDODPCTL_VLDO_1_15V: u32 = 0x00000017; // 1.15 V +pub const SYSCTL_LDODPCTL_VLDO_1_20V: u32 = 0x00000018; // 1.20 V +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWD register. +// +//***************************************************************************** +pub const SYSCTL_PPWD_P1: u32 = 0x00000002; // Watchdog Timer 1 Present +pub const SYSCTL_PPWD_P0: u32 = 0x00000001; // Watchdog Timer 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPTIMER register. +// +//***************************************************************************** +pub const SYSCTL_PPTIMER_P5: u32 = 0x00000020; // 16/32-Bit General-Purpose Timer + // 5 Present +pub const SYSCTL_PPTIMER_P4: u32 = 0x00000010; // 16/32-Bit General-Purpose Timer + // 4 Present +pub const SYSCTL_PPTIMER_P3: u32 = 0x00000008; // 16/32-Bit General-Purpose Timer + // 3 Present +pub const SYSCTL_PPTIMER_P2: u32 = 0x00000004; // 16/32-Bit General-Purpose Timer + // 2 Present +pub const SYSCTL_PPTIMER_P1: u32 = 0x00000002; // 16/32-Bit General-Purpose Timer + // 1 Present +pub const SYSCTL_PPTIMER_P0: u32 = 0x00000001; // 16/32-Bit General-Purpose Timer + // 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPGPIO register. +// +//***************************************************************************** +pub const SYSCTL_PPGPIO_P14: u32 = 0x00004000; // GPIO Port Q Present +pub const SYSCTL_PPGPIO_P13: u32 = 0x00002000; // GPIO Port P Present +pub const SYSCTL_PPGPIO_P12: u32 = 0x00001000; // GPIO Port N Present +pub const SYSCTL_PPGPIO_P11: u32 = 0x00000800; // GPIO Port M Present +pub const SYSCTL_PPGPIO_P10: u32 = 0x00000400; // GPIO Port L Present +pub const SYSCTL_PPGPIO_P9: u32 = 0x00000200; // GPIO Port K Present +pub const SYSCTL_PPGPIO_P8: u32 = 0x00000100; // GPIO Port J Present +pub const SYSCTL_PPGPIO_P7: u32 = 0x00000080; // GPIO Port H Present +pub const SYSCTL_PPGPIO_P6: u32 = 0x00000040; // GPIO Port G Present +pub const SYSCTL_PPGPIO_P5: u32 = 0x00000020; // GPIO Port F Present +pub const SYSCTL_PPGPIO_P4: u32 = 0x00000010; // GPIO Port E Present +pub const SYSCTL_PPGPIO_P3: u32 = 0x00000008; // GPIO Port D Present +pub const SYSCTL_PPGPIO_P2: u32 = 0x00000004; // GPIO Port C Present +pub const SYSCTL_PPGPIO_P1: u32 = 0x00000002; // GPIO Port B Present +pub const SYSCTL_PPGPIO_P0: u32 = 0x00000001; // GPIO Port A Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPDMA register. +// +//***************************************************************************** +pub const SYSCTL_PPDMA_P0: u32 = 0x00000001; // uDMA Module Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPHIB register. +// +//***************************************************************************** +pub const SYSCTL_PPHIB_P0: u32 = 0x00000001; // Hibernation Module Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUART register. +// +//***************************************************************************** +pub const SYSCTL_PPUART_P7: u32 = 0x00000080; // UART Module 7 Present +pub const SYSCTL_PPUART_P6: u32 = 0x00000040; // UART Module 6 Present +pub const SYSCTL_PPUART_P5: u32 = 0x00000020; // UART Module 5 Present +pub const SYSCTL_PPUART_P4: u32 = 0x00000010; // UART Module 4 Present +pub const SYSCTL_PPUART_P3: u32 = 0x00000008; // UART Module 3 Present +pub const SYSCTL_PPUART_P2: u32 = 0x00000004; // UART Module 2 Present +pub const SYSCTL_PPUART_P1: u32 = 0x00000002; // UART Module 1 Present +pub const SYSCTL_PPUART_P0: u32 = 0x00000001; // UART Module 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPSSI register. +// +//***************************************************************************** +pub const SYSCTL_PPSSI_P3: u32 = 0x00000008; // SSI Module 3 Present +pub const SYSCTL_PPSSI_P2: u32 = 0x00000004; // SSI Module 2 Present +pub const SYSCTL_PPSSI_P1: u32 = 0x00000002; // SSI Module 1 Present +pub const SYSCTL_PPSSI_P0: u32 = 0x00000001; // SSI Module 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPI2C register. +// +//***************************************************************************** +pub const SYSCTL_PPI2C_P5: u32 = 0x00000020; // I2C Module 5 Present +pub const SYSCTL_PPI2C_P4: u32 = 0x00000010; // I2C Module 4 Present +pub const SYSCTL_PPI2C_P3: u32 = 0x00000008; // I2C Module 3 Present +pub const SYSCTL_PPI2C_P2: u32 = 0x00000004; // I2C Module 2 Present +pub const SYSCTL_PPI2C_P1: u32 = 0x00000002; // I2C Module 1 Present +pub const SYSCTL_PPI2C_P0: u32 = 0x00000001; // I2C Module 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUSB register. +// +//***************************************************************************** +pub const SYSCTL_PPUSB_P0: u32 = 0x00000001; // USB Module Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPCAN register. +// +//***************************************************************************** +pub const SYSCTL_PPCAN_P1: u32 = 0x00000002; // CAN Module 1 Present +pub const SYSCTL_PPCAN_P0: u32 = 0x00000001; // CAN Module 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPADC register. +// +//***************************************************************************** +pub const SYSCTL_PPADC_P1: u32 = 0x00000002; // ADC Module 1 Present +pub const SYSCTL_PPADC_P0: u32 = 0x00000001; // ADC Module 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPACMP register. +// +//***************************************************************************** +pub const SYSCTL_PPACMP_P0: u32 = 0x00000001; // Analog Comparator Module Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPWM register. +// +//***************************************************************************** +pub const SYSCTL_PPPWM_P1: u32 = 0x00000002; // PWM Module 1 Present +pub const SYSCTL_PPPWM_P0: u32 = 0x00000001; // PWM Module 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPQEI register. +// +//***************************************************************************** +pub const SYSCTL_PPQEI_P1: u32 = 0x00000002; // QEI Module 1 Present +pub const SYSCTL_PPQEI_P0: u32 = 0x00000001; // QEI Module 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEEPROM +// register. +// +//***************************************************************************** +pub const SYSCTL_PPEEPROM_P0: u32 = 0x00000001; // EEPROM Module Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWTIMER +// register. +// +//***************************************************************************** +pub const SYSCTL_PPWTIMER_P5: u32 = 0x00000020; // 32/64-Bit Wide General-Purpose + // Timer 5 Present +pub const SYSCTL_PPWTIMER_P4: u32 = 0x00000010; // 32/64-Bit Wide General-Purpose + // Timer 4 Present +pub const SYSCTL_PPWTIMER_P3: u32 = 0x00000008; // 32/64-Bit Wide General-Purpose + // Timer 3 Present +pub const SYSCTL_PPWTIMER_P2: u32 = 0x00000004; // 32/64-Bit Wide General-Purpose + // Timer 2 Present +pub const SYSCTL_PPWTIMER_P1: u32 = 0x00000002; // 32/64-Bit Wide General-Purpose + // Timer 1 Present +pub const SYSCTL_PPWTIMER_P0: u32 = 0x00000001; // 32/64-Bit Wide General-Purpose + // Timer 0 Present +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWD register. +// +//***************************************************************************** +pub const SYSCTL_SRWD_R1: u32 = 0x00000002; // Watchdog Timer 1 Software Reset +pub const SYSCTL_SRWD_R0: u32 = 0x00000001; // Watchdog Timer 0 Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRTIMER register. +// +//***************************************************************************** +pub const SYSCTL_SRTIMER_R5: u32 = 0x00000020; // 16/32-Bit General-Purpose Timer + // 5 Software Reset +pub const SYSCTL_SRTIMER_R4: u32 = 0x00000010; // 16/32-Bit General-Purpose Timer + // 4 Software Reset +pub const SYSCTL_SRTIMER_R3: u32 = 0x00000008; // 16/32-Bit General-Purpose Timer + // 3 Software Reset +pub const SYSCTL_SRTIMER_R2: u32 = 0x00000004; // 16/32-Bit General-Purpose Timer + // 2 Software Reset +pub const SYSCTL_SRTIMER_R1: u32 = 0x00000002; // 16/32-Bit General-Purpose Timer + // 1 Software Reset +pub const SYSCTL_SRTIMER_R0: u32 = 0x00000001; // 16/32-Bit General-Purpose Timer + // 0 Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRGPIO register. +// +//***************************************************************************** +pub const SYSCTL_SRGPIO_R5: u32 = 0x00000020; // GPIO Port F Software Reset +pub const SYSCTL_SRGPIO_R4: u32 = 0x00000010; // GPIO Port E Software Reset +pub const SYSCTL_SRGPIO_R3: u32 = 0x00000008; // GPIO Port D Software Reset +pub const SYSCTL_SRGPIO_R2: u32 = 0x00000004; // GPIO Port C Software Reset +pub const SYSCTL_SRGPIO_R1: u32 = 0x00000002; // GPIO Port B Software Reset +pub const SYSCTL_SRGPIO_R0: u32 = 0x00000001; // GPIO Port A Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRDMA register. +// +//***************************************************************************** +pub const SYSCTL_SRDMA_R0: u32 = 0x00000001; // uDMA Module Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRHIB register. +// +//***************************************************************************** +pub const SYSCTL_SRHIB_R0: u32 = 0x00000001; // Hibernation Module Software + // Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUART register. +// +//***************************************************************************** +pub const SYSCTL_SRUART_R7: u32 = 0x00000080; // UART Module 7 Software Reset +pub const SYSCTL_SRUART_R6: u32 = 0x00000040; // UART Module 6 Software Reset +pub const SYSCTL_SRUART_R5: u32 = 0x00000020; // UART Module 5 Software Reset +pub const SYSCTL_SRUART_R4: u32 = 0x00000010; // UART Module 4 Software Reset +pub const SYSCTL_SRUART_R3: u32 = 0x00000008; // UART Module 3 Software Reset +pub const SYSCTL_SRUART_R2: u32 = 0x00000004; // UART Module 2 Software Reset +pub const SYSCTL_SRUART_R1: u32 = 0x00000002; // UART Module 1 Software Reset +pub const SYSCTL_SRUART_R0: u32 = 0x00000001; // UART Module 0 Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRSSI register. +// +//***************************************************************************** +pub const SYSCTL_SRSSI_R3: u32 = 0x00000008; // SSI Module 3 Software Reset +pub const SYSCTL_SRSSI_R2: u32 = 0x00000004; // SSI Module 2 Software Reset +pub const SYSCTL_SRSSI_R1: u32 = 0x00000002; // SSI Module 1 Software Reset +pub const SYSCTL_SRSSI_R0: u32 = 0x00000001; // SSI Module 0 Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRI2C register. +// +//***************************************************************************** +pub const SYSCTL_SRI2C_R3: u32 = 0x00000008; // I2C Module 3 Software Reset +pub const SYSCTL_SRI2C_R2: u32 = 0x00000004; // I2C Module 2 Software Reset +pub const SYSCTL_SRI2C_R1: u32 = 0x00000002; // I2C Module 1 Software Reset +pub const SYSCTL_SRI2C_R0: u32 = 0x00000001; // I2C Module 0 Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUSB register. +// +//***************************************************************************** +pub const SYSCTL_SRUSB_R0: u32 = 0x00000001; // USB Module Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCAN register. +// +//***************************************************************************** +pub const SYSCTL_SRCAN_R1: u32 = 0x00000002; // CAN Module 1 Software Reset +pub const SYSCTL_SRCAN_R0: u32 = 0x00000001; // CAN Module 0 Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRADC register. +// +//***************************************************************************** +pub const SYSCTL_SRADC_R1: u32 = 0x00000002; // ADC Module 1 Software Reset +pub const SYSCTL_SRADC_R0: u32 = 0x00000001; // ADC Module 0 Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRACMP register. +// +//***************************************************************************** +pub const SYSCTL_SRACMP_R0: u32 = 0x00000001; // Analog Comparator Module 0 + // Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRPWM register. +// +//***************************************************************************** +pub const SYSCTL_SRPWM_R1: u32 = 0x00000002; // PWM Module 1 Software Reset +pub const SYSCTL_SRPWM_R0: u32 = 0x00000001; // PWM Module 0 Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRQEI register. +// +//***************************************************************************** +pub const SYSCTL_SRQEI_R1: u32 = 0x00000002; // QEI Module 1 Software Reset +pub const SYSCTL_SRQEI_R0: u32 = 0x00000001; // QEI Module 0 Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREEPROM +// register. +// +//***************************************************************************** +pub const SYSCTL_SREEPROM_R0: u32 = 0x00000001; // EEPROM Module Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWTIMER +// register. +// +//***************************************************************************** +pub const SYSCTL_SRWTIMER_R5: u32 = 0x00000020; // 32/64-Bit Wide General-Purpose + // Timer 5 Software Reset +pub const SYSCTL_SRWTIMER_R4: u32 = 0x00000010; // 32/64-Bit Wide General-Purpose + // Timer 4 Software Reset +pub const SYSCTL_SRWTIMER_R3: u32 = 0x00000008; // 32/64-Bit Wide General-Purpose + // Timer 3 Software Reset +pub const SYSCTL_SRWTIMER_R2: u32 = 0x00000004; // 32/64-Bit Wide General-Purpose + // Timer 2 Software Reset +pub const SYSCTL_SRWTIMER_R1: u32 = 0x00000002; // 32/64-Bit Wide General-Purpose + // Timer 1 Software Reset +pub const SYSCTL_SRWTIMER_R0: u32 = 0x00000001; // 32/64-Bit Wide General-Purpose + // Timer 0 Software Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWD register. +// +//***************************************************************************** +pub const SYSCTL_RCGCWD_R1: u32 = 0x00000002; // Watchdog Timer 1 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCWD_R0: u32 = 0x00000001; // Watchdog Timer 0 Run Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCTIMER +// register. +// +//***************************************************************************** +pub const SYSCTL_RCGCTIMER_R5: u32 = 0x00000020; // 16/32-Bit General-Purpose Timer + // 5 Run Mode Clock Gating Control +pub const SYSCTL_RCGCTIMER_R4: u32 = 0x00000010; // 16/32-Bit General-Purpose Timer + // 4 Run Mode Clock Gating Control +pub const SYSCTL_RCGCTIMER_R3: u32 = 0x00000008; // 16/32-Bit General-Purpose Timer + // 3 Run Mode Clock Gating Control +pub const SYSCTL_RCGCTIMER_R2: u32 = 0x00000004; // 16/32-Bit General-Purpose Timer + // 2 Run Mode Clock Gating Control +pub const SYSCTL_RCGCTIMER_R1: u32 = 0x00000002; // 16/32-Bit General-Purpose Timer + // 1 Run Mode Clock Gating Control +pub const SYSCTL_RCGCTIMER_R0: u32 = 0x00000001; // 16/32-Bit General-Purpose Timer + // 0 Run Mode Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCGPIO +// register. +// +//***************************************************************************** +pub const SYSCTL_RCGCGPIO_R5: u32 = 0x00000020; // GPIO Port F Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCGPIO_R4: u32 = 0x00000010; // GPIO Port E Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCGPIO_R3: u32 = 0x00000008; // GPIO Port D Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCGPIO_R2: u32 = 0x00000004; // GPIO Port C Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCGPIO_R1: u32 = 0x00000002; // GPIO Port B Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCGPIO_R0: u32 = 0x00000001; // GPIO Port A Run Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. +// +//***************************************************************************** +pub const SYSCTL_RCGCDMA_R0: u32 = 0x00000001; // uDMA Module Run Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. +// +//***************************************************************************** +pub const SYSCTL_RCGCHIB_R0: u32 = 0x00000001; // Hibernation Module Run Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUART +// register. +// +//***************************************************************************** +pub const SYSCTL_RCGCUART_R7: u32 = 0x00000080; // UART Module 7 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCUART_R6: u32 = 0x00000040; // UART Module 6 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCUART_R5: u32 = 0x00000020; // UART Module 5 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCUART_R4: u32 = 0x00000010; // UART Module 4 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCUART_R3: u32 = 0x00000008; // UART Module 3 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCUART_R2: u32 = 0x00000004; // UART Module 2 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCUART_R1: u32 = 0x00000002; // UART Module 1 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCUART_R0: u32 = 0x00000001; // UART Module 0 Run Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. +// +//***************************************************************************** +pub const SYSCTL_RCGCSSI_R3: u32 = 0x00000008; // SSI Module 3 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCSSI_R2: u32 = 0x00000004; // SSI Module 2 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCSSI_R1: u32 = 0x00000002; // SSI Module 1 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCSSI_R0: u32 = 0x00000001; // SSI Module 0 Run Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. +// +//***************************************************************************** +pub const SYSCTL_RCGCI2C_R3: u32 = 0x00000008; // I2C Module 3 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCI2C_R2: u32 = 0x00000004; // I2C Module 2 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCI2C_R1: u32 = 0x00000002; // I2C Module 1 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCI2C_R0: u32 = 0x00000001; // I2C Module 0 Run Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. +// +//***************************************************************************** +pub const SYSCTL_RCGCUSB_R0: u32 = 0x00000001; // USB Module Run Mode Clock Gating + // Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. +// +//***************************************************************************** +pub const SYSCTL_RCGCCAN_R1: u32 = 0x00000002; // CAN Module 1 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCCAN_R0: u32 = 0x00000001; // CAN Module 0 Run Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCADC register. +// +//***************************************************************************** +pub const SYSCTL_RCGCADC_R1: u32 = 0x00000002; // ADC Module 1 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCADC_R0: u32 = 0x00000001; // ADC Module 0 Run Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCACMP +// register. +// +//***************************************************************************** +pub const SYSCTL_RCGCACMP_R0: u32 = 0x00000001; // Analog Comparator Module 0 Run + // Mode Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. +// +//***************************************************************************** +pub const SYSCTL_RCGCPWM_R1: u32 = 0x00000002; // PWM Module 1 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCPWM_R0: u32 = 0x00000001; // PWM Module 0 Run Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. +// +//***************************************************************************** +pub const SYSCTL_RCGCQEI_R1: u32 = 0x00000002; // QEI Module 1 Run Mode Clock + // Gating Control +pub const SYSCTL_RCGCQEI_R0: u32 = 0x00000001; // QEI Module 0 Run Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM +// register. +// +//***************************************************************************** +pub const SYSCTL_RCGCEEPROM_R0: u32 = 0x00000001; // EEPROM Module Run Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER +// register. +// +//***************************************************************************** +pub const SYSCTL_RCGCWTIMER_R5: u32 = 0x00000020; // 32/64-Bit Wide General-Purpose + // Timer 5 Run Mode Clock Gating + // Control +pub const SYSCTL_RCGCWTIMER_R4: u32 = 0x00000010; // 32/64-Bit Wide General-Purpose + // Timer 4 Run Mode Clock Gating + // Control +pub const SYSCTL_RCGCWTIMER_R3: u32 = 0x00000008; // 32/64-Bit Wide General-Purpose + // Timer 3 Run Mode Clock Gating + // Control +pub const SYSCTL_RCGCWTIMER_R2: u32 = 0x00000004; // 32/64-Bit Wide General-Purpose + // Timer 2 Run Mode Clock Gating + // Control +pub const SYSCTL_RCGCWTIMER_R1: u32 = 0x00000002; // 32/64-Bit Wide General-Purpose + // Timer 1 Run Mode Clock Gating + // Control +pub const SYSCTL_RCGCWTIMER_R0: u32 = 0x00000001; // 32/64-Bit Wide General-Purpose + // Timer 0 Run Mode Clock Gating + // Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWD register. +// +//***************************************************************************** +pub const SYSCTL_SCGCWD_S1: u32 = 0x00000002; // Watchdog Timer 1 Sleep Mode + // Clock Gating Control +pub const SYSCTL_SCGCWD_S0: u32 = 0x00000001; // Watchdog Timer 0 Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCTIMER +// register. +// +//***************************************************************************** +pub const SYSCTL_SCGCTIMER_S5: u32 = 0x00000020; // 16/32-Bit General-Purpose Timer + // 5 Sleep Mode Clock Gating + // Control +pub const SYSCTL_SCGCTIMER_S4: u32 = 0x00000010; // 16/32-Bit General-Purpose Timer + // 4 Sleep Mode Clock Gating + // Control +pub const SYSCTL_SCGCTIMER_S3: u32 = 0x00000008; // 16/32-Bit General-Purpose Timer + // 3 Sleep Mode Clock Gating + // Control +pub const SYSCTL_SCGCTIMER_S2: u32 = 0x00000004; // 16/32-Bit General-Purpose Timer + // 2 Sleep Mode Clock Gating + // Control +pub const SYSCTL_SCGCTIMER_S1: u32 = 0x00000002; // 16/32-Bit General-Purpose Timer + // 1 Sleep Mode Clock Gating + // Control +pub const SYSCTL_SCGCTIMER_S0: u32 = 0x00000001; // 16/32-Bit General-Purpose Timer + // 0 Sleep Mode Clock Gating + // Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCGPIO +// register. +// +//***************************************************************************** +pub const SYSCTL_SCGCGPIO_S5: u32 = 0x00000020; // GPIO Port F Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCGPIO_S4: u32 = 0x00000010; // GPIO Port E Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCGPIO_S3: u32 = 0x00000008; // GPIO Port D Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCGPIO_S2: u32 = 0x00000004; // GPIO Port C Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCGPIO_S1: u32 = 0x00000002; // GPIO Port B Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCGPIO_S0: u32 = 0x00000001; // GPIO Port A Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. +// +//***************************************************************************** +pub const SYSCTL_SCGCDMA_S0: u32 = 0x00000001; // uDMA Module Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. +// +//***************************************************************************** +pub const SYSCTL_SCGCHIB_S0: u32 = 0x00000001; // Hibernation Module Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUART +// register. +// +//***************************************************************************** +pub const SYSCTL_SCGCUART_S7: u32 = 0x00000080; // UART Module 7 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCUART_S6: u32 = 0x00000040; // UART Module 6 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCUART_S5: u32 = 0x00000020; // UART Module 5 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCUART_S4: u32 = 0x00000010; // UART Module 4 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCUART_S3: u32 = 0x00000008; // UART Module 3 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCUART_S2: u32 = 0x00000004; // UART Module 2 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCUART_S1: u32 = 0x00000002; // UART Module 1 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCUART_S0: u32 = 0x00000001; // UART Module 0 Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. +// +//***************************************************************************** +pub const SYSCTL_SCGCSSI_S3: u32 = 0x00000008; // SSI Module 3 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCSSI_S2: u32 = 0x00000004; // SSI Module 2 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCSSI_S1: u32 = 0x00000002; // SSI Module 1 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCSSI_S0: u32 = 0x00000001; // SSI Module 0 Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. +// +//***************************************************************************** +pub const SYSCTL_SCGCI2C_S3: u32 = 0x00000008; // I2C Module 3 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCI2C_S2: u32 = 0x00000004; // I2C Module 2 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCI2C_S1: u32 = 0x00000002; // I2C Module 1 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCI2C_S0: u32 = 0x00000001; // I2C Module 0 Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. +// +//***************************************************************************** +pub const SYSCTL_SCGCUSB_S0: u32 = 0x00000001; // USB Module Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. +// +//***************************************************************************** +pub const SYSCTL_SCGCCAN_S1: u32 = 0x00000002; // CAN Module 1 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCCAN_S0: u32 = 0x00000001; // CAN Module 0 Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCADC register. +// +//***************************************************************************** +pub const SYSCTL_SCGCADC_S1: u32 = 0x00000002; // ADC Module 1 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCADC_S0: u32 = 0x00000001; // ADC Module 0 Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCACMP +// register. +// +//***************************************************************************** +pub const SYSCTL_SCGCACMP_S0: u32 = 0x00000001; // Analog Comparator Module 0 Sleep + // Mode Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. +// +//***************************************************************************** +pub const SYSCTL_SCGCPWM_S1: u32 = 0x00000002; // PWM Module 1 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCPWM_S0: u32 = 0x00000001; // PWM Module 0 Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. +// +//***************************************************************************** +pub const SYSCTL_SCGCQEI_S1: u32 = 0x00000002; // QEI Module 1 Sleep Mode Clock + // Gating Control +pub const SYSCTL_SCGCQEI_S0: u32 = 0x00000001; // QEI Module 0 Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM +// register. +// +//***************************************************************************** +pub const SYSCTL_SCGCEEPROM_S0: u32 = 0x00000001; // EEPROM Module Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER +// register. +// +//***************************************************************************** +pub const SYSCTL_SCGCWTIMER_S5: u32 = 0x00000020; // 32/64-Bit Wide General-Purpose + // Timer 5 Sleep Mode Clock Gating + // Control +pub const SYSCTL_SCGCWTIMER_S4: u32 = 0x00000010; // 32/64-Bit Wide General-Purpose + // Timer 4 Sleep Mode Clock Gating + // Control +pub const SYSCTL_SCGCWTIMER_S3: u32 = 0x00000008; // 32/64-Bit Wide General-Purpose + // Timer 3 Sleep Mode Clock Gating + // Control +pub const SYSCTL_SCGCWTIMER_S2: u32 = 0x00000004; // 32/64-Bit Wide General-Purpose + // Timer 2 Sleep Mode Clock Gating + // Control +pub const SYSCTL_SCGCWTIMER_S1: u32 = 0x00000002; // 32/64-Bit Wide General-Purpose + // Timer 1 Sleep Mode Clock Gating + // Control +pub const SYSCTL_SCGCWTIMER_S0: u32 = 0x00000001; // 32/64-Bit Wide General-Purpose + // Timer 0 Sleep Mode Clock Gating + // Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWD register. +// +//***************************************************************************** +pub const SYSCTL_DCGCWD_D1: u32 = 0x00000002; // Watchdog Timer 1 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCWD_D0: u32 = 0x00000001; // Watchdog Timer 0 Deep-Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCTIMER +// register. +// +//***************************************************************************** +pub const SYSCTL_DCGCTIMER_D5: u32 = 0x00000020; // 16/32-Bit General-Purpose Timer + // 5 Deep-Sleep Mode Clock Gating + // Control +pub const SYSCTL_DCGCTIMER_D4: u32 = 0x00000010; // 16/32-Bit General-Purpose Timer + // 4 Deep-Sleep Mode Clock Gating + // Control +pub const SYSCTL_DCGCTIMER_D3: u32 = 0x00000008; // 16/32-Bit General-Purpose Timer + // 3 Deep-Sleep Mode Clock Gating + // Control +pub const SYSCTL_DCGCTIMER_D2: u32 = 0x00000004; // 16/32-Bit General-Purpose Timer + // 2 Deep-Sleep Mode Clock Gating + // Control +pub const SYSCTL_DCGCTIMER_D1: u32 = 0x00000002; // 16/32-Bit General-Purpose Timer + // 1 Deep-Sleep Mode Clock Gating + // Control +pub const SYSCTL_DCGCTIMER_D0: u32 = 0x00000001; // 16/32-Bit General-Purpose Timer + // 0 Deep-Sleep Mode Clock Gating + // Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCGPIO +// register. +// +//***************************************************************************** +pub const SYSCTL_DCGCGPIO_D5: u32 = 0x00000020; // GPIO Port F Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCGPIO_D4: u32 = 0x00000010; // GPIO Port E Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCGPIO_D3: u32 = 0x00000008; // GPIO Port D Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCGPIO_D2: u32 = 0x00000004; // GPIO Port C Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCGPIO_D1: u32 = 0x00000002; // GPIO Port B Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCGPIO_D0: u32 = 0x00000001; // GPIO Port A Deep-Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. +// +//***************************************************************************** +pub const SYSCTL_DCGCDMA_D0: u32 = 0x00000001; // uDMA Module Deep-Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. +// +//***************************************************************************** +pub const SYSCTL_DCGCHIB_D0: u32 = 0x00000001; // Hibernation Module Deep-Sleep + // Mode Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUART +// register. +// +//***************************************************************************** +pub const SYSCTL_DCGCUART_D7: u32 = 0x00000080; // UART Module 7 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCUART_D6: u32 = 0x00000040; // UART Module 6 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCUART_D5: u32 = 0x00000020; // UART Module 5 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCUART_D4: u32 = 0x00000010; // UART Module 4 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCUART_D3: u32 = 0x00000008; // UART Module 3 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCUART_D2: u32 = 0x00000004; // UART Module 2 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCUART_D1: u32 = 0x00000002; // UART Module 1 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCUART_D0: u32 = 0x00000001; // UART Module 0 Deep-Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. +// +//***************************************************************************** +pub const SYSCTL_DCGCSSI_D3: u32 = 0x00000008; // SSI Module 3 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCSSI_D2: u32 = 0x00000004; // SSI Module 2 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCSSI_D1: u32 = 0x00000002; // SSI Module 1 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCSSI_D0: u32 = 0x00000001; // SSI Module 0 Deep-Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. +// +//***************************************************************************** +pub const SYSCTL_DCGCI2C_D3: u32 = 0x00000008; // I2C Module 3 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCI2C_D2: u32 = 0x00000004; // I2C Module 2 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCI2C_D1: u32 = 0x00000002; // I2C Module 1 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCI2C_D0: u32 = 0x00000001; // I2C Module 0 Deep-Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. +// +//***************************************************************************** +pub const SYSCTL_DCGCUSB_D0: u32 = 0x00000001; // USB Module Deep-Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. +// +//***************************************************************************** +pub const SYSCTL_DCGCCAN_D1: u32 = 0x00000002; // CAN Module 1 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCCAN_D0: u32 = 0x00000001; // CAN Module 0 Deep-Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCADC register. +// +//***************************************************************************** +pub const SYSCTL_DCGCADC_D1: u32 = 0x00000002; // ADC Module 1 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCADC_D0: u32 = 0x00000001; // ADC Module 0 Deep-Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCACMP +// register. +// +//***************************************************************************** +pub const SYSCTL_DCGCACMP_D0: u32 = 0x00000001; // Analog Comparator Module 0 + // Deep-Sleep Mode Clock Gating + // Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. +// +//***************************************************************************** +pub const SYSCTL_DCGCPWM_D1: u32 = 0x00000002; // PWM Module 1 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCPWM_D0: u32 = 0x00000001; // PWM Module 0 Deep-Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. +// +//***************************************************************************** +pub const SYSCTL_DCGCQEI_D1: u32 = 0x00000002; // QEI Module 1 Deep-Sleep Mode + // Clock Gating Control +pub const SYSCTL_DCGCQEI_D0: u32 = 0x00000001; // QEI Module 0 Deep-Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM +// register. +// +//***************************************************************************** +pub const SYSCTL_DCGCEEPROM_D0: u32 = 0x00000001; // EEPROM Module Deep-Sleep Mode + // Clock Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER +// register. +// +//***************************************************************************** +pub const SYSCTL_DCGCWTIMER_D5: u32 = 0x00000020; // 32/64-Bit Wide General-Purpose + // Timer 5 Deep-Sleep Mode Clock + // Gating Control +pub const SYSCTL_DCGCWTIMER_D4: u32 = 0x00000010; // 32/64-Bit Wide General-Purpose + // Timer 4 Deep-Sleep Mode Clock + // Gating Control +pub const SYSCTL_DCGCWTIMER_D3: u32 = 0x00000008; // 32/64-Bit Wide General-Purpose + // Timer 3 Deep-Sleep Mode Clock + // Gating Control +pub const SYSCTL_DCGCWTIMER_D2: u32 = 0x00000004; // 32/64-Bit Wide General-Purpose + // Timer 2 Deep-Sleep Mode Clock + // Gating Control +pub const SYSCTL_DCGCWTIMER_D1: u32 = 0x00000002; // 32/64-Bit Wide General-Purpose + // Timer 1 Deep-Sleep Mode Clock + // Gating Control +pub const SYSCTL_DCGCWTIMER_D0: u32 = 0x00000001; // 32/64-Bit Wide General-Purpose + // Timer 0 Deep-Sleep Mode Clock + // Gating Control +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWD register. +// +//***************************************************************************** +pub const SYSCTL_PRWD_R1: u32 = 0x00000002; // Watchdog Timer 1 Peripheral + // Ready +pub const SYSCTL_PRWD_R0: u32 = 0x00000001; // Watchdog Timer 0 Peripheral + // Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRTIMER register. +// +//***************************************************************************** +pub const SYSCTL_PRTIMER_R5: u32 = 0x00000020; // 16/32-Bit General-Purpose Timer + // 5 Peripheral Ready +pub const SYSCTL_PRTIMER_R4: u32 = 0x00000010; // 16/32-Bit General-Purpose Timer + // 4 Peripheral Ready +pub const SYSCTL_PRTIMER_R3: u32 = 0x00000008; // 16/32-Bit General-Purpose Timer + // 3 Peripheral Ready +pub const SYSCTL_PRTIMER_R2: u32 = 0x00000004; // 16/32-Bit General-Purpose Timer + // 2 Peripheral Ready +pub const SYSCTL_PRTIMER_R1: u32 = 0x00000002; // 16/32-Bit General-Purpose Timer + // 1 Peripheral Ready +pub const SYSCTL_PRTIMER_R0: u32 = 0x00000001; // 16/32-Bit General-Purpose Timer + // 0 Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRGPIO register. +// +//***************************************************************************** +pub const SYSCTL_PRGPIO_R5: u32 = 0x00000020; // GPIO Port F Peripheral Ready +pub const SYSCTL_PRGPIO_R4: u32 = 0x00000010; // GPIO Port E Peripheral Ready +pub const SYSCTL_PRGPIO_R3: u32 = 0x00000008; // GPIO Port D Peripheral Ready +pub const SYSCTL_PRGPIO_R2: u32 = 0x00000004; // GPIO Port C Peripheral Ready +pub const SYSCTL_PRGPIO_R1: u32 = 0x00000002; // GPIO Port B Peripheral Ready +pub const SYSCTL_PRGPIO_R0: u32 = 0x00000001; // GPIO Port A Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRDMA register. +// +//***************************************************************************** +pub const SYSCTL_PRDMA_R0: u32 = 0x00000001; // uDMA Module Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRHIB register. +// +//***************************************************************************** +pub const SYSCTL_PRHIB_R0: u32 = 0x00000001; // Hibernation Module Peripheral + // Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUART register. +// +//***************************************************************************** +pub const SYSCTL_PRUART_R7: u32 = 0x00000080; // UART Module 7 Peripheral Ready +pub const SYSCTL_PRUART_R6: u32 = 0x00000040; // UART Module 6 Peripheral Ready +pub const SYSCTL_PRUART_R5: u32 = 0x00000020; // UART Module 5 Peripheral Ready +pub const SYSCTL_PRUART_R4: u32 = 0x00000010; // UART Module 4 Peripheral Ready +pub const SYSCTL_PRUART_R3: u32 = 0x00000008; // UART Module 3 Peripheral Ready +pub const SYSCTL_PRUART_R2: u32 = 0x00000004; // UART Module 2 Peripheral Ready +pub const SYSCTL_PRUART_R1: u32 = 0x00000002; // UART Module 1 Peripheral Ready +pub const SYSCTL_PRUART_R0: u32 = 0x00000001; // UART Module 0 Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRSSI register. +// +//***************************************************************************** +pub const SYSCTL_PRSSI_R3: u32 = 0x00000008; // SSI Module 3 Peripheral Ready +pub const SYSCTL_PRSSI_R2: u32 = 0x00000004; // SSI Module 2 Peripheral Ready +pub const SYSCTL_PRSSI_R1: u32 = 0x00000002; // SSI Module 1 Peripheral Ready +pub const SYSCTL_PRSSI_R0: u32 = 0x00000001; // SSI Module 0 Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRI2C register. +// +//***************************************************************************** +pub const SYSCTL_PRI2C_R3: u32 = 0x00000008; // I2C Module 3 Peripheral Ready +pub const SYSCTL_PRI2C_R2: u32 = 0x00000004; // I2C Module 2 Peripheral Ready +pub const SYSCTL_PRI2C_R1: u32 = 0x00000002; // I2C Module 1 Peripheral Ready +pub const SYSCTL_PRI2C_R0: u32 = 0x00000001; // I2C Module 0 Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUSB register. +// +//***************************************************************************** +pub const SYSCTL_PRUSB_R0: u32 = 0x00000001; // USB Module Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRCAN register. +// +//***************************************************************************** +pub const SYSCTL_PRCAN_R1: u32 = 0x00000002; // CAN Module 1 Peripheral Ready +pub const SYSCTL_PRCAN_R0: u32 = 0x00000001; // CAN Module 0 Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRADC register. +// +//***************************************************************************** +pub const SYSCTL_PRADC_R1: u32 = 0x00000002; // ADC Module 1 Peripheral Ready +pub const SYSCTL_PRADC_R0: u32 = 0x00000001; // ADC Module 0 Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRACMP register. +// +//***************************************************************************** +pub const SYSCTL_PRACMP_R0: u32 = 0x00000001; // Analog Comparator Module 0 + // Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRPWM register. +// +//***************************************************************************** +pub const SYSCTL_PRPWM_R1: u32 = 0x00000002; // PWM Module 1 Peripheral Ready +pub const SYSCTL_PRPWM_R0: u32 = 0x00000001; // PWM Module 0 Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRQEI register. +// +//***************************************************************************** +pub const SYSCTL_PRQEI_R1: u32 = 0x00000002; // QEI Module 1 Peripheral Ready +pub const SYSCTL_PRQEI_R0: u32 = 0x00000001; // QEI Module 0 Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREEPROM +// register. +// +//***************************************************************************** +pub const SYSCTL_PREEPROM_R0: u32 = 0x00000001; // EEPROM Module Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWTIMER +// register. +// +//***************************************************************************** +pub const SYSCTL_PRWTIMER_R5: u32 = 0x00000020; // 32/64-Bit Wide General-Purpose + // Timer 5 Peripheral Ready +pub const SYSCTL_PRWTIMER_R4: u32 = 0x00000010; // 32/64-Bit Wide General-Purpose + // Timer 4 Peripheral Ready +pub const SYSCTL_PRWTIMER_R3: u32 = 0x00000008; // 32/64-Bit Wide General-Purpose + // Timer 3 Peripheral Ready +pub const SYSCTL_PRWTIMER_R2: u32 = 0x00000004; // 32/64-Bit Wide General-Purpose + // Timer 2 Peripheral Ready +pub const SYSCTL_PRWTIMER_R1: u32 = 0x00000002; // 32/64-Bit Wide General-Purpose + // Timer 1 Peripheral Ready +pub const SYSCTL_PRWTIMER_R0: u32 = 0x00000001; // 32/64-Bit Wide General-Purpose + // Timer 0 Peripheral Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_STAT register. +// +//***************************************************************************** +pub const UDMA_STAT_DMACHANS_M: u32 = 0x001F0000; // Available uDMA Channels Minus 1 +pub const UDMA_STAT_STATE_M: u32 = 0x000000F0; // Control State Machine Status +pub const UDMA_STAT_STATE_IDLE: u32 = 0x00000000; // Idle +pub const UDMA_STAT_STATE_RD_CTRL: u32 = 0x00000010; // Reading channel controller data +pub const UDMA_STAT_STATE_RD_SRCENDP: u32 = 0x00000020; // Reading source end pointer +pub const UDMA_STAT_STATE_RD_DSTENDP: u32 = 0x00000030; // Reading destination end pointer +pub const UDMA_STAT_STATE_RD_SRCDAT: u32 = 0x00000040; // Reading source data +pub const UDMA_STAT_STATE_WR_DSTDAT: u32 = 0x00000050; // Writing destination data +pub const UDMA_STAT_STATE_WAIT: u32 = 0x00000060; // Waiting for uDMA request to + // clear +pub const UDMA_STAT_STATE_WR_CTRL: u32 = 0x00000070; // Writing channel controller data +pub const UDMA_STAT_STATE_STALL: u32 = 0x00000080; // Stalled +pub const UDMA_STAT_STATE_DONE: u32 = 0x00000090; // Done +pub const UDMA_STAT_STATE_UNDEF: u32 = 0x000000A0; // Undefined +pub const UDMA_STAT_MASTEN: u32 = 0x00000001; // Master Enable Status +pub const UDMA_STAT_DMACHANS_S: u32 = 16; +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CFG register. +// +//***************************************************************************** +pub const UDMA_CFG_MASTEN: u32 = 0x00000001; // Controller Master Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CTLBASE register. +// +//***************************************************************************** +pub const UDMA_CTLBASE_ADDR_M: u32 = 0xFFFFFC00; // Channel Control Base Address +pub const UDMA_CTLBASE_ADDR_S: u32 = 10; +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTBASE register. +// +//***************************************************************************** +pub const UDMA_ALTBASE_ADDR_M: u32 = 0xFFFFFFFF; // Alternate Channel Address + // Pointer +pub const UDMA_ALTBASE_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_WAITSTAT register. +// +//***************************************************************************** +pub const UDMA_WAITSTAT_WAITREQ_M: u32 = 0xFFFFFFFF; // Channel [n] Wait Status +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_SWREQ register. +// +//***************************************************************************** +pub const UDMA_SWREQ_M: u32 = 0xFFFFFFFF; // Channel [n] Software Request +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTSET +// register. +// +//***************************************************************************** +pub const UDMA_USEBURSTSET_SET_M: u32 = 0xFFFFFFFF; // Channel [n] Useburst Set +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTCLR +// register. +// +//***************************************************************************** +pub const UDMA_USEBURSTCLR_CLR_M: u32 = 0xFFFFFFFF; // Channel [n] Useburst Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKSET +// register. +// +//***************************************************************************** +pub const UDMA_REQMASKSET_SET_M: u32 = 0xFFFFFFFF; // Channel [n] Request Mask Set +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKCLR +// register. +// +//***************************************************************************** +pub const UDMA_REQMASKCLR_CLR_M: u32 = 0xFFFFFFFF; // Channel [n] Request Mask Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENASET register. +// +//***************************************************************************** +pub const UDMA_ENASET_SET_M: u32 = 0xFFFFFFFF; // Channel [n] Enable Set +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENACLR register. +// +//***************************************************************************** +pub const UDMA_ENACLR_CLR_M: u32 = 0xFFFFFFFF; // Clear Channel [n] Enable Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTSET register. +// +//***************************************************************************** +pub const UDMA_ALTSET_SET_M: u32 = 0xFFFFFFFF; // Channel [n] Alternate Set +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTCLR register. +// +//***************************************************************************** +pub const UDMA_ALTCLR_CLR_M: u32 = 0xFFFFFFFF; // Channel [n] Alternate Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOSET register. +// +//***************************************************************************** +pub const UDMA_PRIOSET_SET_M: u32 = 0xFFFFFFFF; // Channel [n] Priority Set +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOCLR register. +// +//***************************************************************************** +pub const UDMA_PRIOCLR_CLR_M: u32 = 0xFFFFFFFF; // Channel [n] Priority Clear +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ERRCLR register. +// +//***************************************************************************** +pub const UDMA_ERRCLR_ERRCLR: u32 = 0x00000001; // uDMA Bus Error Status +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHASGN register. +// +//***************************************************************************** +pub const UDMA_CHASGN_M: u32 = 0xFFFFFFFF; // Channel [n] Assignment Select +pub const UDMA_CHASGN_PRIMARY: u32 = 0x00000000; // Use the primary channel + // assignment +pub const UDMA_CHASGN_SECONDARY: u32 = 0x00000001; // Use the secondary channel + // assignment +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHIS register. +// +//***************************************************************************** +pub const UDMA_CHIS_M: u32 = 0xFFFFFFFF; // Channel [n] Interrupt Status +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP0 register. +// +//***************************************************************************** +pub const UDMA_CHMAP0_CH7SEL_M: u32 = 0xF0000000; // uDMA Channel 7 Source Select +pub const UDMA_CHMAP0_CH6SEL_M: u32 = 0x0F000000; // uDMA Channel 6 Source Select +pub const UDMA_CHMAP0_CH5SEL_M: u32 = 0x00F00000; // uDMA Channel 5 Source Select +pub const UDMA_CHMAP0_CH4SEL_M: u32 = 0x000F0000; // uDMA Channel 4 Source Select +pub const UDMA_CHMAP0_CH3SEL_M: u32 = 0x0000F000; // uDMA Channel 3 Source Select +pub const UDMA_CHMAP0_CH2SEL_M: u32 = 0x00000F00; // uDMA Channel 2 Source Select +pub const UDMA_CHMAP0_CH1SEL_M: u32 = 0x000000F0; // uDMA Channel 1 Source Select +pub const UDMA_CHMAP0_CH0SEL_M: u32 = 0x0000000F; // uDMA Channel 0 Source Select +pub const UDMA_CHMAP0_CH7SEL_S: u32 = 28; +pub const UDMA_CHMAP0_CH6SEL_S: u32 = 24; +pub const UDMA_CHMAP0_CH5SEL_S: u32 = 20; +pub const UDMA_CHMAP0_CH4SEL_S: u32 = 16; +pub const UDMA_CHMAP0_CH3SEL_S: u32 = 12; +pub const UDMA_CHMAP0_CH2SEL_S: u32 = 8; +pub const UDMA_CHMAP0_CH1SEL_S: u32 = 4; +pub const UDMA_CHMAP0_CH0SEL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP1 register. +// +//***************************************************************************** +pub const UDMA_CHMAP1_CH15SEL_M: u32 = 0xF0000000; // uDMA Channel 15 Source Select +pub const UDMA_CHMAP1_CH14SEL_M: u32 = 0x0F000000; // uDMA Channel 14 Source Select +pub const UDMA_CHMAP1_CH13SEL_M: u32 = 0x00F00000; // uDMA Channel 13 Source Select +pub const UDMA_CHMAP1_CH12SEL_M: u32 = 0x000F0000; // uDMA Channel 12 Source Select +pub const UDMA_CHMAP1_CH11SEL_M: u32 = 0x0000F000; // uDMA Channel 11 Source Select +pub const UDMA_CHMAP1_CH10SEL_M: u32 = 0x00000F00; // uDMA Channel 10 Source Select +pub const UDMA_CHMAP1_CH9SEL_M: u32 = 0x000000F0; // uDMA Channel 9 Source Select +pub const UDMA_CHMAP1_CH8SEL_M: u32 = 0x0000000F; // uDMA Channel 8 Source Select +pub const UDMA_CHMAP1_CH15SEL_S: u32 = 28; +pub const UDMA_CHMAP1_CH14SEL_S: u32 = 24; +pub const UDMA_CHMAP1_CH13SEL_S: u32 = 20; +pub const UDMA_CHMAP1_CH12SEL_S: u32 = 16; +pub const UDMA_CHMAP1_CH11SEL_S: u32 = 12; +pub const UDMA_CHMAP1_CH10SEL_S: u32 = 8; +pub const UDMA_CHMAP1_CH9SEL_S: u32 = 4; +pub const UDMA_CHMAP1_CH8SEL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP2 register. +// +//***************************************************************************** +pub const UDMA_CHMAP2_CH23SEL_M: u32 = 0xF0000000; // uDMA Channel 23 Source Select +pub const UDMA_CHMAP2_CH22SEL_M: u32 = 0x0F000000; // uDMA Channel 22 Source Select +pub const UDMA_CHMAP2_CH21SEL_M: u32 = 0x00F00000; // uDMA Channel 21 Source Select +pub const UDMA_CHMAP2_CH20SEL_M: u32 = 0x000F0000; // uDMA Channel 20 Source Select +pub const UDMA_CHMAP2_CH19SEL_M: u32 = 0x0000F000; // uDMA Channel 19 Source Select +pub const UDMA_CHMAP2_CH18SEL_M: u32 = 0x00000F00; // uDMA Channel 18 Source Select +pub const UDMA_CHMAP2_CH17SEL_M: u32 = 0x000000F0; // uDMA Channel 17 Source Select +pub const UDMA_CHMAP2_CH16SEL_M: u32 = 0x0000000F; // uDMA Channel 16 Source Select +pub const UDMA_CHMAP2_CH23SEL_S: u32 = 28; +pub const UDMA_CHMAP2_CH22SEL_S: u32 = 24; +pub const UDMA_CHMAP2_CH21SEL_S: u32 = 20; +pub const UDMA_CHMAP2_CH20SEL_S: u32 = 16; +pub const UDMA_CHMAP2_CH19SEL_S: u32 = 12; +pub const UDMA_CHMAP2_CH18SEL_S: u32 = 8; +pub const UDMA_CHMAP2_CH17SEL_S: u32 = 4; +pub const UDMA_CHMAP2_CH16SEL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP3 register. +// +//***************************************************************************** +pub const UDMA_CHMAP3_CH31SEL_M: u32 = 0xF0000000; // uDMA Channel 31 Source Select +pub const UDMA_CHMAP3_CH30SEL_M: u32 = 0x0F000000; // uDMA Channel 30 Source Select +pub const UDMA_CHMAP3_CH29SEL_M: u32 = 0x00F00000; // uDMA Channel 29 Source Select +pub const UDMA_CHMAP3_CH28SEL_M: u32 = 0x000F0000; // uDMA Channel 28 Source Select +pub const UDMA_CHMAP3_CH27SEL_M: u32 = 0x0000F000; // uDMA Channel 27 Source Select +pub const UDMA_CHMAP3_CH26SEL_M: u32 = 0x00000F00; // uDMA Channel 26 Source Select +pub const UDMA_CHMAP3_CH25SEL_M: u32 = 0x000000F0; // uDMA Channel 25 Source Select +pub const UDMA_CHMAP3_CH24SEL_M: u32 = 0x0000000F; // uDMA Channel 24 Source Select +pub const UDMA_CHMAP3_CH31SEL_S: u32 = 28; +pub const UDMA_CHMAP3_CH30SEL_S: u32 = 24; +pub const UDMA_CHMAP3_CH29SEL_S: u32 = 20; +pub const UDMA_CHMAP3_CH28SEL_S: u32 = 16; +pub const UDMA_CHMAP3_CH27SEL_S: u32 = 12; +pub const UDMA_CHMAP3_CH26SEL_S: u32 = 8; +pub const UDMA_CHMAP3_CH25SEL_S: u32 = 4; +pub const UDMA_CHMAP3_CH24SEL_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SRCENDP register. +// +//***************************************************************************** +pub const UDMA_SRCENDP_ADDR_M: u32 = 0xFFFFFFFF; // Source Address End Pointer +pub const UDMA_SRCENDP_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_DSTENDP register. +// +//***************************************************************************** +pub const UDMA_DSTENDP_ADDR_M: u32 = 0xFFFFFFFF; // Destination Address End Pointer +pub const UDMA_DSTENDP_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHCTL register. +// +//***************************************************************************** +pub const UDMA_CHCTL_DSTINC_M: u32 = 0xC0000000; // Destination Address Increment +pub const UDMA_CHCTL_DSTINC_8: u32 = 0x00000000; // Byte +pub const UDMA_CHCTL_DSTINC_16: u32 = 0x40000000; // Half-word +pub const UDMA_CHCTL_DSTINC_32: u32 = 0x80000000; // Word +pub const UDMA_CHCTL_DSTINC_NONE: u32 = 0xC0000000; // No increment +pub const UDMA_CHCTL_DSTSIZE_M: u32 = 0x30000000; // Destination Data Size +pub const UDMA_CHCTL_DSTSIZE_8: u32 = 0x00000000; // Byte +pub const UDMA_CHCTL_DSTSIZE_16: u32 = 0x10000000; // Half-word +pub const UDMA_CHCTL_DSTSIZE_32: u32 = 0x20000000; // Word +pub const UDMA_CHCTL_SRCINC_M: u32 = 0x0C000000; // Source Address Increment +pub const UDMA_CHCTL_SRCINC_8: u32 = 0x00000000; // Byte +pub const UDMA_CHCTL_SRCINC_16: u32 = 0x04000000; // Half-word +pub const UDMA_CHCTL_SRCINC_32: u32 = 0x08000000; // Word +pub const UDMA_CHCTL_SRCINC_NONE: u32 = 0x0C000000; // No increment +pub const UDMA_CHCTL_SRCSIZE_M: u32 = 0x03000000; // Source Data Size +pub const UDMA_CHCTL_SRCSIZE_8: u32 = 0x00000000; // Byte +pub const UDMA_CHCTL_SRCSIZE_16: u32 = 0x01000000; // Half-word +pub const UDMA_CHCTL_SRCSIZE_32: u32 = 0x02000000; // Word +pub const UDMA_CHCTL_ARBSIZE_M: u32 = 0x0003C000; // Arbitration Size +pub const UDMA_CHCTL_ARBSIZE_1: u32 = 0x00000000; // 1 Transfer +pub const UDMA_CHCTL_ARBSIZE_2: u32 = 0x00004000; // 2 Transfers +pub const UDMA_CHCTL_ARBSIZE_4: u32 = 0x00008000; // 4 Transfers +pub const UDMA_CHCTL_ARBSIZE_8: u32 = 0x0000C000; // 8 Transfers +pub const UDMA_CHCTL_ARBSIZE_16: u32 = 0x00010000; // 16 Transfers +pub const UDMA_CHCTL_ARBSIZE_32: u32 = 0x00014000; // 32 Transfers +pub const UDMA_CHCTL_ARBSIZE_64: u32 = 0x00018000; // 64 Transfers +pub const UDMA_CHCTL_ARBSIZE_128: u32 = 0x0001C000; // 128 Transfers +pub const UDMA_CHCTL_ARBSIZE_256: u32 = 0x00020000; // 256 Transfers +pub const UDMA_CHCTL_ARBSIZE_512: u32 = 0x00024000; // 512 Transfers +pub const UDMA_CHCTL_ARBSIZE_1024: u32 = 0x00028000; // 1024 Transfers +pub const UDMA_CHCTL_XFERSIZE_M: u32 = 0x00003FF0; // Transfer Size (minus 1) +pub const UDMA_CHCTL_NXTUSEBURST: u32 = 0x00000008; // Next Useburst +pub const UDMA_CHCTL_XFERMODE_M: u32 = 0x00000007; // uDMA Transfer Mode +pub const UDMA_CHCTL_XFERMODE_STOP: u32 = 0x00000000; // Stop +pub const UDMA_CHCTL_XFERMODE_BASIC: u32 = 0x00000001; // Basic +pub const UDMA_CHCTL_XFERMODE_AUTO: u32 = 0x00000002; // Auto-Request +pub const UDMA_CHCTL_XFERMODE_PINGPONG: u32 = 0x00000003; // Ping-Pong +pub const UDMA_CHCTL_XFERMODE_MEM_SG: u32 = 0x00000004; // Memory Scatter-Gather +pub const UDMA_CHCTL_XFERMODE_MEM_SGA: u32 = 0x00000005; // Alternate Memory Scatter-Gather +pub const UDMA_CHCTL_XFERMODE_PER_SG: u32 = 0x00000006; // Peripheral Scatter-Gather +pub const UDMA_CHCTL_XFERMODE_PER_SGA: u32 = 0x00000007; // Alternate Peripheral + // Scatter-Gather +pub const UDMA_CHCTL_XFERSIZE_S: u32 = 4; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +pub const NVIC_ACTLR_DISOOFP: u32 = 0x00000200; // Disable Out-Of-Order Floating + // Point +pub const NVIC_ACTLR_DISFPCA: u32 = 0x00000100; // Disable CONTROL +pub const NVIC_ACTLR_DISFOLD: u32 = 0x00000004; // Disable IT Folding +pub const NVIC_ACTLR_DISWBUF: u32 = 0x00000002; // Disable Write Buffer +pub const NVIC_ACTLR_DISMCYC: u32 = 0x00000001; // Disable Interrupts of Multiple + // Cycle Instructions +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +pub const NVIC_ST_CTRL_COUNT: u32 = 0x00010000; // Count Flag +pub const NVIC_ST_CTRL_CLK_SRC: u32 = 0x00000004; // Clock Source +pub const NVIC_ST_CTRL_INTEN: u32 = 0x00000002; // Interrupt Enable +pub const NVIC_ST_CTRL_ENABLE: u32 = 0x00000001; // Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +pub const NVIC_ST_RELOAD_M: u32 = 0x00FFFFFF; // Reload Value +pub const NVIC_ST_RELOAD_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +pub const NVIC_ST_CURRENT_M: u32 = 0x00FFFFFF; // Current Value +pub const NVIC_ST_CURRENT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +pub const NVIC_EN0_INT_M: u32 = 0xFFFFFFFF; // Interrupt Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +pub const NVIC_EN1_INT_M: u32 = 0xFFFFFFFF; // Interrupt Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +pub const NVIC_EN2_INT_M: u32 = 0xFFFFFFFF; // Interrupt Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +pub const NVIC_EN3_INT_M: u32 = 0xFFFFFFFF; // Interrupt Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +pub const NVIC_EN4_INT_M: u32 = 0x000007FF; // Interrupt Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +pub const NVIC_DIS0_INT_M: u32 = 0xFFFFFFFF; // Interrupt Disable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +pub const NVIC_DIS1_INT_M: u32 = 0xFFFFFFFF; // Interrupt Disable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +pub const NVIC_DIS2_INT_M: u32 = 0xFFFFFFFF; // Interrupt Disable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +pub const NVIC_DIS3_INT_M: u32 = 0xFFFFFFFF; // Interrupt Disable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +pub const NVIC_DIS4_INT_M: u32 = 0x000007FF; // Interrupt Disable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +pub const NVIC_PEND0_INT_M: u32 = 0xFFFFFFFF; // Interrupt Set Pending +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +pub const NVIC_PEND1_INT_M: u32 = 0xFFFFFFFF; // Interrupt Set Pending +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +pub const NVIC_PEND2_INT_M: u32 = 0xFFFFFFFF; // Interrupt Set Pending +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +pub const NVIC_PEND3_INT_M: u32 = 0xFFFFFFFF; // Interrupt Set Pending +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +pub const NVIC_PEND4_INT_M: u32 = 0x000007FF; // Interrupt Set Pending +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +pub const NVIC_UNPEND0_INT_M: u32 = 0xFFFFFFFF; // Interrupt Clear Pending +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +pub const NVIC_UNPEND1_INT_M: u32 = 0xFFFFFFFF; // Interrupt Clear Pending +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +pub const NVIC_UNPEND2_INT_M: u32 = 0xFFFFFFFF; // Interrupt Clear Pending +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +pub const NVIC_UNPEND3_INT_M: u32 = 0xFFFFFFFF; // Interrupt Clear Pending +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +pub const NVIC_UNPEND4_INT_M: u32 = 0x000007FF; // Interrupt Clear Pending +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +pub const NVIC_ACTIVE0_INT_M: u32 = 0xFFFFFFFF; // Interrupt Active +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +pub const NVIC_ACTIVE1_INT_M: u32 = 0xFFFFFFFF; // Interrupt Active +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +pub const NVIC_ACTIVE2_INT_M: u32 = 0xFFFFFFFF; // Interrupt Active +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +pub const NVIC_ACTIVE3_INT_M: u32 = 0xFFFFFFFF; // Interrupt Active +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +pub const NVIC_ACTIVE4_INT_M: u32 = 0x000007FF; // Interrupt Active +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +pub const NVIC_PRI0_INT3_M: u32 = 0xE0000000; // Interrupt 3 Priority Mask +pub const NVIC_PRI0_INT2_M: u32 = 0x00E00000; // Interrupt 2 Priority Mask +pub const NVIC_PRI0_INT1_M: u32 = 0x0000E000; // Interrupt 1 Priority Mask +pub const NVIC_PRI0_INT0_M: u32 = 0x000000E0; // Interrupt 0 Priority Mask +pub const NVIC_PRI0_INT3_S: u32 = 29; +pub const NVIC_PRI0_INT2_S: u32 = 21; +pub const NVIC_PRI0_INT1_S: u32 = 13; +pub const NVIC_PRI0_INT0_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +pub const NVIC_PRI1_INT7_M: u32 = 0xE0000000; // Interrupt 7 Priority Mask +pub const NVIC_PRI1_INT6_M: u32 = 0x00E00000; // Interrupt 6 Priority Mask +pub const NVIC_PRI1_INT5_M: u32 = 0x0000E000; // Interrupt 5 Priority Mask +pub const NVIC_PRI1_INT4_M: u32 = 0x000000E0; // Interrupt 4 Priority Mask +pub const NVIC_PRI1_INT7_S: u32 = 29; +pub const NVIC_PRI1_INT6_S: u32 = 21; +pub const NVIC_PRI1_INT5_S: u32 = 13; +pub const NVIC_PRI1_INT4_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +pub const NVIC_PRI2_INT11_M: u32 = 0xE0000000; // Interrupt 11 Priority Mask +pub const NVIC_PRI2_INT10_M: u32 = 0x00E00000; // Interrupt 10 Priority Mask +pub const NVIC_PRI2_INT9_M: u32 = 0x0000E000; // Interrupt 9 Priority Mask +pub const NVIC_PRI2_INT8_M: u32 = 0x000000E0; // Interrupt 8 Priority Mask +pub const NVIC_PRI2_INT11_S: u32 = 29; +pub const NVIC_PRI2_INT10_S: u32 = 21; +pub const NVIC_PRI2_INT9_S: u32 = 13; +pub const NVIC_PRI2_INT8_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +pub const NVIC_PRI3_INT15_M: u32 = 0xE0000000; // Interrupt 15 Priority Mask +pub const NVIC_PRI3_INT14_M: u32 = 0x00E00000; // Interrupt 14 Priority Mask +pub const NVIC_PRI3_INT13_M: u32 = 0x0000E000; // Interrupt 13 Priority Mask +pub const NVIC_PRI3_INT12_M: u32 = 0x000000E0; // Interrupt 12 Priority Mask +pub const NVIC_PRI3_INT15_S: u32 = 29; +pub const NVIC_PRI3_INT14_S: u32 = 21; +pub const NVIC_PRI3_INT13_S: u32 = 13; +pub const NVIC_PRI3_INT12_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +pub const NVIC_PRI4_INT19_M: u32 = 0xE0000000; // Interrupt 19 Priority Mask +pub const NVIC_PRI4_INT18_M: u32 = 0x00E00000; // Interrupt 18 Priority Mask +pub const NVIC_PRI4_INT17_M: u32 = 0x0000E000; // Interrupt 17 Priority Mask +pub const NVIC_PRI4_INT16_M: u32 = 0x000000E0; // Interrupt 16 Priority Mask +pub const NVIC_PRI4_INT19_S: u32 = 29; +pub const NVIC_PRI4_INT18_S: u32 = 21; +pub const NVIC_PRI4_INT17_S: u32 = 13; +pub const NVIC_PRI4_INT16_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +pub const NVIC_PRI5_INT23_M: u32 = 0xE0000000; // Interrupt 23 Priority Mask +pub const NVIC_PRI5_INT22_M: u32 = 0x00E00000; // Interrupt 22 Priority Mask +pub const NVIC_PRI5_INT21_M: u32 = 0x0000E000; // Interrupt 21 Priority Mask +pub const NVIC_PRI5_INT20_M: u32 = 0x000000E0; // Interrupt 20 Priority Mask +pub const NVIC_PRI5_INT23_S: u32 = 29; +pub const NVIC_PRI5_INT22_S: u32 = 21; +pub const NVIC_PRI5_INT21_S: u32 = 13; +pub const NVIC_PRI5_INT20_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +pub const NVIC_PRI6_INT27_M: u32 = 0xE0000000; // Interrupt 27 Priority Mask +pub const NVIC_PRI6_INT26_M: u32 = 0x00E00000; // Interrupt 26 Priority Mask +pub const NVIC_PRI6_INT25_M: u32 = 0x0000E000; // Interrupt 25 Priority Mask +pub const NVIC_PRI6_INT24_M: u32 = 0x000000E0; // Interrupt 24 Priority Mask +pub const NVIC_PRI6_INT27_S: u32 = 29; +pub const NVIC_PRI6_INT26_S: u32 = 21; +pub const NVIC_PRI6_INT25_S: u32 = 13; +pub const NVIC_PRI6_INT24_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +pub const NVIC_PRI7_INT31_M: u32 = 0xE0000000; // Interrupt 31 Priority Mask +pub const NVIC_PRI7_INT30_M: u32 = 0x00E00000; // Interrupt 30 Priority Mask +pub const NVIC_PRI7_INT29_M: u32 = 0x0000E000; // Interrupt 29 Priority Mask +pub const NVIC_PRI7_INT28_M: u32 = 0x000000E0; // Interrupt 28 Priority Mask +pub const NVIC_PRI7_INT31_S: u32 = 29; +pub const NVIC_PRI7_INT30_S: u32 = 21; +pub const NVIC_PRI7_INT29_S: u32 = 13; +pub const NVIC_PRI7_INT28_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +pub const NVIC_PRI8_INT35_M: u32 = 0xE0000000; // Interrupt 35 Priority Mask +pub const NVIC_PRI8_INT34_M: u32 = 0x00E00000; // Interrupt 34 Priority Mask +pub const NVIC_PRI8_INT33_M: u32 = 0x0000E000; // Interrupt 33 Priority Mask +pub const NVIC_PRI8_INT32_M: u32 = 0x000000E0; // Interrupt 32 Priority Mask +pub const NVIC_PRI8_INT35_S: u32 = 29; +pub const NVIC_PRI8_INT34_S: u32 = 21; +pub const NVIC_PRI8_INT33_S: u32 = 13; +pub const NVIC_PRI8_INT32_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +pub const NVIC_PRI9_INT39_M: u32 = 0xE0000000; // Interrupt 39 Priority Mask +pub const NVIC_PRI9_INT38_M: u32 = 0x00E00000; // Interrupt 38 Priority Mask +pub const NVIC_PRI9_INT37_M: u32 = 0x0000E000; // Interrupt 37 Priority Mask +pub const NVIC_PRI9_INT36_M: u32 = 0x000000E0; // Interrupt 36 Priority Mask +pub const NVIC_PRI9_INT39_S: u32 = 29; +pub const NVIC_PRI9_INT38_S: u32 = 21; +pub const NVIC_PRI9_INT37_S: u32 = 13; +pub const NVIC_PRI9_INT36_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +pub const NVIC_PRI10_INT43_M: u32 = 0xE0000000; // Interrupt 43 Priority Mask +pub const NVIC_PRI10_INT42_M: u32 = 0x00E00000; // Interrupt 42 Priority Mask +pub const NVIC_PRI10_INT41_M: u32 = 0x0000E000; // Interrupt 41 Priority Mask +pub const NVIC_PRI10_INT40_M: u32 = 0x000000E0; // Interrupt 40 Priority Mask +pub const NVIC_PRI10_INT43_S: u32 = 29; +pub const NVIC_PRI10_INT42_S: u32 = 21; +pub const NVIC_PRI10_INT41_S: u32 = 13; +pub const NVIC_PRI10_INT40_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +pub const NVIC_PRI11_INT47_M: u32 = 0xE0000000; // Interrupt 47 Priority Mask +pub const NVIC_PRI11_INT46_M: u32 = 0x00E00000; // Interrupt 46 Priority Mask +pub const NVIC_PRI11_INT45_M: u32 = 0x0000E000; // Interrupt 45 Priority Mask +pub const NVIC_PRI11_INT44_M: u32 = 0x000000E0; // Interrupt 44 Priority Mask +pub const NVIC_PRI11_INT47_S: u32 = 29; +pub const NVIC_PRI11_INT46_S: u32 = 21; +pub const NVIC_PRI11_INT45_S: u32 = 13; +pub const NVIC_PRI11_INT44_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +pub const NVIC_PRI12_INT51_M: u32 = 0xE0000000; // Interrupt 51 Priority Mask +pub const NVIC_PRI12_INT50_M: u32 = 0x00E00000; // Interrupt 50 Priority Mask +pub const NVIC_PRI12_INT49_M: u32 = 0x0000E000; // Interrupt 49 Priority Mask +pub const NVIC_PRI12_INT48_M: u32 = 0x000000E0; // Interrupt 48 Priority Mask +pub const NVIC_PRI12_INT51_S: u32 = 29; +pub const NVIC_PRI12_INT50_S: u32 = 21; +pub const NVIC_PRI12_INT49_S: u32 = 13; +pub const NVIC_PRI12_INT48_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +pub const NVIC_PRI13_INT55_M: u32 = 0xE0000000; // Interrupt 55 Priority Mask +pub const NVIC_PRI13_INT54_M: u32 = 0x00E00000; // Interrupt 54 Priority Mask +pub const NVIC_PRI13_INT53_M: u32 = 0x0000E000; // Interrupt 53 Priority Mask +pub const NVIC_PRI13_INT52_M: u32 = 0x000000E0; // Interrupt 52 Priority Mask +pub const NVIC_PRI13_INT55_S: u32 = 29; +pub const NVIC_PRI13_INT54_S: u32 = 21; +pub const NVIC_PRI13_INT53_S: u32 = 13; +pub const NVIC_PRI13_INT52_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +pub const NVIC_PRI14_INTD_M: u32 = 0xE0000000; // Interrupt 59 Priority Mask +pub const NVIC_PRI14_INTC_M: u32 = 0x00E00000; // Interrupt 58 Priority Mask +pub const NVIC_PRI14_INTB_M: u32 = 0x0000E000; // Interrupt 57 Priority Mask +pub const NVIC_PRI14_INTA_M: u32 = 0x000000E0; // Interrupt 56 Priority Mask +pub const NVIC_PRI14_INTD_S: u32 = 29; +pub const NVIC_PRI14_INTC_S: u32 = 21; +pub const NVIC_PRI14_INTB_S: u32 = 13; +pub const NVIC_PRI14_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +pub const NVIC_PRI15_INTD_M: u32 = 0xE0000000; // Interrupt 63 Priority Mask +pub const NVIC_PRI15_INTC_M: u32 = 0x00E00000; // Interrupt 62 Priority Mask +pub const NVIC_PRI15_INTB_M: u32 = 0x0000E000; // Interrupt 61 Priority Mask +pub const NVIC_PRI15_INTA_M: u32 = 0x000000E0; // Interrupt 60 Priority Mask +pub const NVIC_PRI15_INTD_S: u32 = 29; +pub const NVIC_PRI15_INTC_S: u32 = 21; +pub const NVIC_PRI15_INTB_S: u32 = 13; +pub const NVIC_PRI15_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +pub const NVIC_PRI16_INTD_M: u32 = 0xE0000000; // Interrupt 67 Priority Mask +pub const NVIC_PRI16_INTC_M: u32 = 0x00E00000; // Interrupt 66 Priority Mask +pub const NVIC_PRI16_INTB_M: u32 = 0x0000E000; // Interrupt 65 Priority Mask +pub const NVIC_PRI16_INTA_M: u32 = 0x000000E0; // Interrupt 64 Priority Mask +pub const NVIC_PRI16_INTD_S: u32 = 29; +pub const NVIC_PRI16_INTC_S: u32 = 21; +pub const NVIC_PRI16_INTB_S: u32 = 13; +pub const NVIC_PRI16_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +pub const NVIC_PRI17_INTD_M: u32 = 0xE0000000; // Interrupt 71 Priority Mask +pub const NVIC_PRI17_INTC_M: u32 = 0x00E00000; // Interrupt 70 Priority Mask +pub const NVIC_PRI17_INTB_M: u32 = 0x0000E000; // Interrupt 69 Priority Mask +pub const NVIC_PRI17_INTA_M: u32 = 0x000000E0; // Interrupt 68 Priority Mask +pub const NVIC_PRI17_INTD_S: u32 = 29; +pub const NVIC_PRI17_INTC_S: u32 = 21; +pub const NVIC_PRI17_INTB_S: u32 = 13; +pub const NVIC_PRI17_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +pub const NVIC_PRI18_INTD_M: u32 = 0xE0000000; // Interrupt 75 Priority Mask +pub const NVIC_PRI18_INTC_M: u32 = 0x00E00000; // Interrupt 74 Priority Mask +pub const NVIC_PRI18_INTB_M: u32 = 0x0000E000; // Interrupt 73 Priority Mask +pub const NVIC_PRI18_INTA_M: u32 = 0x000000E0; // Interrupt 72 Priority Mask +pub const NVIC_PRI18_INTD_S: u32 = 29; +pub const NVIC_PRI18_INTC_S: u32 = 21; +pub const NVIC_PRI18_INTB_S: u32 = 13; +pub const NVIC_PRI18_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +pub const NVIC_PRI19_INTD_M: u32 = 0xE0000000; // Interrupt 79 Priority Mask +pub const NVIC_PRI19_INTC_M: u32 = 0x00E00000; // Interrupt 78 Priority Mask +pub const NVIC_PRI19_INTB_M: u32 = 0x0000E000; // Interrupt 77 Priority Mask +pub const NVIC_PRI19_INTA_M: u32 = 0x000000E0; // Interrupt 76 Priority Mask +pub const NVIC_PRI19_INTD_S: u32 = 29; +pub const NVIC_PRI19_INTC_S: u32 = 21; +pub const NVIC_PRI19_INTB_S: u32 = 13; +pub const NVIC_PRI19_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +pub const NVIC_PRI20_INTD_M: u32 = 0xE0000000; // Interrupt 83 Priority Mask +pub const NVIC_PRI20_INTC_M: u32 = 0x00E00000; // Interrupt 82 Priority Mask +pub const NVIC_PRI20_INTB_M: u32 = 0x0000E000; // Interrupt 81 Priority Mask +pub const NVIC_PRI20_INTA_M: u32 = 0x000000E0; // Interrupt 80 Priority Mask +pub const NVIC_PRI20_INTD_S: u32 = 29; +pub const NVIC_PRI20_INTC_S: u32 = 21; +pub const NVIC_PRI20_INTB_S: u32 = 13; +pub const NVIC_PRI20_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +pub const NVIC_PRI21_INTD_M: u32 = 0xE0000000; // Interrupt 87 Priority Mask +pub const NVIC_PRI21_INTC_M: u32 = 0x00E00000; // Interrupt 86 Priority Mask +pub const NVIC_PRI21_INTB_M: u32 = 0x0000E000; // Interrupt 85 Priority Mask +pub const NVIC_PRI21_INTA_M: u32 = 0x000000E0; // Interrupt 84 Priority Mask +pub const NVIC_PRI21_INTD_S: u32 = 29; +pub const NVIC_PRI21_INTC_S: u32 = 21; +pub const NVIC_PRI21_INTB_S: u32 = 13; +pub const NVIC_PRI21_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +pub const NVIC_PRI22_INTD_M: u32 = 0xE0000000; // Interrupt 91 Priority Mask +pub const NVIC_PRI22_INTC_M: u32 = 0x00E00000; // Interrupt 90 Priority Mask +pub const NVIC_PRI22_INTB_M: u32 = 0x0000E000; // Interrupt 89 Priority Mask +pub const NVIC_PRI22_INTA_M: u32 = 0x000000E0; // Interrupt 88 Priority Mask +pub const NVIC_PRI22_INTD_S: u32 = 29; +pub const NVIC_PRI22_INTC_S: u32 = 21; +pub const NVIC_PRI22_INTB_S: u32 = 13; +pub const NVIC_PRI22_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +pub const NVIC_PRI23_INTD_M: u32 = 0xE0000000; // Interrupt 95 Priority Mask +pub const NVIC_PRI23_INTC_M: u32 = 0x00E00000; // Interrupt 94 Priority Mask +pub const NVIC_PRI23_INTB_M: u32 = 0x0000E000; // Interrupt 93 Priority Mask +pub const NVIC_PRI23_INTA_M: u32 = 0x000000E0; // Interrupt 92 Priority Mask +pub const NVIC_PRI23_INTD_S: u32 = 29; +pub const NVIC_PRI23_INTC_S: u32 = 21; +pub const NVIC_PRI23_INTB_S: u32 = 13; +pub const NVIC_PRI23_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +pub const NVIC_PRI24_INTD_M: u32 = 0xE0000000; // Interrupt 99 Priority Mask +pub const NVIC_PRI24_INTC_M: u32 = 0x00E00000; // Interrupt 98 Priority Mask +pub const NVIC_PRI24_INTB_M: u32 = 0x0000E000; // Interrupt 97 Priority Mask +pub const NVIC_PRI24_INTA_M: u32 = 0x000000E0; // Interrupt 96 Priority Mask +pub const NVIC_PRI24_INTD_S: u32 = 29; +pub const NVIC_PRI24_INTC_S: u32 = 21; +pub const NVIC_PRI24_INTB_S: u32 = 13; +pub const NVIC_PRI24_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +pub const NVIC_PRI25_INTD_M: u32 = 0xE0000000; // Interrupt 103 Priority Mask +pub const NVIC_PRI25_INTC_M: u32 = 0x00E00000; // Interrupt 102 Priority Mask +pub const NVIC_PRI25_INTB_M: u32 = 0x0000E000; // Interrupt 101 Priority Mask +pub const NVIC_PRI25_INTA_M: u32 = 0x000000E0; // Interrupt 100 Priority Mask +pub const NVIC_PRI25_INTD_S: u32 = 29; +pub const NVIC_PRI25_INTC_S: u32 = 21; +pub const NVIC_PRI25_INTB_S: u32 = 13; +pub const NVIC_PRI25_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +pub const NVIC_PRI26_INTD_M: u32 = 0xE0000000; // Interrupt 107 Priority Mask +pub const NVIC_PRI26_INTC_M: u32 = 0x00E00000; // Interrupt 106 Priority Mask +pub const NVIC_PRI26_INTB_M: u32 = 0x0000E000; // Interrupt 105 Priority Mask +pub const NVIC_PRI26_INTA_M: u32 = 0x000000E0; // Interrupt 104 Priority Mask +pub const NVIC_PRI26_INTD_S: u32 = 29; +pub const NVIC_PRI26_INTC_S: u32 = 21; +pub const NVIC_PRI26_INTB_S: u32 = 13; +pub const NVIC_PRI26_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +pub const NVIC_PRI27_INTD_M: u32 = 0xE0000000; // Interrupt 111 Priority Mask +pub const NVIC_PRI27_INTC_M: u32 = 0x00E00000; // Interrupt 110 Priority Mask +pub const NVIC_PRI27_INTB_M: u32 = 0x0000E000; // Interrupt 109 Priority Mask +pub const NVIC_PRI27_INTA_M: u32 = 0x000000E0; // Interrupt 108 Priority Mask +pub const NVIC_PRI27_INTD_S: u32 = 29; +pub const NVIC_PRI27_INTC_S: u32 = 21; +pub const NVIC_PRI27_INTB_S: u32 = 13; +pub const NVIC_PRI27_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +pub const NVIC_PRI28_INTD_M: u32 = 0xE0000000; // Interrupt 115 Priority Mask +pub const NVIC_PRI28_INTC_M: u32 = 0x00E00000; // Interrupt 114 Priority Mask +pub const NVIC_PRI28_INTB_M: u32 = 0x0000E000; // Interrupt 113 Priority Mask +pub const NVIC_PRI28_INTA_M: u32 = 0x000000E0; // Interrupt 112 Priority Mask +pub const NVIC_PRI28_INTD_S: u32 = 29; +pub const NVIC_PRI28_INTC_S: u32 = 21; +pub const NVIC_PRI28_INTB_S: u32 = 13; +pub const NVIC_PRI28_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +pub const NVIC_PRI29_INTD_M: u32 = 0xE0000000; // Interrupt 119 Priority Mask +pub const NVIC_PRI29_INTC_M: u32 = 0x00E00000; // Interrupt 118 Priority Mask +pub const NVIC_PRI29_INTB_M: u32 = 0x0000E000; // Interrupt 117 Priority Mask +pub const NVIC_PRI29_INTA_M: u32 = 0x000000E0; // Interrupt 116 Priority Mask +pub const NVIC_PRI29_INTD_S: u32 = 29; +pub const NVIC_PRI29_INTC_S: u32 = 21; +pub const NVIC_PRI29_INTB_S: u32 = 13; +pub const NVIC_PRI29_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +pub const NVIC_PRI30_INTD_M: u32 = 0xE0000000; // Interrupt 123 Priority Mask +pub const NVIC_PRI30_INTC_M: u32 = 0x00E00000; // Interrupt 122 Priority Mask +pub const NVIC_PRI30_INTB_M: u32 = 0x0000E000; // Interrupt 121 Priority Mask +pub const NVIC_PRI30_INTA_M: u32 = 0x000000E0; // Interrupt 120 Priority Mask +pub const NVIC_PRI30_INTD_S: u32 = 29; +pub const NVIC_PRI30_INTC_S: u32 = 21; +pub const NVIC_PRI30_INTB_S: u32 = 13; +pub const NVIC_PRI30_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +pub const NVIC_PRI31_INTD_M: u32 = 0xE0000000; // Interrupt 127 Priority Mask +pub const NVIC_PRI31_INTC_M: u32 = 0x00E00000; // Interrupt 126 Priority Mask +pub const NVIC_PRI31_INTB_M: u32 = 0x0000E000; // Interrupt 125 Priority Mask +pub const NVIC_PRI31_INTA_M: u32 = 0x000000E0; // Interrupt 124 Priority Mask +pub const NVIC_PRI31_INTD_S: u32 = 29; +pub const NVIC_PRI31_INTC_S: u32 = 21; +pub const NVIC_PRI31_INTB_S: u32 = 13; +pub const NVIC_PRI31_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +pub const NVIC_PRI32_INTD_M: u32 = 0xE0000000; // Interrupt 131 Priority Mask +pub const NVIC_PRI32_INTC_M: u32 = 0x00E00000; // Interrupt 130 Priority Mask +pub const NVIC_PRI32_INTB_M: u32 = 0x0000E000; // Interrupt 129 Priority Mask +pub const NVIC_PRI32_INTA_M: u32 = 0x000000E0; // Interrupt 128 Priority Mask +pub const NVIC_PRI32_INTD_S: u32 = 29; +pub const NVIC_PRI32_INTC_S: u32 = 21; +pub const NVIC_PRI32_INTB_S: u32 = 13; +pub const NVIC_PRI32_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI33 register. +// +//***************************************************************************** +pub const NVIC_PRI33_INTD_M: u32 = 0xE0000000; // Interrupt Priority for Interrupt + // [4n+3] +pub const NVIC_PRI33_INTC_M: u32 = 0x00E00000; // Interrupt Priority for Interrupt + // [4n+2] +pub const NVIC_PRI33_INTB_M: u32 = 0x0000E000; // Interrupt Priority for Interrupt + // [4n+1] +pub const NVIC_PRI33_INTA_M: u32 = 0x000000E0; // Interrupt Priority for Interrupt + // [4n] +pub const NVIC_PRI33_INTD_S: u32 = 29; +pub const NVIC_PRI33_INTC_S: u32 = 21; +pub const NVIC_PRI33_INTB_S: u32 = 13; +pub const NVIC_PRI33_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI34 register. +// +//***************************************************************************** +pub const NVIC_PRI34_INTD_M: u32 = 0xE0000000; // Interrupt Priority for Interrupt + // [4n+3] +pub const NVIC_PRI34_INTC_M: u32 = 0x00E00000; // Interrupt Priority for Interrupt + // [4n+2] +pub const NVIC_PRI34_INTB_M: u32 = 0x0000E000; // Interrupt Priority for Interrupt + // [4n+1] +pub const NVIC_PRI34_INTA_M: u32 = 0x000000E0; // Interrupt Priority for Interrupt + // [4n] +pub const NVIC_PRI34_INTD_S: u32 = 29; +pub const NVIC_PRI34_INTC_S: u32 = 21; +pub const NVIC_PRI34_INTB_S: u32 = 13; +pub const NVIC_PRI34_INTA_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +pub const NVIC_CPUID_IMP_M: u32 = 0xFF000000; // Implementer Code +pub const NVIC_CPUID_IMP_ARM: u32 = 0x41000000; // ARM +pub const NVIC_CPUID_VAR_M: u32 = 0x00F00000; // Variant Number +pub const NVIC_CPUID_CON_M: u32 = 0x000F0000; // pub constant +pub const NVIC_CPUID_PARTNO_M: u32 = 0x0000FFF0; // Part Number +pub const NVIC_CPUID_PARTNO_CM4: u32 = 0x0000C240; // Cortex-M4 processor +pub const NVIC_CPUID_REV_M: u32 = 0x0000000F; // Revision Number +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +pub const NVIC_INT_CTRL_NMI_SET: u32 = 0x80000000; // NMI Set Pending +pub const NVIC_INT_CTRL_PEND_SV: u32 = 0x10000000; // PendSV Set Pending +pub const NVIC_INT_CTRL_UNPEND_SV: u32 = 0x08000000; // PendSV Clear Pending +pub const NVIC_INT_CTRL_PENDSTSET: u32 = 0x04000000; // SysTick Set Pending +pub const NVIC_INT_CTRL_PENDSTCLR: u32 = 0x02000000; // SysTick Clear Pending +pub const NVIC_INT_CTRL_ISR_PRE: u32 = 0x00800000; // Debug Interrupt Handling +pub const NVIC_INT_CTRL_ISR_PEND: u32 = 0x00400000; // Interrupt Pending +pub const NVIC_INT_CTRL_VEC_PEN_M: u32 = 0x000FF000; // Interrupt Pending Vector Number +pub const NVIC_INT_CTRL_VEC_PEN_NMI: u32 = 0x00002000; // NMI +pub const NVIC_INT_CTRL_VEC_PEN_HARD: u32 = 0x00003000; // Hard fault +pub const NVIC_INT_CTRL_VEC_PEN_MEM: u32 = 0x00004000; // Memory management fault +pub const NVIC_INT_CTRL_VEC_PEN_BUS: u32 = 0x00005000; // Bus fault +pub const NVIC_INT_CTRL_VEC_PEN_USG: u32 = 0x00006000; // Usage fault +pub const NVIC_INT_CTRL_VEC_PEN_SVC: u32 = 0x0000B000; // SVCall +pub const NVIC_INT_CTRL_VEC_PEN_PNDSV: u32 = 0x0000E000; // PendSV +pub const NVIC_INT_CTRL_VEC_PEN_TICK: u32 = 0x0000F000; // SysTick +pub const NVIC_INT_CTRL_RET_BASE: u32 = 0x00000800; // Return to Base +pub const NVIC_INT_CTRL_VEC_ACT_M: u32 = 0x000000FF; // Interrupt Pending Vector Number +pub const NVIC_INT_CTRL_VEC_ACT_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +pub const NVIC_VTABLE_OFFSET_M: u32 = 0xFFFFFC00; // Vector Table Offset +pub const NVIC_VTABLE_OFFSET_S: u32 = 10; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +pub const NVIC_APINT_VECTKEY_M: u32 = 0xFFFF0000; // Register Key +pub const NVIC_APINT_VECTKEY: u32 = 0x05FA0000; // Vector key +pub const NVIC_APINT_ENDIANESS: u32 = 0x00008000; // Data Endianess +pub const NVIC_APINT_PRIGROUP_M: u32 = 0x00000700; // Interrupt Priority Grouping +pub const NVIC_APINT_PRIGROUP_7_1: u32 = 0x00000000; // Priority group 7.1 split +pub const NVIC_APINT_PRIGROUP_6_2: u32 = 0x00000100; // Priority group 6.2 split +pub const NVIC_APINT_PRIGROUP_5_3: u32 = 0x00000200; // Priority group 5.3 split +pub const NVIC_APINT_PRIGROUP_4_4: u32 = 0x00000300; // Priority group 4.4 split +pub const NVIC_APINT_PRIGROUP_3_5: u32 = 0x00000400; // Priority group 3.5 split +pub const NVIC_APINT_PRIGROUP_2_6: u32 = 0x00000500; // Priority group 2.6 split +pub const NVIC_APINT_PRIGROUP_1_7: u32 = 0x00000600; // Priority group 1.7 split +pub const NVIC_APINT_PRIGROUP_0_8: u32 = 0x00000700; // Priority group 0.8 split +pub const NVIC_APINT_SYSRESETREQ: u32 = 0x00000004; // System Reset Request +pub const NVIC_APINT_VECT_CLR_ACT: u32 = 0x00000002; // Clear Active NMI / Fault +pub const NVIC_APINT_VECT_RESET: u32 = 0x00000001; // System Reset +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +pub const NVIC_SYS_CTRL_SEVONPEND: u32 = 0x00000010; // Wake Up on Pending +pub const NVIC_SYS_CTRL_SLEEPDEEP: u32 = 0x00000004; // Deep Sleep Enable +pub const NVIC_SYS_CTRL_SLEEPEXIT: u32 = 0x00000002; // Sleep on ISR Exit +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +pub const NVIC_CFG_CTRL_STKALIGN: u32 = 0x00000200; // Stack Alignment on Exception + // Entry +pub const NVIC_CFG_CTRL_BFHFNMIGN: u32 = 0x00000100; // Ignore Bus Fault in NMI and + // Fault +pub const NVIC_CFG_CTRL_DIV0: u32 = 0x00000010; // Trap on Divide by 0 +pub const NVIC_CFG_CTRL_UNALIGNED: u32 = 0x00000008; // Trap on Unaligned Access +pub const NVIC_CFG_CTRL_MAIN_PEND: u32 = 0x00000002; // Allow Main Interrupt Trigger +pub const NVIC_CFG_CTRL_BASE_THR: u32 = 0x00000001; // Thread State Control +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +pub const NVIC_SYS_PRI1_USAGE_M: u32 = 0x00E00000; // Usage Fault Priority +pub const NVIC_SYS_PRI1_BUS_M: u32 = 0x0000E000; // Bus Fault Priority +pub const NVIC_SYS_PRI1_MEM_M: u32 = 0x000000E0; // Memory Management Fault Priority +pub const NVIC_SYS_PRI1_USAGE_S: u32 = 21; +pub const NVIC_SYS_PRI1_BUS_S: u32 = 13; +pub const NVIC_SYS_PRI1_MEM_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +pub const NVIC_SYS_PRI2_SVC_M: u32 = 0xE0000000; // SVCall Priority +pub const NVIC_SYS_PRI2_SVC_S: u32 = 29; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +pub const NVIC_SYS_PRI3_TICK_M: u32 = 0xE0000000; // SysTick Exception Priority +pub const NVIC_SYS_PRI3_PENDSV_M: u32 = 0x00E00000; // PendSV Priority +pub const NVIC_SYS_PRI3_DEBUG_M: u32 = 0x000000E0; // Debug Priority +pub const NVIC_SYS_PRI3_TICK_S: u32 = 29; +pub const NVIC_SYS_PRI3_PENDSV_S: u32 = 21; +pub const NVIC_SYS_PRI3_DEBUG_S: u32 = 5; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +pub const NVIC_SYS_HND_CTRL_USAGE: u32 = 0x00040000; // Usage Fault Enable +pub const NVIC_SYS_HND_CTRL_BUS: u32 = 0x00020000; // Bus Fault Enable +pub const NVIC_SYS_HND_CTRL_MEM: u32 = 0x00010000; // Memory Management Fault Enable +pub const NVIC_SYS_HND_CTRL_SVC: u32 = 0x00008000; // SVC Call Pending +pub const NVIC_SYS_HND_CTRL_BUSP: u32 = 0x00004000; // Bus Fault Pending +pub const NVIC_SYS_HND_CTRL_MEMP: u32 = 0x00002000; // Memory Management Fault Pending +pub const NVIC_SYS_HND_CTRL_USAGEP: u32 = 0x00001000; // Usage Fault Pending +pub const NVIC_SYS_HND_CTRL_TICK: u32 = 0x00000800; // SysTick Exception Active +pub const NVIC_SYS_HND_CTRL_PNDSV: u32 = 0x00000400; // PendSV Exception Active +pub const NVIC_SYS_HND_CTRL_MON: u32 = 0x00000100; // Debug Monitor Active +pub const NVIC_SYS_HND_CTRL_SVCA: u32 = 0x00000080; // SVC Call Active +pub const NVIC_SYS_HND_CTRL_USGA: u32 = 0x00000008; // Usage Fault Active +pub const NVIC_SYS_HND_CTRL_BUSA: u32 = 0x00000002; // Bus Fault Active +pub const NVIC_SYS_HND_CTRL_MEMA: u32 = 0x00000001; // Memory Management Fault Active +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +pub const NVIC_FAULT_STAT_DIV0: u32 = 0x02000000; // Divide-by-Zero Usage Fault +pub const NVIC_FAULT_STAT_UNALIGN: u32 = 0x01000000; // Unaligned Access Usage Fault +pub const NVIC_FAULT_STAT_NOCP: u32 = 0x00080000; // No Coprocessor Usage Fault +pub const NVIC_FAULT_STAT_INVPC: u32 = 0x00040000; // Invalid PC Load Usage Fault +pub const NVIC_FAULT_STAT_INVSTAT: u32 = 0x00020000; // Invalid State Usage Fault +pub const NVIC_FAULT_STAT_UNDEF: u32 = 0x00010000; // Undefined Instruction Usage + // Fault +pub const NVIC_FAULT_STAT_BFARV: u32 = 0x00008000; // Bus Fault Address Register Valid +pub const NVIC_FAULT_STAT_BLSPERR: u32 = 0x00002000; // Bus Fault on Floating-Point Lazy + // State Preservation +pub const NVIC_FAULT_STAT_BSTKE: u32 = 0x00001000; // Stack Bus Fault +pub const NVIC_FAULT_STAT_BUSTKE: u32 = 0x00000800; // Unstack Bus Fault +pub const NVIC_FAULT_STAT_IMPRE: u32 = 0x00000400; // Imprecise Data Bus Error +pub const NVIC_FAULT_STAT_PRECISE: u32 = 0x00000200; // Precise Data Bus Error +pub const NVIC_FAULT_STAT_IBUS: u32 = 0x00000100; // Instruction Bus Error +pub const NVIC_FAULT_STAT_MMARV: u32 = 0x00000080; // Memory Management Fault Address + // Register Valid +pub const NVIC_FAULT_STAT_MLSPERR: u32 = 0x00000020; // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +pub const NVIC_FAULT_STAT_MSTKE: u32 = 0x00000010; // Stack Access Violation +pub const NVIC_FAULT_STAT_MUSTKE: u32 = 0x00000008; // Unstack Access Violation +pub const NVIC_FAULT_STAT_DERR: u32 = 0x00000002; // Data Access Violation +pub const NVIC_FAULT_STAT_IERR: u32 = 0x00000001; // Instruction Access Violation +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +pub const NVIC_HFAULT_STAT_DBG: u32 = 0x80000000; // Debug Event +pub const NVIC_HFAULT_STAT_FORCED: u32 = 0x40000000; // Forced Hard Fault +pub const NVIC_HFAULT_STAT_VECT: u32 = 0x00000002; // Vector Table Read Fault +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +pub const NVIC_DEBUG_STAT_EXTRNL: u32 = 0x00000010; // EDBGRQ asserted +pub const NVIC_DEBUG_STAT_VCATCH: u32 = 0x00000008; // Vector catch +pub const NVIC_DEBUG_STAT_DWTTRAP: u32 = 0x00000004; // DWT match +pub const NVIC_DEBUG_STAT_BKPT: u32 = 0x00000002; // Breakpoint instruction +pub const NVIC_DEBUG_STAT_HALTED: u32 = 0x00000001; // Halt request +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +pub const NVIC_MM_ADDR_M: u32 = 0xFFFFFFFF; // Fault Address +pub const NVIC_MM_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +pub const NVIC_FAULT_ADDR_M: u32 = 0xFFFFFFFF; // Fault Address +pub const NVIC_FAULT_ADDR_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPAC register. +// +//***************************************************************************** +pub const NVIC_CPAC_CP11_M: u32 = 0x00C00000; // CP11 Coprocessor Access + // Privilege +pub const NVIC_CPAC_CP11_DIS: u32 = 0x00000000; // Access Denied +pub const NVIC_CPAC_CP11_PRIV: u32 = 0x00400000; // Privileged Access Only +pub const NVIC_CPAC_CP11_FULL: u32 = 0x00C00000; // Full Access +pub const NVIC_CPAC_CP10_M: u32 = 0x00300000; // CP10 Coprocessor Access + // Privilege +pub const NVIC_CPAC_CP10_DIS: u32 = 0x00000000; // Access Denied +pub const NVIC_CPAC_CP10_PRIV: u32 = 0x00100000; // Privileged Access Only +pub const NVIC_CPAC_CP10_FULL: u32 = 0x00300000; // Full Access +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +pub const NVIC_MPU_TYPE_IREGION_M: u32 = 0x00FF0000; // Number of I Regions +pub const NVIC_MPU_TYPE_DREGION_M: u32 = 0x0000FF00; // Number of D Regions +pub const NVIC_MPU_TYPE_SEPARATE: u32 = 0x00000001; // Separate or Unified MPU +pub const NVIC_MPU_TYPE_IREGION_S: u32 = 16; +pub const NVIC_MPU_TYPE_DREGION_S: u32 = 8; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +pub const NVIC_MPU_CTRL_PRIVDEFEN: u32 = 0x00000004; // MPU Default Region +pub const NVIC_MPU_CTRL_HFNMIENA: u32 = 0x00000002; // MPU Enabled During Faults +pub const NVIC_MPU_CTRL_ENABLE: u32 = 0x00000001; // MPU Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +pub const NVIC_MPU_NUMBER_M: u32 = 0x00000007; // MPU Region to Access +pub const NVIC_MPU_NUMBER_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +pub const NVIC_MPU_BASE_ADDR_M: u32 = 0xFFFFFFE0; // Base Address Mask +pub const NVIC_MPU_BASE_VALID: u32 = 0x00000010; // Region Number Valid +pub const NVIC_MPU_BASE_REGION_M: u32 = 0x00000007; // Region Number +pub const NVIC_MPU_BASE_ADDR_S: u32 = 5; +pub const NVIC_MPU_BASE_REGION_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +pub const NVIC_MPU_ATTR_XN: u32 = 0x10000000; // Instruction Access Disable +pub const NVIC_MPU_ATTR_AP_M: u32 = 0x07000000; // Access Privilege +pub const NVIC_MPU_ATTR_TEX_M: u32 = 0x00380000; // Type Extension Mask +pub const NVIC_MPU_ATTR_SHAREABLE: u32 = 0x00040000; // Shareable +pub const NVIC_MPU_ATTR_CACHEABLE: u32 = 0x00020000; // Cacheable +pub const NVIC_MPU_ATTR_BUFFRABLE: u32 = 0x00010000; // Bufferable +pub const NVIC_MPU_ATTR_SRD_M: u32 = 0x0000FF00; // Subregion Disable Bits +pub const NVIC_MPU_ATTR_SIZE_M: u32 = 0x0000003E; // Region Size Mask +pub const NVIC_MPU_ATTR_ENABLE: u32 = 0x00000001; // Region Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +pub const NVIC_MPU_BASE1_ADDR_M: u32 = 0xFFFFFFE0; // Base Address Mask +pub const NVIC_MPU_BASE1_VALID: u32 = 0x00000010; // Region Number Valid +pub const NVIC_MPU_BASE1_REGION_M: u32 = 0x00000007; // Region Number +pub const NVIC_MPU_BASE1_ADDR_S: u32 = 5; +pub const NVIC_MPU_BASE1_REGION_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +pub const NVIC_MPU_ATTR1_XN: u32 = 0x10000000; // Instruction Access Disable +pub const NVIC_MPU_ATTR1_AP_M: u32 = 0x07000000; // Access Privilege +pub const NVIC_MPU_ATTR1_TEX_M: u32 = 0x00380000; // Type Extension Mask +pub const NVIC_MPU_ATTR1_SHAREABLE: u32 = 0x00040000; // Shareable +pub const NVIC_MPU_ATTR1_CACHEABLE: u32 = 0x00020000; // Cacheable +pub const NVIC_MPU_ATTR1_BUFFRABLE: u32 = 0x00010000; // Bufferable +pub const NVIC_MPU_ATTR1_SRD_M: u32 = 0x0000FF00; // Subregion Disable Bits +pub const NVIC_MPU_ATTR1_SIZE_M: u32 = 0x0000003E; // Region Size Mask +pub const NVIC_MPU_ATTR1_ENABLE: u32 = 0x00000001; // Region Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +pub const NVIC_MPU_BASE2_ADDR_M: u32 = 0xFFFFFFE0; // Base Address Mask +pub const NVIC_MPU_BASE2_VALID: u32 = 0x00000010; // Region Number Valid +pub const NVIC_MPU_BASE2_REGION_M: u32 = 0x00000007; // Region Number +pub const NVIC_MPU_BASE2_ADDR_S: u32 = 5; +pub const NVIC_MPU_BASE2_REGION_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +pub const NVIC_MPU_ATTR2_XN: u32 = 0x10000000; // Instruction Access Disable +pub const NVIC_MPU_ATTR2_AP_M: u32 = 0x07000000; // Access Privilege +pub const NVIC_MPU_ATTR2_TEX_M: u32 = 0x00380000; // Type Extension Mask +pub const NVIC_MPU_ATTR2_SHAREABLE: u32 = 0x00040000; // Shareable +pub const NVIC_MPU_ATTR2_CACHEABLE: u32 = 0x00020000; // Cacheable +pub const NVIC_MPU_ATTR2_BUFFRABLE: u32 = 0x00010000; // Bufferable +pub const NVIC_MPU_ATTR2_SRD_M: u32 = 0x0000FF00; // Subregion Disable Bits +pub const NVIC_MPU_ATTR2_SIZE_M: u32 = 0x0000003E; // Region Size Mask +pub const NVIC_MPU_ATTR2_ENABLE: u32 = 0x00000001; // Region Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +pub const NVIC_MPU_BASE3_ADDR_M: u32 = 0xFFFFFFE0; // Base Address Mask +pub const NVIC_MPU_BASE3_VALID: u32 = 0x00000010; // Region Number Valid +pub const NVIC_MPU_BASE3_REGION_M: u32 = 0x00000007; // Region Number +pub const NVIC_MPU_BASE3_ADDR_S: u32 = 5; +pub const NVIC_MPU_BASE3_REGION_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +pub const NVIC_MPU_ATTR3_XN: u32 = 0x10000000; // Instruction Access Disable +pub const NVIC_MPU_ATTR3_AP_M: u32 = 0x07000000; // Access Privilege +pub const NVIC_MPU_ATTR3_TEX_M: u32 = 0x00380000; // Type Extension Mask +pub const NVIC_MPU_ATTR3_SHAREABLE: u32 = 0x00040000; // Shareable +pub const NVIC_MPU_ATTR3_CACHEABLE: u32 = 0x00020000; // Cacheable +pub const NVIC_MPU_ATTR3_BUFFRABLE: u32 = 0x00010000; // Bufferable +pub const NVIC_MPU_ATTR3_SRD_M: u32 = 0x0000FF00; // Subregion Disable Bits +pub const NVIC_MPU_ATTR3_SIZE_M: u32 = 0x0000003E; // Region Size Mask +pub const NVIC_MPU_ATTR3_ENABLE: u32 = 0x00000001; // Region Enable +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +pub const NVIC_DBG_CTRL_DBGKEY_M: u32 = 0xFFFF0000; // Debug key mask +pub const NVIC_DBG_CTRL_DBGKEY: u32 = 0xA05F0000; // Debug key +pub const NVIC_DBG_CTRL_S_RESET_ST: u32 = 0x02000000; // Core has reset since last read +pub const NVIC_DBG_CTRL_S_RETIRE_ST: u32 = 0x01000000; // Core has executed insruction + // since last read +pub const NVIC_DBG_CTRL_S_LOCKUP: u32 = 0x00080000; // Core is locked up +pub const NVIC_DBG_CTRL_S_SLEEP: u32 = 0x00040000; // Core is sleeping +pub const NVIC_DBG_CTRL_S_HALT: u32 = 0x00020000; // Core status on halt +pub const NVIC_DBG_CTRL_S_REGRDY: u32 = 0x00010000; // Register read/write available +pub const NVIC_DBG_CTRL_C_SNAPSTALL: u32 = 0x00000020; // Breaks a stalled load/store +pub const NVIC_DBG_CTRL_C_MASKINT: u32 = 0x00000008; // Mask interrupts when stepping +pub const NVIC_DBG_CTRL_C_STEP: u32 = 0x00000004; // Step the core +pub const NVIC_DBG_CTRL_C_HALT: u32 = 0x00000002; // Halt the core +pub const NVIC_DBG_CTRL_C_DEBUGEN: u32 = 0x00000001; // Enable debug +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +pub const NVIC_DBG_XFER_REG_WNR: u32 = 0x00010000; // Write or not read +pub const NVIC_DBG_XFER_REG_SEL_M: u32 = 0x0000001F; // Register +pub const NVIC_DBG_XFER_REG_R0: u32 = 0x00000000; // Register R0 +pub const NVIC_DBG_XFER_REG_R1: u32 = 0x00000001; // Register R1 +pub const NVIC_DBG_XFER_REG_R2: u32 = 0x00000002; // Register R2 +pub const NVIC_DBG_XFER_REG_R3: u32 = 0x00000003; // Register R3 +pub const NVIC_DBG_XFER_REG_R4: u32 = 0x00000004; // Register R4 +pub const NVIC_DBG_XFER_REG_R5: u32 = 0x00000005; // Register R5 +pub const NVIC_DBG_XFER_REG_R6: u32 = 0x00000006; // Register R6 +pub const NVIC_DBG_XFER_REG_R7: u32 = 0x00000007; // Register R7 +pub const NVIC_DBG_XFER_REG_R8: u32 = 0x00000008; // Register R8 +pub const NVIC_DBG_XFER_REG_R9: u32 = 0x00000009; // Register R9 +pub const NVIC_DBG_XFER_REG_R10: u32 = 0x0000000A; // Register R10 +pub const NVIC_DBG_XFER_REG_R11: u32 = 0x0000000B; // Register R11 +pub const NVIC_DBG_XFER_REG_R12: u32 = 0x0000000C; // Register R12 +pub const NVIC_DBG_XFER_REG_R13: u32 = 0x0000000D; // Register R13 +pub const NVIC_DBG_XFER_REG_R14: u32 = 0x0000000E; // Register R14 +pub const NVIC_DBG_XFER_REG_R15: u32 = 0x0000000F; // Register R15 +pub const NVIC_DBG_XFER_REG_FLAGS: u32 = 0x00000010; // xPSR/Flags register +pub const NVIC_DBG_XFER_REG_MSP: u32 = 0x00000011; // Main SP +pub const NVIC_DBG_XFER_REG_PSP: u32 = 0x00000012; // Process SP +pub const NVIC_DBG_XFER_REG_DSP: u32 = 0x00000013; // Deep SP +pub const NVIC_DBG_XFER_REG_CFBP: u32 = 0x00000014; // Control/Fault/BasePri/PriMask +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +pub const NVIC_DBG_DATA_M: u32 = 0xFFFFFFFF; // Data temporary cache +pub const NVIC_DBG_DATA_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +pub const NVIC_DBG_INT_HARDERR: u32 = 0x00000400; // Debug trap on hard fault +pub const NVIC_DBG_INT_INTERR: u32 = 0x00000200; // Debug trap on interrupt errors +pub const NVIC_DBG_INT_BUSERR: u32 = 0x00000100; // Debug trap on bus error +pub const NVIC_DBG_INT_STATERR: u32 = 0x00000080; // Debug trap on usage fault state +pub const NVIC_DBG_INT_CHKERR: u32 = 0x00000040; // Debug trap on usage fault check +pub const NVIC_DBG_INT_NOCPERR: u32 = 0x00000020; // Debug trap on coprocessor error +pub const NVIC_DBG_INT_MMERR: u32 = 0x00000010; // Debug trap on mem manage fault +pub const NVIC_DBG_INT_RESET: u32 = 0x00000008; // Core reset status +pub const NVIC_DBG_INT_RSTPENDCLR: u32 = 0x00000004; // Clear pending core reset +pub const NVIC_DBG_INT_RSTPENDING: u32 = 0x00000002; // Core reset is pending +pub const NVIC_DBG_INT_RSTVCATCH: u32 = 0x00000001; // Reset vector catch +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +pub const NVIC_SW_TRIG_INTID_M: u32 = 0x000000FF; // Interrupt ID +pub const NVIC_SW_TRIG_INTID_S: u32 = 0; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCC register. +// +//***************************************************************************** +pub const NVIC_FPCC_ASPEN: u32 = 0x80000000; // Automatic State Preservation + // Enable +pub const NVIC_FPCC_LSPEN: u32 = 0x40000000; // Lazy State Preservation Enable +pub const NVIC_FPCC_MONRDY: u32 = 0x00000100; // Monitor Ready +pub const NVIC_FPCC_BFRDY: u32 = 0x00000040; // Bus Fault Ready +pub const NVIC_FPCC_MMRDY: u32 = 0x00000020; // Memory Management Fault Ready +pub const NVIC_FPCC_HFRDY: u32 = 0x00000010; // Hard Fault Ready +pub const NVIC_FPCC_THREAD: u32 = 0x00000008; // Thread Mode +pub const NVIC_FPCC_USER: u32 = 0x00000002; // User Privilege Level +pub const NVIC_FPCC_LSPACT: u32 = 0x00000001; // Lazy State Preservation Active +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCA register. +// +//***************************************************************************** +pub const NVIC_FPCA_ADDRESS_M: u32 = 0xFFFFFFF8; // Address +pub const NVIC_FPCA_ADDRESS_S: u32 = 3; +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPDSC register. +// +//***************************************************************************** +pub const NVIC_FPDSC_AHP: u32 = 0x04000000; // AHP Bit Default +pub const NVIC_FPDSC_DN: u32 = 0x02000000; // DN Bit Default +pub const NVIC_FPDSC_FZ: u32 = 0x01000000; // FZ Bit Default +pub const NVIC_FPDSC_RMODE_M: u32 = 0x00C00000; // RMODE Bit Default +pub const NVIC_FPDSC_RMODE_RN: u32 = 0x00000000; // Round to Nearest (RN) mode +pub const NVIC_FPDSC_RMODE_RP: u32 = 0x00400000; // Round towards Plus Infinity (RP) + // mode +pub const NVIC_FPDSC_RMODE_RM: u32 = 0x00800000; // Round towards Minus Infinity + // (RM) mode +pub const NVIC_FPDSC_RMODE_RZ: u32 = 0x00C00000; // Round towards Zero (RZ) mode +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +pub const SYSCTL_DID0_CLASS_BLIZZARD: u32 = 0x00050000; // Tiva(TM) C Series TM4C123-class + // microcontrollers +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ui32IntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +pub const UART_INT_DMATX: u32 = 0x20000; // DMA TX interrupt +pub const UART_INT_DMARX: u32 = 0x10000; // DMA RX interrupt +pub const UART_INT_9BIT: u32 = 0x1000; // 9-bit address match interrupt +pub const UART_INT_OE: u32 = 0x400; // Overrun Error Interrupt Mask +pub const UART_INT_BE: u32 = 0x200; // Break Error Interrupt Mask +pub const UART_INT_PE: u32 = 0x100; // Parity Error Interrupt Mask +pub const UART_INT_FE: u32 = 0x080; // Framing Error Interrupt Mask +pub const UART_INT_RT: u32 = 0x040; // Receive Timeout Interrupt Mask +pub const UART_INT_TX: u32 = 0x020; // Transmit Interrupt Mask +pub const UART_INT_RX: u32 = 0x010; // Receive Interrupt Mask +pub const UART_INT_DSR: u32 = 0x008; // DSR Modem Interrupt Mask +pub const UART_INT_DCD: u32 = 0x004; // DCD Modem Interrupt Mask +pub const UART_INT_CTS: u32 = 0x002; // CTS Modem Interrupt Mask +pub const UART_INT_RI: u32 = 0x001; // RI Modem Interrupt Mask +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter +// and returned by UARTConfigGetExpClk in the pui32Config parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ui32Parity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +pub const UART_CONFIG_WLEN_MASK: u32 = 0x00000060; // Mask for extracting word length +pub const UART_CONFIG_WLEN_8: u32 = 0x00000060; // 8 bit data +pub const UART_CONFIG_WLEN_7: u32 = 0x00000040; // 7 bit data +pub const UART_CONFIG_WLEN_6: u32 = 0x00000020; // 6 bit data +pub const UART_CONFIG_WLEN_5: u32 = 0x00000000; // 5 bit data +pub const UART_CONFIG_STOP_MASK: u32 = 0x00000008; // Mask for extracting stop bits +pub const UART_CONFIG_STOP_ONE: u32 = 0x00000000; // One stop bit +pub const UART_CONFIG_STOP_TWO: u32 = 0x00000008; // Two stop bits +pub const UART_CONFIG_PAR_MASK: u32 = 0x00000086; // Mask for extracting parity +pub const UART_CONFIG_PAR_NONE: u32 = 0x00000000; // No parity +pub const UART_CONFIG_PAR_EVEN: u32 = 0x00000006; // Even parity +pub const UART_CONFIG_PAR_ODD: u32 = 0x00000002; // Odd parity +pub const UART_CONFIG_PAR_ONE: u32 = 0x00000082; // Parity bit is one +pub const UART_CONFIG_PAR_ZERO: u32 = 0x00000086; // Parity bit is zero +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32TxLevel. +// +//***************************************************************************** +pub const UART_FIFO_TX1_8: u32 = 0x00000000; // Transmit interrupt at 1/8 Full +pub const UART_FIFO_TX2_8: u32 = 0x00000001; // Transmit interrupt at 1/4 Full +pub const UART_FIFO_TX4_8: u32 = 0x00000002; // Transmit interrupt at 1/2 Full +pub const UART_FIFO_TX6_8: u32 = 0x00000003; // Transmit interrupt at 3/4 Full +pub const UART_FIFO_TX7_8: u32 = 0x00000004; // Transmit interrupt at 7/8 Full +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32RxLevel. +// +//***************************************************************************** +pub const UART_FIFO_RX1_8: u32 = 0x00000000; // Receive interrupt at 1/8 Full +pub const UART_FIFO_RX2_8: u32 = 0x00000008; // Receive interrupt at 1/4 Full +pub const UART_FIFO_RX4_8: u32 = 0x00000010; // Receive interrupt at 1/2 Full +pub const UART_FIFO_RX6_8: u32 = 0x00000018; // Receive interrupt at 3/4 Full +pub const UART_FIFO_RX7_8: u32 = 0x00000020; // Receive interrupt at 7/8 Full +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +pub const UART_DMA_ERR_RXSTOP: u32 = 0x00000004; // Stop DMA receive if UART error +pub const UART_DMA_TX: u32 = 0x00000002; // Enable DMA for transmit +pub const UART_DMA_RX: u32 = 0x00000001; // Enable DMA for receive +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +pub const UART_RXERROR_OVERRUN: u32 = 0x00000008; +pub const UART_RXERROR_BREAK: u32 = 0x00000004; +pub const UART_RXERROR_PARITY: u32 = 0x00000002; +pub const UART_RXERROR_FRAMING: u32 = 0x00000001; +//***************************************************************************** +// +// Values that can be passed to UARTHandshakeOutputsSet() or returned from +// UARTHandshakeOutputGet(). +// +//***************************************************************************** +pub const UART_OUTPUT_RTS: u32 = 0x00000800; +pub const UART_OUTPUT_DTR: u32 = 0x00000400; +//***************************************************************************** +// +// Values that can be returned from UARTHandshakeInputsGet(). +// +//***************************************************************************** +pub const UART_INPUT_RI: u32 = 0x00000100; +pub const UART_INPUT_DCD: u32 = 0x00000004; +pub const UART_INPUT_DSR: u32 = 0x00000002; +pub const UART_INPUT_CTS: u32 = 0x00000001; +//***************************************************************************** +// +// Values that can be passed to UARTFlowControl() or returned from +// UARTFlowControlGet(). +// +//***************************************************************************** +pub const UART_FLOWCONTROL_TX: u32 = 0x00008000; +pub const UART_FLOWCONTROL_RX: u32 = 0x00004000; +pub const UART_FLOWCONTROL_NONE: u32 = 0x00000000; +//***************************************************************************** +// +// Values that can be passed to UARTTxIntModeSet() or returned from +// UARTTxIntModeGet(). +// +//***************************************************************************** +pub const UART_TXINT_MODE_FIFO: u32 = 0x00000000; +pub const UART_TXINT_MODE_EOT: u32 = 0x00000010; +//***************************************************************************** +// +// Values that can be passed to UARTClockSourceSet() or returned from +// UARTClockSourceGet(). +// +//***************************************************************************** +pub const UART_CLOCK_SYSTEM: u32 = 0x00000000; +pub const UART_CLOCK_PIOSC: u32 = 0x00000005; +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// udma.h - Prototypes and macros for the uDMA controller. +// +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// \addtogroup udma_api +// @{ +// +//***************************************************************************** +//***************************************************************************** +// +// A structure that defines an entry in the channel control table. These +// fields are used by the uDMA controller and normally it is not necessary for +// software to directly read or write fields in the table. +// +//***************************************************************************** + // + // The ending source address of the data transfer. + // + // + // The ending destination address of the data transfer. + // + // + // The channel control mode. + // + // + // An unused location. + // +//***************************************************************************** +// +// A helper macro for building scatter-gather task table entries. +// +// \param ui32TransferCount is the count of items to transfer for this task. +// \param ui32ItemSize is the bit size of the items to transfer for this task. +// \param ui32SrcIncrement is the bit size increment for source data. +// \param pvSrcAddr is the starting address of the data to transfer. +// \param ui32DstIncrement is the bit size increment for destination data. +// \param pvDstAddr is the starting address of the destination data. +// \param ui32ArbSize is the arbitration size to use for the transfer task. +// \param ui32Mode is the transfer mode for this task. +// +// This macro is intended to be used to help populate a table of uDMA tasks +// for a scatter-gather transfer. This macro will calculate the values for +// the fields of a task structure entry based on the input parameters. +// +// There are specific requirements for the values of each parameter. No +// checking is done so it is up to the caller to ensure that correct values +// are used for the parameters. +// +// The \e ui32TransferCount parameter is the number of items that will be +// transferred by this task. It must be in the range 1-1024. +// +// The \e ui32ItemSize parameter is the bit size of the transfer data. It +// must be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. +// +// The \e ui32SrcIncrement parameter is the increment size for the source +// data. It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, +// \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. +// +// The \e pvSrcAddr parameter is a void pointer to the beginning of the source +// data. +// +// The \e ui32DstIncrement parameter is the increment size for the destination +// data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, +// \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. +// +// The \e pvDstAddr parameter is a void pointer to the beginning of the +// location where the data will be transferred. +// +// The \e ui32ArbSize parameter is the arbitration size for the transfer, and +// must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on +// up to \b UDMA_ARB_1024. This is used to select the arbitration size in +// powers of 2, from 1 to 1024. +// +// The \e ui32Mode parameter is the mode to use for this transfer task. It +// must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, +// \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note +// that normally all tasks will be one of the scatter-gather modes while the +// last task is a task list will be AUTO or BASIC. +// +// This macro is intended to be used to initialize individual entries of +// a structure of tDMAControlTable type, like this: +// +// \verbatim +// tDMAControlTable MyTaskList[] = +// { +// uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, +// UDMA_SRC_INC_8, MySourceBuf, +// UDMA_DST_INC_8, MyDestBuf, +// UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), +// uDMATaskStructEntry(Task2Count, ...), +// } +// \endverbatim +// +// \return Nothing; this is not a function. +// +//***************************************************************************** +//pub const uDMATaskStructEntry(ui32TransferCount,: u32 = ui32ItemSize,; +//***************************************************************************** +// +// Close the Doxygen group. +// @} +// +//***************************************************************************** +//***************************************************************************** +// +// Flags that can be passed to uDMAChannelAttributeEnable(), +// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). +// +//***************************************************************************** +pub const UDMA_ATTR_USEBURST: u32 = 0x00000001; +pub const UDMA_ATTR_ALTSELECT: u32 = 0x00000002; +pub const UDMA_ATTR_HIGH_PRIORITY: u32 = 0x00000004; +pub const UDMA_ATTR_REQMASK: u32 = 0x00000008; +pub const UDMA_ATTR_ALL: u32 = 0x0000000F; +//***************************************************************************** +// +// DMA control modes that can be passed to uDMAModeSet() and returned +// uDMAModeGet(). +// +//***************************************************************************** +pub const UDMA_MODE_STOP: u32 = 0x00000000; +pub const UDMA_MODE_BASIC: u32 = 0x00000001; +pub const UDMA_MODE_AUTO: u32 = 0x00000002; +pub const UDMA_MODE_PINGPONG: u32 = 0x00000003; +pub const UDMA_MODE_MEM_SCATTER_GATHER: u32 = 0x00000004; +pub const UDMA_MODE_PER_SCATTER_GATHER: u32 = 0x00000006; +pub const UDMA_MODE_ALT_SELECT: u32 = 0x00000001; +//***************************************************************************** +// +// Channel configuration values that can be passed to uDMAControlSet(). +// +//***************************************************************************** +pub const UDMA_DST_INC_8: u32 = 0x00000000; +pub const UDMA_DST_INC_16: u32 = 0x40000000; +pub const UDMA_DST_INC_32: u32 = 0x80000000; +pub const UDMA_DST_INC_NONE: u32 = 0xc0000000; +pub const UDMA_SRC_INC_8: u32 = 0x00000000; +pub const UDMA_SRC_INC_16: u32 = 0x04000000; +pub const UDMA_SRC_INC_32: u32 = 0x08000000; +pub const UDMA_SRC_INC_NONE: u32 = 0x0c000000; +pub const UDMA_SIZE_8: u32 = 0x00000000; +pub const UDMA_SIZE_16: u32 = 0x11000000; +pub const UDMA_SIZE_32: u32 = 0x22000000; +pub const UDMA_DST_PROT_PRIV: u32 = 0x00200000; +pub const UDMA_SRC_PROT_PRIV: u32 = 0x00040000; +pub const UDMA_ARB_1: u32 = 0x00000000; +pub const UDMA_ARB_2: u32 = 0x00004000; +pub const UDMA_ARB_4: u32 = 0x00008000; +pub const UDMA_ARB_8: u32 = 0x0000c000; +pub const UDMA_ARB_16: u32 = 0x00010000; +pub const UDMA_ARB_32: u32 = 0x00014000; +pub const UDMA_ARB_64: u32 = 0x00018000; +pub const UDMA_ARB_128: u32 = 0x0001c000; +pub const UDMA_ARB_256: u32 = 0x00020000; +pub const UDMA_ARB_512: u32 = 0x00024000; +pub const UDMA_ARB_1024: u32 = 0x00028000; +pub const UDMA_NEXT_USEBURST: u32 = 0x00000008; +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. +// +//***************************************************************************** +pub const UDMA_CHANNEL_USBEP1RX: u32 = 0; +pub const UDMA_CHANNEL_USBEP1TX: u32 = 1; +pub const UDMA_CHANNEL_USBEP2RX: u32 = 2; +pub const UDMA_CHANNEL_USBEP2TX: u32 = 3; +pub const UDMA_CHANNEL_USBEP3RX: u32 = 4; +pub const UDMA_CHANNEL_USBEP3TX: u32 = 5; +pub const UDMA_CHANNEL_ETH0RX: u32 = 6; +pub const UDMA_CHANNEL_ETH0TX: u32 = 7; +pub const UDMA_CHANNEL_UART0RX: u32 = 8; +pub const UDMA_CHANNEL_UART0TX: u32 = 9; +pub const UDMA_CHANNEL_SSI0RX: u32 = 10; +pub const UDMA_CHANNEL_SSI0TX: u32 = 11; +pub const UDMA_CHANNEL_ADC0: u32 = 14; +pub const UDMA_CHANNEL_ADC1: u32 = 15; +pub const UDMA_CHANNEL_ADC2: u32 = 16; +pub const UDMA_CHANNEL_ADC3: u32 = 17; +pub const UDMA_CHANNEL_TMR0A: u32 = 18; +pub const UDMA_CHANNEL_TMR0B: u32 = 19; +pub const UDMA_CHANNEL_TMR1A: u32 = 20; +pub const UDMA_CHANNEL_TMR1B: u32 = 21; +pub const UDMA_CHANNEL_UART1RX: u32 = 22; +pub const UDMA_CHANNEL_UART1TX: u32 = 23; +pub const UDMA_CHANNEL_SSI1RX: u32 = 24; +pub const UDMA_CHANNEL_SSI1TX: u32 = 25; +pub const UDMA_CHANNEL_I2S0RX: u32 = 28; +pub const UDMA_CHANNEL_I2S0TX: u32 = 29; +pub const UDMA_CHANNEL_SW: u32 = 30; +//***************************************************************************** +// +// Flags to be OR'd with the channel ID to indicate if the primary or alternate +// control structure should be used. +// +//***************************************************************************** +pub const UDMA_PRI_SELECT: u32 = 0x00000000; +pub const UDMA_ALT_SELECT: u32 = 0x00000020; +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. These are for secondary peripheral assignments. +// +//***************************************************************************** +pub const UDMA_SEC_CHANNEL_UART2RX_0: u32 = 0; +pub const UDMA_SEC_CHANNEL_UART2TX_1: u32 = 1; +pub const UDMA_SEC_CHANNEL_TMR3A: u32 = 2; +pub const UDMA_SEC_CHANNEL_TMR3B: u32 = 3; +pub const UDMA_SEC_CHANNEL_TMR2A_4: u32 = 4; +pub const UDMA_SEC_CHANNEL_TMR2B_5: u32 = 5; +pub const UDMA_SEC_CHANNEL_TMR2A_6: u32 = 6; +pub const UDMA_SEC_CHANNEL_TMR2B_7: u32 = 7; +pub const UDMA_SEC_CHANNEL_UART1RX: u32 = 8; +pub const UDMA_SEC_CHANNEL_UART1TX: u32 = 9; +pub const UDMA_SEC_CHANNEL_SSI1RX: u32 = 10; +pub const UDMA_SEC_CHANNEL_SSI1TX: u32 = 11; +pub const UDMA_SEC_CHANNEL_UART2RX_12: u32 = 12; +pub const UDMA_SEC_CHANNEL_UART2TX_13: u32 = 13; +pub const UDMA_SEC_CHANNEL_TMR2A_14: u32 = 14; +pub const UDMA_SEC_CHANNEL_TMR2B_15: u32 = 15; +pub const UDMA_SEC_CHANNEL_TMR1A: u32 = 18; +pub const UDMA_SEC_CHANNEL_TMR1B: u32 = 19; +pub const UDMA_SEC_CHANNEL_EPI0RX: u32 = 20; +pub const UDMA_SEC_CHANNEL_EPI0TX: u32 = 21; +pub const UDMA_SEC_CHANNEL_ADC10: u32 = 24; +pub const UDMA_SEC_CHANNEL_ADC11: u32 = 25; +pub const UDMA_SEC_CHANNEL_ADC12: u32 = 26; +pub const UDMA_SEC_CHANNEL_ADC13: u32 = 27; +pub const UDMA_SEC_CHANNEL_SW: u32 = 30; +//***************************************************************************** +// +// Values that can be passed to uDMAChannelAssign() to select peripheral +// mapping for each channel. The channels named RESERVED may be assigned +// to a peripheral in future parts. +// +//***************************************************************************** +// +// Channel 0 +// +pub const UDMA_CH0_USB0EP1RX: u32 = 0x00000000; +pub const UDMA_CH0_UART2RX: u32 = 0x00010000; +pub const UDMA_CH0_RESERVED2: u32 = 0x00020000; +pub const UDMA_CH0_TIMER4A: u32 = 0x00030000; +pub const UDMA_CH0_RESERVED4: u32 = 0x00040000; +pub const UDMA_CH0_RESERVED5: u32 = 0x00050000; +pub const UDMA_CH0_I2C0RX: u32 = 0x00060000; +pub const UDMA_CH0_RESERVED7: u32 = 0x00070000; +pub const UDMA_CH0_RESERVED8: u32 = 0x00080000; +// +// Channel 1 +// +pub const UDMA_CH1_USB0EP1TX: u32 = 0x00000001; +pub const UDMA_CH1_UART2TX: u32 = 0x00010001; +pub const UDMA_CH1_RESERVED2: u32 = 0x00020001; +pub const UDMA_CH1_TIMER4B: u32 = 0x00030001; +pub const UDMA_CH1_RESERVED4: u32 = 0x00040001; +pub const UDMA_CH1_RESERVED5: u32 = 0x00050001; +pub const UDMA_CH1_I2C0TX: u32 = 0x00060001; +pub const UDMA_CH1_RESERVED7: u32 = 0x00070001; +pub const UDMA_CH1_RESERVED8: u32 = 0x00080001; +// +// Channel 2 +// +pub const UDMA_CH2_USB0EP2RX: u32 = 0x00000002; +pub const UDMA_CH2_TIMER3A: u32 = 0x00010002; +pub const UDMA_CH2_RESERVED2: u32 = 0x00020002; +pub const UDMA_CH2_RESERVED3: u32 = 0x00030002; +pub const UDMA_CH2_RESERVED4: u32 = 0x00040002; +pub const UDMA_CH2_RESERVED5: u32 = 0x00050002; +pub const UDMA_CH2_I2C1RX: u32 = 0x00060002; +pub const UDMA_CH2_RESERVED7: u32 = 0x00070002; +pub const UDMA_CH2_RESERVED8: u32 = 0x00080002; +// +// Channel 3 +// +pub const UDMA_CH3_USB0EP2TX: u32 = 0x00000003; +pub const UDMA_CH3_TIMER3B: u32 = 0x00010003; +pub const UDMA_CH3_RESERVED2: u32 = 0x00020003; +pub const UDMA_CH3_LPC0_3: u32 = 0x00030003; +pub const UDMA_CH3_RESERVED4: u32 = 0x00040003; +pub const UDMA_CH3_RESERVED5: u32 = 0x00050003; +pub const UDMA_CH3_I2C1TX: u32 = 0x00060003; +pub const UDMA_CH3_RESERVED7: u32 = 0x00070003; +pub const UDMA_CH3_RESERVED8: u32 = 0x00080003; +// +// Channel 4 +// +pub const UDMA_CH4_USB0EP3RX: u32 = 0x00000004; +pub const UDMA_CH4_TIMER2A: u32 = 0x00010004; +pub const UDMA_CH4_RESERVED2: u32 = 0x00020004; +pub const UDMA_CH4_GPIOA: u32 = 0x00030004; +pub const UDMA_CH4_RESERVED4: u32 = 0x00040004; +pub const UDMA_CH4_SHAMD50CIN: u32 = 0x00050004; +pub const UDMA_CH4_I2C2RX: u32 = 0x00060004; +pub const UDMA_CH4_RESERVED7: u32 = 0x00070004; +pub const UDMA_CH4_RESERVED8: u32 = 0x00080004; +// +// Channel 5 +// +pub const UDMA_CH5_USB0EP3TX: u32 = 0x00000005; +pub const UDMA_CH5_TIMER2B: u32 = 0x00010005; +pub const UDMA_CH5_RESERVED2: u32 = 0x00020005; +pub const UDMA_CH5_GPIOB: u32 = 0x00030005; +pub const UDMA_CH5_RESERVED4: u32 = 0x00040005; +pub const UDMA_CH5_SHAMD50DIN: u32 = 0x00050005; +pub const UDMA_CH5_I2C2TX: u32 = 0x00060005; +pub const UDMA_CH5_RESERVED7: u32 = 0x00070005; +pub const UDMA_CH5_RESERVED8: u32 = 0x00080005; +// +// Channel 6 +// +pub const UDMA_CH6_RESERVED0: u32 = 0x00000006; +pub const UDMA_CH6_ETH0RX: u32 = 0x00000006; +pub const UDMA_CH6_TIMER2A: u32 = 0x00010006; +pub const UDMA_CH6_UART5RX: u32 = 0x00020006; +pub const UDMA_CH6_GPIOC: u32 = 0x00030006; +pub const UDMA_CH6_I2C0RX: u32 = 0x00040006; +pub const UDMA_CH6_SHAMD50COUT: u32 = 0x00050006; +pub const UDMA_CH6_RESERVED6: u32 = 0x00060006; +pub const UDMA_CH6_RESERVED7: u32 = 0x00070006; +pub const UDMA_CH6_RESERVED8: u32 = 0x00080006; +// +// Channel 7 +// +pub const UDMA_CH7_RESERVED0: u32 = 0x00000007; +pub const UDMA_CH7_ETH0TX: u32 = 0x00000007; +pub const UDMA_CH7_TIMER2B: u32 = 0x00010007; +pub const UDMA_CH7_UART5TX: u32 = 0x00020007; +pub const UDMA_CH7_GPIOD: u32 = 0x00030007; +pub const UDMA_CH7_I2C0TX: u32 = 0x00040007; +pub const UDMA_CH7_RESERVED5: u32 = 0x00050007; +pub const UDMA_CH7_RESERVED6: u32 = 0x00060007; +pub const UDMA_CH7_RESERVED7: u32 = 0x00070007; +pub const UDMA_CH7_RESERVED8: u32 = 0x00080007; +// +// Channel 8 +// +pub const UDMA_CH8_UART0RX: u32 = 0x00000008; +pub const UDMA_CH8_UART1RX: u32 = 0x00010008; +pub const UDMA_CH8_RESERVED2: u32 = 0x00020008; +pub const UDMA_CH8_TIMER5A: u32 = 0x00030008; +pub const UDMA_CH8_I2C1RX: u32 = 0x00040008; +pub const UDMA_CH8_RESERVED5: u32 = 0x00050008; +pub const UDMA_CH8_RESERVED6: u32 = 0x00060008; +pub const UDMA_CH8_RESERVED7: u32 = 0x00070008; +pub const UDMA_CH8_RESERVED8: u32 = 0x00080008; +// +// Channel 9 +// +pub const UDMA_CH9_UART0TX: u32 = 0x00000009; +pub const UDMA_CH9_UART1TX: u32 = 0x00010009; +pub const UDMA_CH9_RESERVED2: u32 = 0x00020009; +pub const UDMA_CH9_TIMER5B: u32 = 0x00030009; +pub const UDMA_CH9_I2C1TX: u32 = 0x00040009; +pub const UDMA_CH9_RESERVED5: u32 = 0x00050009; +pub const UDMA_CH9_RESERVED6: u32 = 0x00060009; +pub const UDMA_CH9_RESERVED7: u32 = 0x00070009; +pub const UDMA_CH9_RESERVED8: u32 = 0x00080009; +// +// Channel 10 +// +pub const UDMA_CH10_SSI0RX: u32 = 0x0000000A; +pub const UDMA_CH10_SSI1RX: u32 = 0x0001000A; +pub const UDMA_CH10_UART6RX: u32 = 0x0002000A; +pub const UDMA_CH10_WTIMER0A: u32 = 0x0003000A; +pub const UDMA_CH10_I2C2RX: u32 = 0x0004000A; +pub const UDMA_CH10_RESERVED5: u32 = 0x0005000A; +pub const UDMA_CH10_RESERVED6: u32 = 0x0006000A; +pub const UDMA_CH10_TIMER6A: u32 = 0x0007000A; +pub const UDMA_CH10_RESERVED8: u32 = 0x0008000A; +// +// Channel 11 +// +pub const UDMA_CH11_SSI0TX: u32 = 0x0000000B; +pub const UDMA_CH11_SSI1TX: u32 = 0x0001000B; +pub const UDMA_CH11_UART6TX: u32 = 0x0002000B; +pub const UDMA_CH11_WTIMER0B: u32 = 0x0003000B; +pub const UDMA_CH11_I2C2TX: u32 = 0x0004000B; +pub const UDMA_CH11_RESERVED5: u32 = 0x0005000B; +pub const UDMA_CH11_RESERVED6: u32 = 0x0006000B; +pub const UDMA_CH11_TIMER6B: u32 = 0x0007000B; +pub const UDMA_CH11_RESERVED8: u32 = 0x0008000B; +// +// Channel 12 +// +pub const UDMA_CH12_RESERVED0: u32 = 0x0000000C; +pub const UDMA_CH12_UART2RX: u32 = 0x0001000C; +pub const UDMA_CH12_SSI2RX: u32 = 0x0002000C; +pub const UDMA_CH12_WTIMER1A: u32 = 0x0003000C; +pub const UDMA_CH12_GPIOK: u32 = 0x0004000C; +pub const UDMA_CH12_AES0CIN: u32 = 0x0005000C; +pub const UDMA_CH12_RESERVED6: u32 = 0x0006000C; +pub const UDMA_CH12_TIMER7A: u32 = 0x0007000C; +pub const UDMA_CH12_RESERVED8: u32 = 0x0008000C; +// +// Channel 13 +// +pub const UDMA_CH13_RESERVED0: u32 = 0x0000000D; +pub const UDMA_CH13_UART2TX: u32 = 0x0001000D; +pub const UDMA_CH13_SSI2TX: u32 = 0x0002000D; +pub const UDMA_CH13_WTIMER1B: u32 = 0x0003000D; +pub const UDMA_CH13_GPIOL: u32 = 0x0004000D; +pub const UDMA_CH13_AES0COUT: u32 = 0x0005000D; +pub const UDMA_CH13_RESERVED6: u32 = 0x0006000D; +pub const UDMA_CH13_TIMER7B: u32 = 0x0007000D; +pub const UDMA_CH13_RESERVED8: u32 = 0x0008000D; +// +// Channel 14 +// +pub const UDMA_CH14_ADC0_0: u32 = 0x0000000E; +pub const UDMA_CH14_TIMER2A: u32 = 0x0001000E; +pub const UDMA_CH14_SSI3RX: u32 = 0x0002000E; +pub const UDMA_CH14_GPIOE: u32 = 0x0003000E; +pub const UDMA_CH14_GPIOM: u32 = 0x0004000E; +pub const UDMA_CH14_AES0DIN: u32 = 0x0005000E; +pub const UDMA_CH14_RESERVED6: u32 = 0x0006000E; +pub const UDMA_CH14_RESERVED7: u32 = 0x0007000E; +pub const UDMA_CH14_RESERVED8: u32 = 0x0008000E; +// +// Channel 15 +// +pub const UDMA_CH15_ADC0_1: u32 = 0x0000000F; +pub const UDMA_CH15_TIMER2B: u32 = 0x0001000F; +pub const UDMA_CH15_SSI3TX: u32 = 0x0002000F; +pub const UDMA_CH15_GPIOF: u32 = 0x0003000F; +pub const UDMA_CH15_GPION: u32 = 0x0004000F; +pub const UDMA_CH15_AES0DOUT: u32 = 0x0005000F; +pub const UDMA_CH15_RESERVED6: u32 = 0x0006000F; +pub const UDMA_CH15_RESERVED7: u32 = 0x0007000F; +pub const UDMA_CH15_RESERVED8: u32 = 0x0008000F; +// +// Channel 16 +// +pub const UDMA_CH16_ADC0_2: u32 = 0x00000010; +pub const UDMA_CH16_RESERVED1: u32 = 0x00010010; +pub const UDMA_CH16_UART3RX: u32 = 0x00020010; +pub const UDMA_CH16_WTIMER2A: u32 = 0x00030010; +pub const UDMA_CH16_GPIOP: u32 = 0x00040010; +pub const UDMA_CH16_RESERVED5: u32 = 0x00050010; +pub const UDMA_CH16_RESERVED6: u32 = 0x00060010; +pub const UDMA_CH16_RESERVED7: u32 = 0x00070010; +pub const UDMA_CH16_RESERVED8: u32 = 0x00080010; +// +// Channel 17 +// +pub const UDMA_CH17_ADC0_3: u32 = 0x00000011; +pub const UDMA_CH17_RESERVED1: u32 = 0x00010011; +pub const UDMA_CH17_UART3TX: u32 = 0x00020011; +pub const UDMA_CH17_WTIMER2B: u32 = 0x00030011; +pub const UDMA_CH17_RESERVED4: u32 = 0x00040011; +pub const UDMA_CH17_RESERVED5: u32 = 0x00050011; +pub const UDMA_CH17_RESERVED6: u32 = 0x00060011; +pub const UDMA_CH17_RESERVED7: u32 = 0x00070011; +pub const UDMA_CH17_RESERVED8: u32 = 0x00080011; +// +// Channel 18 +// +pub const UDMA_CH18_TIMER0A: u32 = 0x00000012; +pub const UDMA_CH18_TIMER1A: u32 = 0x00010012; +pub const UDMA_CH18_UART4RX: u32 = 0x00020012; +pub const UDMA_CH18_GPIOB: u32 = 0x00030012; +pub const UDMA_CH18_I2C3RX: u32 = 0x00040012; +pub const UDMA_CH18_RESERVED5: u32 = 0x00050012; +pub const UDMA_CH18_RESERVED6: u32 = 0x00060012; +pub const UDMA_CH18_RESERVED7: u32 = 0x00070012; +pub const UDMA_CH18_RESERVED8: u32 = 0x00080012; +// +// Channel 19 +// +pub const UDMA_CH19_TIMER0B: u32 = 0x00000013; +pub const UDMA_CH19_TIMER1B: u32 = 0x00010013; +pub const UDMA_CH19_UART4TX: u32 = 0x00020013; +pub const UDMA_CH19_GPIOG: u32 = 0x00030013; +pub const UDMA_CH19_I2C3TX: u32 = 0x00040013; +pub const UDMA_CH19_RESERVED5: u32 = 0x00050013; +pub const UDMA_CH19_RESERVED6: u32 = 0x00060013; +pub const UDMA_CH19_RESERVED7: u32 = 0x00070013; +pub const UDMA_CH19_RESERVED8: u32 = 0x00080013; +// +// Channel 20 +// +pub const UDMA_CH20_TIMER1A: u32 = 0x00000014; +pub const UDMA_CH20_RESERVED1: u32 = 0x00010014; +pub const UDMA_CH20_EPI0RX: u32 = 0x00010014; +pub const UDMA_CH20_UART7RX: u32 = 0x00020014; +pub const UDMA_CH20_GPIOH: u32 = 0x00030014; +pub const UDMA_CH20_I2C4RX: u32 = 0x00040014; +pub const UDMA_CH20_DES0CIN: u32 = 0x00050014; +pub const UDMA_CH20_RESERVED6: u32 = 0x00060014; +pub const UDMA_CH20_RESERVED7: u32 = 0x00070014; +pub const UDMA_CH20_RESERVED8: u32 = 0x00080014; +// +// Channel 21 +// +pub const UDMA_CH21_TIMER1B: u32 = 0x00000015; +pub const UDMA_CH21_RESERVED1: u32 = 0x00010015; +pub const UDMA_CH21_EPI0TX: u32 = 0x00010015; +pub const UDMA_CH21_UART7TX: u32 = 0x00020015; +pub const UDMA_CH21_GPIOJ: u32 = 0x00030015; +pub const UDMA_CH21_I2C4TX: u32 = 0x00040015; +pub const UDMA_CH21_DES0DIN: u32 = 0x00050015; +pub const UDMA_CH21_RESERVED6: u32 = 0x00060015; +pub const UDMA_CH21_RESERVED7: u32 = 0x00070015; +pub const UDMA_CH21_RESERVED8: u32 = 0x00080015; +// +// Channel 22 +// +pub const UDMA_CH22_UART1RX: u32 = 0x00000016; +pub const UDMA_CH22_RESERVED1: u32 = 0x00010016; +pub const UDMA_CH22_RESERVED2: u32 = 0x00020016; +pub const UDMA_CH22_LPC0_2: u32 = 0x00030016; +pub const UDMA_CH22_I2C5RX: u32 = 0x00040016; +pub const UDMA_CH22_DES0DOUT: u32 = 0x00050016; +pub const UDMA_CH22_RESERVED6: u32 = 0x00060016; +pub const UDMA_CH22_RESERVED7: u32 = 0x00070016; +pub const UDMA_CH22_I2C8RX: u32 = 0x00080016; +// +// Channel 23 +// +pub const UDMA_CH23_UART1TX: u32 = 0x00000017; +pub const UDMA_CH23_RESERVED1: u32 = 0x00010017; +pub const UDMA_CH23_RESERVED2: u32 = 0x00020017; +pub const UDMA_CH23_LPC0_1: u32 = 0x00030017; +pub const UDMA_CH23_I2C5TX: u32 = 0x00040017; +pub const UDMA_CH23_RESERVED5: u32 = 0x00050017; +pub const UDMA_CH23_RESERVED6: u32 = 0x00060017; +pub const UDMA_CH23_RESERVED7: u32 = 0x00070017; +pub const UDMA_CH23_I2C8TX: u32 = 0x00080017; +// +// Channel 24 +// +pub const UDMA_CH24_SSI1RX: u32 = 0x00000018; +pub const UDMA_CH24_ADC1_0: u32 = 0x00010018; +pub const UDMA_CH24_RESERVED2: u32 = 0x00020018; +pub const UDMA_CH24_WTIMER3A: u32 = 0x00030018; +pub const UDMA_CH24_GPIOQ: u32 = 0x00040018; +pub const UDMA_CH24_RESERVED5: u32 = 0x00050018; +pub const UDMA_CH24_RESERVED6: u32 = 0x00060018; +pub const UDMA_CH24_RESERVED7: u32 = 0x00070018; +pub const UDMA_CH24_I2C9RX: u32 = 0x00080018; +// +// Channel 25 +// +pub const UDMA_CH25_SSI1TX: u32 = 0x00000019; +pub const UDMA_CH25_ADC1_1: u32 = 0x00010019; +pub const UDMA_CH25_RESERVED2: u32 = 0x00020019; +pub const UDMA_CH25_WTIMER3B: u32 = 0x00030019; +pub const UDMA_CH25_RESERVED4: u32 = 0x00040019; +pub const UDMA_CH25_RESERVED5: u32 = 0x00050019; +pub const UDMA_CH25_RESERVED6: u32 = 0x00060019; +pub const UDMA_CH25_RESERVED7: u32 = 0x00070019; +pub const UDMA_CH25_I2C9TX: u32 = 0x00080019; +// +// Channel 26 +// +pub const UDMA_CH26_RESERVED0: u32 = 0x0000001A; +pub const UDMA_CH26_ADC1_2: u32 = 0x0001001A; +pub const UDMA_CH26_RESERVED2: u32 = 0x0002001A; +pub const UDMA_CH26_WTIMER4A: u32 = 0x0003001A; +pub const UDMA_CH26_RESERVED4: u32 = 0x0004001A; +pub const UDMA_CH26_RESERVED5: u32 = 0x0005001A; +pub const UDMA_CH26_RESERVED6: u32 = 0x0006001A; +pub const UDMA_CH26_RESERVED7: u32 = 0x0007001A; +pub const UDMA_CH26_I2C6RX: u32 = 0x0008001A; +// +// Channel 27 +// +pub const UDMA_CH27_RESERVED0: u32 = 0x0000001B; +pub const UDMA_CH27_ADC1_3: u32 = 0x0001001B; +pub const UDMA_CH27_RESERVED2: u32 = 0x0002001B; +pub const UDMA_CH27_WTIMER4B: u32 = 0x0003001B; +pub const UDMA_CH27_RESERVED4: u32 = 0x0004001B; +pub const UDMA_CH27_RESERVED5: u32 = 0x0005001B; +pub const UDMA_CH27_RESERVED6: u32 = 0x0006001B; +pub const UDMA_CH27_RESERVED7: u32 = 0x0007001B; +pub const UDMA_CH27_I2C6TX: u32 = 0x0008001B; +// +// Channel 28 +// +pub const UDMA_CH28_RESERVED0: u32 = 0x0000001C; +pub const UDMA_CH28_RESERVED1: u32 = 0x0001001C; +pub const UDMA_CH28_RESERVED2: u32 = 0x0002001C; +pub const UDMA_CH28_WTIMER5A: u32 = 0x0003001C; +pub const UDMA_CH28_RESERVED4: u32 = 0x0004001C; +pub const UDMA_CH28_RESERVED5: u32 = 0x0005001C; +pub const UDMA_CH28_RESERVED6: u32 = 0x0006001C; +pub const UDMA_CH28_RESERVED7: u32 = 0x0007001C; +pub const UDMA_CH28_I2C7RX: u32 = 0x0008001C; +// +// Channel 29 +// +pub const UDMA_CH29_RESERVED0: u32 = 0x0000001D; +pub const UDMA_CH29_RESERVED1: u32 = 0x0001001D; +pub const UDMA_CH29_RESERVED2: u32 = 0x0002001D; +pub const UDMA_CH29_WTIMER5B: u32 = 0x0003001D; +pub const UDMA_CH29_RESERVED4: u32 = 0x0004001D; +pub const UDMA_CH29_RESERVED5: u32 = 0x0005001D; +pub const UDMA_CH29_RESERVED6: u32 = 0x0006001D; +pub const UDMA_CH29_RESERVED7: u32 = 0x0007001D; +pub const UDMA_CH29_I2C7TX: u32 = 0x0008001D; +// +// Channel 30 +// +pub const UDMA_CH30_SW: u32 = 0x0000001E; +pub const UDMA_CH30_RESERVED1: u32 = 0x0001001E; +pub const UDMA_CH30_RESERVED2: u32 = 0x0002001E; +pub const UDMA_CH30_RESERVED3: u32 = 0x0003001E; +pub const UDMA_CH30_RESERVED4: u32 = 0x0004001E; +pub const UDMA_CH30_RESERVED5: u32 = 0x0005001E; +pub const UDMA_CH30_RESERVED6: u32 = 0x0006001E; +pub const UDMA_CH30_EPI0RX: u32 = 0x0007001E; +pub const UDMA_CH30_1WIRE0: u32 = 0x0008001E; +// +// Channel 31 +// +pub const UDMA_CH31_RESERVED0: u32 = 0x0000001F; +pub const UDMA_CH31_RESERVED1: u32 = 0x0001001F; +pub const UDMA_CH31_RESERVED2: u32 = 0x0002001F; +pub const UDMA_CH31_LPC0_0: u32 = 0x0003001F; +pub const UDMA_CH31_RESERVED4: u32 = 0x0004001F; +pub const UDMA_CH31_RESERVED5: u32 = 0x0005001F; +pub const UDMA_CH31_RESERVED6: u32 = 0x0006001F; +pub const UDMA_CH31_EPI0RX: u32 = 0x0007001F; +pub const UDMA_CH31_RESERVED8: u32 = 0x0008001F; +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +// The following functions and definitions are deprecated and will be removed +// from the API in the future. Use uDMAChannelAssign() instead to accomplish +// the same end. +// +//***************************************************************************** +//***************************************************************************** +// +// uDMA default/secondary peripheral selections, to be passed to +// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault(). +// +//***************************************************************************** +pub const UDMA_DEF_USBEP1RX_SEC_UART2RX: u32 = 0x00000001; +pub const UDMA_DEF_USBEP1TX_SEC_UART2TX: u32 = 0x00000002; +pub const UDMA_DEF_USBEP2RX_SEC_TMR3A: u32 = 0x00000004; +pub const UDMA_DEF_USBEP2TX_SEC_TMR3B: u32 = 0x00000008; +pub const UDMA_DEF_USBEP3RX_SEC_TMR2A: u32 = 0x00000010; +pub const UDMA_DEF_USBEP3TX_SEC_TMR2B: u32 = 0x00000020; +pub const UDMA_DEF_ETH0RX_SEC_TMR2A: u32 = 0x00000040; +pub const UDMA_DEF_ETH0TX_SEC_TMR2B: u32 = 0x00000080; +pub const UDMA_DEF_UART0RX_SEC_UART1RX: u32 = 0x00000100; +pub const UDMA_DEF_UART0TX_SEC_UART1TX: u32 = 0x00000200; +pub const UDMA_DEF_SSI0RX_SEC_SSI1RX: u32 = 0x00000400; +pub const UDMA_DEF_SSI0TX_SEC_SSI1TX: u32 = 0x00000800; +pub const UDMA_DEF_RESERVED_SEC_UART2RX: u32 = 0x00001000; +pub const UDMA_DEF_RESERVED_SEC_UART2TX: u32 = 0x00002000; +pub const UDMA_DEF_ADC00_SEC_TMR2A: u32 = 0x00004000; +pub const UDMA_DEF_ADC01_SEC_TMR2B: u32 = 0x00008000; +pub const UDMA_DEF_ADC02_SEC_RESERVED: u32 = 0x00010000; +pub const UDMA_DEF_ADC03_SEC_RESERVED: u32 = 0x00020000; +pub const UDMA_DEF_TMR0A_SEC_TMR1A: u32 = 0x00040000; +pub const UDMA_DEF_TMR0B_SEC_TMR1B: u32 = 0x00080000; +pub const UDMA_DEF_TMR1A_SEC_EPI0RX: u32 = 0x00100000; +pub const UDMA_DEF_TMR1B_SEC_EPI0TX: u32 = 0x00200000; +pub const UDMA_DEF_UART1RX_SEC_RESERVED: u32 = 0x00400000; +pub const UDMA_DEF_UART1TX_SEC_RESERVED: u32 = 0x00800000; +pub const UDMA_DEF_SSI1RX_SEC_ADC10: u32 = 0x01000000; +pub const UDMA_DEF_SSI1TX_SEC_ADC11: u32 = 0x02000000; +pub const UDMA_DEF_RESERVED_SEC_ADC12: u32 = 0x04000000; +pub const UDMA_DEF_RESERVED_SEC_ADC13: u32 = 0x08000000; +pub const UDMA_DEF_I2S0RX_SEC_RESERVED: u32 = 0x10000000; +pub const UDMA_DEF_I2S0TX_SEC_RESERVED: u32 = 0x20000000; +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// usb.h - Prototypes for the USB Interface Driver. +// +// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableControl() and +// USBIntDisableControl() as the ui32Flags parameter, and are returned from +// USBIntStatusControl(). +// +//***************************************************************************** +pub const USB_INTCTRL_ALL: u32 = 0x000003FF; // All control interrupt sources +pub const USB_INTCTRL_STATUS: u32 = 0x000000FF; // Status Interrupts +pub const USB_INTCTRL_VBUS_ERR: u32 = 0x00000080; // VBUS Error +pub const USB_INTCTRL_SESSION: u32 = 0x00000040; // Session Start Detected +pub const USB_INTCTRL_SESSION_END: u32 = 0x00000040; // Session End Detected +pub const USB_INTCTRL_DISCONNECT: u32 = 0x00000020; // Disconnect Detected +pub const USB_INTCTRL_CONNECT: u32 = 0x00000010; // Device Connect Detected +pub const USB_INTCTRL_SOF: u32 = 0x00000008; // Start of Frame Detected +pub const USB_INTCTRL_BABBLE: u32 = 0x00000004; // Babble signaled +pub const USB_INTCTRL_RESET: u32 = 0x00000004; // Reset signaled +pub const USB_INTCTRL_RESUME: u32 = 0x00000002; // Resume detected +pub const USB_INTCTRL_SUSPEND: u32 = 0x00000001; // Suspend detected +pub const USB_INTCTRL_MODE_DETECT: u32 = 0x00000200; // Mode value valid +pub const USB_INTCTRL_POWER_FAULT: u32 = 0x00000100; // Power Fault detected +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableEndpoint() and +// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from +// USBIntStatusEndpoint(). +// +//***************************************************************************** +pub const USB_INTEP_ALL: u32 = 0xFFFFFFFF; // Host IN Interrupts +pub const USB_INTEP_HOST_IN: u32 = 0xFFFE0000; // Host IN Interrupts +pub const USB_INTEP_HOST_IN_15: u32 = 0x80000000; // Endpoint 15 Host IN Interrupt +pub const USB_INTEP_HOST_IN_14: u32 = 0x40000000; // Endpoint 14 Host IN Interrupt +pub const USB_INTEP_HOST_IN_13: u32 = 0x20000000; // Endpoint 13 Host IN Interrupt +pub const USB_INTEP_HOST_IN_12: u32 = 0x10000000; // Endpoint 12 Host IN Interrupt +pub const USB_INTEP_HOST_IN_11: u32 = 0x08000000; // Endpoint 11 Host IN Interrupt +pub const USB_INTEP_HOST_IN_10: u32 = 0x04000000; // Endpoint 10 Host IN Interrupt +pub const USB_INTEP_HOST_IN_9: u32 = 0x02000000; // Endpoint 9 Host IN Interrupt +pub const USB_INTEP_HOST_IN_8: u32 = 0x01000000; // Endpoint 8 Host IN Interrupt +pub const USB_INTEP_HOST_IN_7: u32 = 0x00800000; // Endpoint 7 Host IN Interrupt +pub const USB_INTEP_HOST_IN_6: u32 = 0x00400000; // Endpoint 6 Host IN Interrupt +pub const USB_INTEP_HOST_IN_5: u32 = 0x00200000; // Endpoint 5 Host IN Interrupt +pub const USB_INTEP_HOST_IN_4: u32 = 0x00100000; // Endpoint 4 Host IN Interrupt +pub const USB_INTEP_HOST_IN_3: u32 = 0x00080000; // Endpoint 3 Host IN Interrupt +pub const USB_INTEP_HOST_IN_2: u32 = 0x00040000; // Endpoint 2 Host IN Interrupt +pub const USB_INTEP_HOST_IN_1: u32 = 0x00020000; // Endpoint 1 Host IN Interrupt +pub const USB_INTEP_DEV_OUT: u32 = 0xFFFE0000; // Device OUT Interrupts +pub const USB_INTEP_DEV_OUT_15: u32 = 0x80000000; // Endpoint 15 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_14: u32 = 0x40000000; // Endpoint 14 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_13: u32 = 0x20000000; // Endpoint 13 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_12: u32 = 0x10000000; // Endpoint 12 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_11: u32 = 0x08000000; // Endpoint 11 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_10: u32 = 0x04000000; // Endpoint 10 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_9: u32 = 0x02000000; // Endpoint 9 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_8: u32 = 0x01000000; // Endpoint 8 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_7: u32 = 0x00800000; // Endpoint 7 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_6: u32 = 0x00400000; // Endpoint 6 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_5: u32 = 0x00200000; // Endpoint 5 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_4: u32 = 0x00100000; // Endpoint 4 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_3: u32 = 0x00080000; // Endpoint 3 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_2: u32 = 0x00040000; // Endpoint 2 Device OUT Interrupt +pub const USB_INTEP_DEV_OUT_1: u32 = 0x00020000; // Endpoint 1 Device OUT Interrupt +pub const USB_INTEP_HOST_OUT: u32 = 0x0000FFFE; // Host OUT Interrupts +pub const USB_INTEP_HOST_OUT_15: u32 = 0x00008000; // Endpoint 15 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_14: u32 = 0x00004000; // Endpoint 14 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_13: u32 = 0x00002000; // Endpoint 13 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_12: u32 = 0x00001000; // Endpoint 12 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_11: u32 = 0x00000800; // Endpoint 11 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_10: u32 = 0x00000400; // Endpoint 10 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_9: u32 = 0x00000200; // Endpoint 9 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_8: u32 = 0x00000100; // Endpoint 8 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_7: u32 = 0x00000080; // Endpoint 7 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_6: u32 = 0x00000040; // Endpoint 6 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_5: u32 = 0x00000020; // Endpoint 5 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_4: u32 = 0x00000010; // Endpoint 4 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_3: u32 = 0x00000008; // Endpoint 3 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_2: u32 = 0x00000004; // Endpoint 2 Host OUT Interrupt +pub const USB_INTEP_HOST_OUT_1: u32 = 0x00000002; // Endpoint 1 Host OUT Interrupt +pub const USB_INTEP_DEV_IN: u32 = 0x0000FFFE; // Device IN Interrupts +pub const USB_INTEP_DEV_IN_15: u32 = 0x00008000; // Endpoint 15 Device IN Interrupt +pub const USB_INTEP_DEV_IN_14: u32 = 0x00004000; // Endpoint 14 Device IN Interrupt +pub const USB_INTEP_DEV_IN_13: u32 = 0x00002000; // Endpoint 13 Device IN Interrupt +pub const USB_INTEP_DEV_IN_12: u32 = 0x00001000; // Endpoint 12 Device IN Interrupt +pub const USB_INTEP_DEV_IN_11: u32 = 0x00000800; // Endpoint 11 Device IN Interrupt +pub const USB_INTEP_DEV_IN_10: u32 = 0x00000400; // Endpoint 10 Device IN Interrupt +pub const USB_INTEP_DEV_IN_9: u32 = 0x00000200; // Endpoint 9 Device IN Interrupt +pub const USB_INTEP_DEV_IN_8: u32 = 0x00000100; // Endpoint 8 Device IN Interrupt +pub const USB_INTEP_DEV_IN_7: u32 = 0x00000080; // Endpoint 7 Device IN Interrupt +pub const USB_INTEP_DEV_IN_6: u32 = 0x00000040; // Endpoint 6 Device IN Interrupt +pub const USB_INTEP_DEV_IN_5: u32 = 0x00000020; // Endpoint 5 Device IN Interrupt +pub const USB_INTEP_DEV_IN_4: u32 = 0x00000010; // Endpoint 4 Device IN Interrupt +pub const USB_INTEP_DEV_IN_3: u32 = 0x00000008; // Endpoint 3 Device IN Interrupt +pub const USB_INTEP_DEV_IN_2: u32 = 0x00000004; // Endpoint 2 Device IN Interrupt +pub const USB_INTEP_DEV_IN_1: u32 = 0x00000002; // Endpoint 1 Device IN Interrupt +pub const USB_INTEP_0: u32 = 0x00000001; // Endpoint 0 Interrupt +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +pub const USB_UNDEF_SPEED: u32 = 0x80000000; // Current speed is undefined +pub const USB_HIGH_SPEED: u32 = 0x00000002; // Current speed is High Speed +pub const USB_FULL_SPEED: u32 = 0x00000001; // Current speed is Full Speed +pub const USB_LOW_SPEED: u32 = 0x00000000; // Current speed is Low Speed +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +pub const USB_HOST_IN_STATUS: u32 = 0x114F0000; // Mask of all host IN interrupts +pub const USB_HOST_IN_PID_ERROR: u32 = 0x10000000; // Stall on this endpoint received +pub const USB_HOST_IN_NOT_COMP: u32 = 0x01000000; // Device failed to respond +pub const USB_HOST_IN_STALL: u32 = 0x00400000; // Stall on this endpoint received +pub const USB_HOST_IN_DATA_ERROR: u32 = 0x00080000; // CRC or bit-stuff error + // (ISOC Mode) +pub const USB_HOST_IN_NAK_TO: u32 = 0x00080000; // NAK received for more than the + // specified timeout period +pub const USB_HOST_IN_ERROR: u32 = 0x00040000; // Failed to communicate with a + // device +pub const USB_HOST_IN_FIFO_FULL: u32 = 0x00020000; // RX FIFO full +pub const USB_HOST_IN_PKTRDY: u32 = 0x00010000; // Data packet ready +pub const USB_HOST_OUT_STATUS: u32 = 0x000000A7; // Mask of all host OUT interrupts +pub const USB_HOST_OUT_NAK_TO: u32 = 0x00000080; // NAK received for more than the + // specified timeout period +pub const USB_HOST_OUT_NOT_COMP: u32 = 0x00000080; // No response from device + // (ISOC mode) +pub const USB_HOST_OUT_STALL: u32 = 0x00000020; // Stall on this endpoint received +pub const USB_HOST_OUT_ERROR: u32 = 0x00000004; // Failed to communicate with a + // device +pub const USB_HOST_OUT_FIFO_NE: u32 = 0x00000002; // TX FIFO is not empty +pub const USB_HOST_OUT_PKTPEND: u32 = 0x00000001; // Transmit still being transmitted +pub const USB_HOST_EP0_NAK_TO: u32 = 0x00000080; // NAK received for more than the + // specified timeout period +pub const USB_HOST_EP0_STATUS: u32 = 0x00000040; // This was a status packet +pub const USB_HOST_EP0_ERROR: u32 = 0x00000010; // Failed to communicate with a + // device +pub const USB_HOST_EP0_RX_STALL: u32 = 0x00000004; // Stall on this endpoint received +pub const USB_HOST_EP0_RXPKTRDY: u32 = 0x00000001; // Receive data packet ready +pub const USB_DEV_RX_PID_ERROR: u32 = 0x01000000; // PID error in isochronous + // transfer +pub const USB_DEV_RX_SENT_STALL: u32 = 0x00400000; // Stall was sent on this endpoint +pub const USB_DEV_RX_DATA_ERROR: u32 = 0x00080000; // CRC error on the data +pub const USB_DEV_RX_OVERRUN: u32 = 0x00040000; // OUT packet was not loaded due to + // a full FIFO +pub const USB_DEV_RX_FIFO_FULL: u32 = 0x00020000; // RX FIFO full +pub const USB_DEV_RX_PKT_RDY: u32 = 0x00010000; // Data packet ready +pub const USB_DEV_TX_NOT_COMP: u32 = 0x00000080; // Large packet split up, more data + // to come +pub const USB_DEV_TX_SENT_STALL: u32 = 0x00000020; // Stall was sent on this endpoint +pub const USB_DEV_TX_UNDERRUN: u32 = 0x00000004; // IN received with no data ready +pub const USB_DEV_TX_FIFO_NE: u32 = 0x00000002; // The TX FIFO is not empty +pub const USB_DEV_TX_TXPKTRDY: u32 = 0x00000001; // Transmit still being transmitted +pub const USB_DEV_EP0_SETUP_END: u32 = 0x00000010; // Control transaction ended before + // Data End seen +pub const USB_DEV_EP0_SENT_STALL: u32 = 0x00000004; // Stall was sent on this endpoint +pub const USB_DEV_EP0_IN_PKTPEND: u32 = 0x00000002; // Transmit data packet pending +pub const USB_DEV_EP0_OUT_PKTRDY: u32 = 0x00000001; // Receive data packet ready +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfigSet() as the ui32Flags parameter. +// +//***************************************************************************** +pub const USB_EP_AUTO_SET: u32 = 0x00000001; // Auto set feature enabled +pub const USB_EP_AUTO_REQUEST: u32 = 0x00000002; // Auto request feature enabled +pub const USB_EP_AUTO_CLEAR: u32 = 0x00000004; // Auto clear feature enabled +pub const USB_EP_DMA_MODE_0: u32 = 0x00000008; // Enable DMA access using mode 0 +pub const USB_EP_DMA_MODE_1: u32 = 0x00000010; // Enable DMA access using mode 1 +pub const USB_EP_DIS_NYET: u32 = 0x00000020; // Disable NYET response for + // high-speed Bulk and Interrupt + // endpoints in device mode. +pub const USB_EP_MODE_ISOC: u32 = 0x00000000; // Isochronous endpoint +pub const USB_EP_MODE_BULK: u32 = 0x00000100; // Bulk endpoint +pub const USB_EP_MODE_INT: u32 = 0x00000200; // Interrupt endpoint +pub const USB_EP_MODE_CTRL: u32 = 0x00000300; // Control endpoint +pub const USB_EP_MODE_MASK: u32 = 0x00000300; // Mode Mask +pub const USB_EP_SPEED_LOW: u32 = 0x00000000; // Low Speed +pub const USB_EP_SPEED_FULL: u32 = 0x00001000; // Full Speed +pub const USB_EP_SPEED_HIGH: u32 = 0x00004000; // High Speed +pub const USB_EP_HOST_IN: u32 = 0x00000000; // Host IN endpoint +pub const USB_EP_HOST_OUT: u32 = 0x00002000; // Host OUT endpoint +pub const USB_EP_DEV_IN: u32 = 0x00002000; // Device IN endpoint +pub const USB_EP_DEV_OUT: u32 = 0x00000000; // Device OUT endpoint +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrConfig() as the +// ui32Flags parameter. +// +//***************************************************************************** +pub const USB_HOST_PWRFLT_LOW: u32 = 0x00000010; +pub const USB_HOST_PWRFLT_HIGH: u32 = 0x00000030; +pub const USB_HOST_PWRFLT_EP_NONE: u32 = 0x00000000; +pub const USB_HOST_PWRFLT_EP_TRI: u32 = 0x00000140; +pub const USB_HOST_PWRFLT_EP_LOW: u32 = 0x00000240; +pub const USB_HOST_PWRFLT_EP_HIGH: u32 = 0x00000340; +pub const USB_HOST_PWREN_MAN_LOW: u32 = 0x00000000; +pub const USB_HOST_PWREN_MAN_HIGH: u32 = 0x00000001; +pub const USB_HOST_PWREN_AUTOLOW: u32 = 0x00000002; +pub const USB_HOST_PWREN_AUTOHIGH: u32 = 0x00000003; +pub const USB_HOST_PWREN_FILTER: u32 = 0x00010000; +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// USBHostLPMConfig() function in the ui32Config parameter. +// +//***************************************************************************** +pub const USB_HOST_LPM_RMTWAKE: u32 = 0x00000100; +pub const USB_HOST_LPM_L1: u32 = 0x00000001; +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// USBDevLPMConfig() function in the ui32Config parameter. +// +//***************************************************************************** +pub const USB_DEV_LPM_NAK: u32 = 0x00000010; +pub const USB_DEV_LPM_NONE: u32 = 0x00000000; +pub const USB_DEV_LPM_EN: u32 = 0x0000000c; +pub const USB_DEV_LPM_EXTONLY: u32 = 0x00000004; +//***************************************************************************** +// +// The following are the valid values that are returned from the +// USBLPMLinkStateGet() function. +// +//***************************************************************************** +pub const USB_DEV_LPM_LS_RMTWAKE: u32 = 0x00000100; +pub const USB_DEV_LPM_LS_L1: u32 = 0x00000001; +//***************************************************************************** +// +// The following are the valid values that are passed to the USBLPMIntEnable() +// or USBLPMIntDisable() functions or are returned from the USBLPMIntStatus() +// function. +// +//***************************************************************************** +pub const USB_INTLPM_ERROR: u32 = 0x00000020; +pub const USB_INTLPM_RESUME: u32 = 0x00000010; +pub const USB_INTLPM_INCOMPLETE: u32 = 0x00000008; +pub const USB_INTLPM_ACK: u32 = 0x00000004; +pub const USB_INTLPM_NYET: u32 = 0x00000002; +pub const USB_INTLPM_STALL: u32 = 0x00000001; +//***************************************************************************** +// +// The following are the valid values that are passed to the USBClockEnable() +// functions. +// +//***************************************************************************** +pub const USB_CLOCK_INTERNAL: u32 = 0x00000200; +pub const USB_CLOCK_EXTERNAL: u32 = 0x00000300; +//***************************************************************************** +// +// The configuration options used with the USBULPIConfig() API. +// +//***************************************************************************** +pub const USB_ULPI_EXTVBUS: u32 = 0x00000001; +pub const USB_ULPI_EXTVBUS_IND: u32 = 0x00000002; +//***************************************************************************** +// +// The following are special values that can be passed to +// USBHostEndpointConfig() as the ui32NAKPollInterval parameter. +// +//***************************************************************************** +pub const MAX_NAK_LIMIT: u32 = 31; // Maximum NAK interval +pub const DISABLE_NAK_LIMIT: u32 = 0; // No NAK timeouts +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +pub const MAX_PACKET_SIZE_EP0: u32 = 64; +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +pub const USB_EP_0: u32 = 0x00000000; // Endpoint 0 +pub const USB_EP_1: u32 = 0x00000010; // Endpoint 1 +pub const USB_EP_2: u32 = 0x00000020; // Endpoint 2 +pub const USB_EP_3: u32 = 0x00000030; // Endpoint 3 +pub const USB_EP_4: u32 = 0x00000040; // Endpoint 4 +pub const USB_EP_5: u32 = 0x00000050; // Endpoint 5 +pub const USB_EP_6: u32 = 0x00000060; // Endpoint 6 +pub const USB_EP_7: u32 = 0x00000070; // Endpoint 7 +pub const NUM_USB_EP: u32 = 8; // Number of supported endpoints +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +//pub const IndexToUSBEP(x): u32 = ((x); +//pub const USBEPToIndex(x): u32 = ((x); +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +pub const USB_FIFO_SZ_8: u32 = 0x00000000; // 8 byte FIFO +pub const USB_FIFO_SZ_16: u32 = 0x00000001; // 16 byte FIFO +pub const USB_FIFO_SZ_32: u32 = 0x00000002; // 32 byte FIFO +pub const USB_FIFO_SZ_64: u32 = 0x00000003; // 64 byte FIFO +pub const USB_FIFO_SZ_128: u32 = 0x00000004; // 128 byte FIFO +pub const USB_FIFO_SZ_256: u32 = 0x00000005; // 256 byte FIFO +pub const USB_FIFO_SZ_512: u32 = 0x00000006; // 512 byte FIFO +pub const USB_FIFO_SZ_1024: u32 = 0x00000007; // 1024 byte FIFO +pub const USB_FIFO_SZ_2048: u32 = 0x00000008; // 2048 byte FIFO +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +//pub const USBFIFOSizeToBytes(x): u32 = (8; +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ui32TransType parameter. +// +//***************************************************************************** +pub const USB_TRANS_OUT: u32 = 0x00000102; // Normal OUT transaction +pub const USB_TRANS_IN: u32 = 0x00000102; // Normal IN transaction +pub const USB_TRANS_IN_LAST: u32 = 0x0000010a; // Final IN transaction (for + // endpoint 0 in device mode) +pub const USB_TRANS_SETUP: u32 = 0x0000110a; // Setup transaction (for endpoint + // 0) +pub const USB_TRANS_STATUS: u32 = 0x00000142; // Status transaction (for endpoint + // 0) +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +pub const USB_DUAL_MODE_HOST: u32 = 0x00000001; // Dual mode controller is in Host + // mode. +pub const USB_DUAL_MODE_DEVICE: u32 = 0x00000081; // Dual mode controller is in + // Device mode. +pub const USB_DUAL_MODE_NONE: u32 = 0x00000080; // Dual mode controller mode is not + // set. +pub const USB_OTG_MODE_ASIDE_HOST: u32 = 0x0000001d; // OTG controller on the A side of + // the cable. +pub const USB_OTG_MODE_ASIDE_NPWR: u32 = 0x00000001; // OTG controller on the A side of + // the cable. +pub const USB_OTG_MODE_ASIDE_SESS: u32 = 0x00000009; // OTG controller on the A side of + // the cable Session Valid. +pub const USB_OTG_MODE_ASIDE_AVAL: u32 = 0x00000011; // OTG controller on the A side of + // the cable A valid. +pub const USB_OTG_MODE_ASIDE_DEV: u32 = 0x00000019; // OTG controller on the A side of + // the cable. +pub const USB_OTG_MODE_BSIDE_HOST: u32 = 0x0000009d; // OTG controller on the B side of + // the cable. +pub const USB_OTG_MODE_BSIDE_DEV: u32 = 0x00000099; // OTG controller on the B side of + // the cable. +pub const USB_OTG_MODE_BSIDE_NPWR: u32 = 0x00000081; // OTG controller on the B side of + // the cable. +pub const USB_OTG_MODE_NONE: u32 = 0x00000080; // OTG controller mode is not set. +//***************************************************************************** +// +// The values for the USBDMAChannelIntEnable() and USBDMAChannelIntStatus() +// APIs. +// +//***************************************************************************** +pub const USB_DMA_INT_CH8: u32 = 0x00000080; +pub const USB_DMA_INT_CH7: u32 = 0x00000040; +pub const USB_DMA_INT_CH6: u32 = 0x00000020; +pub const USB_DMA_INT_CH5: u32 = 0x00000010; +pub const USB_DMA_INT_CH4: u32 = 0x00000008; +pub const USB_DMA_INT_CH3: u32 = 0x00000004; +pub const USB_DMA_INT_CH2: u32 = 0x00000002; +pub const USB_DMA_INT_CH1: u32 = 0x00000001; +//***************************************************************************** +// +// The values for the USBDMAChannelStatus() API. +// +//***************************************************************************** +pub const USB_DMA_STATUS_ERROR: u32 = 0x00000100; +//***************************************************************************** +// +// The valid return values for the USBControllerVersion() API. +// +//***************************************************************************** +pub const USB_CONTROLLER_VER_0: u32 = 0x00000000; // This is for Blizzard class + // devices. +pub const USB_CONTROLLER_VER_1: u32 = 0x00000001; // This is for Snowflake class + // devices. +//***************************************************************************** +// +// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or +// USBDMAChannelConfig(). +// +//***************************************************************************** +pub const USB_DMA_CFG_BURST_NONE: u32 = 0x00000000; +pub const USB_DMA_CFG_BURST_4: u32 = 0x00000200; +pub const USB_DMA_CFG_BURST_8: u32 = 0x00000400; +pub const USB_DMA_CFG_BURST_16: u32 = 0x00000600; +pub const USB_DMA_CFG_INT_EN: u32 = 0x00000008; +pub const USB_DMA_CFG_MODE_0: u32 = 0x00000000; +pub const USB_DMA_CFG_MODE_1: u32 = 0x00000004; +pub const USB_DMA_CFG_DIR_RX: u32 = 0x00000000; +pub const USB_DMA_CFG_DIR_TX: u32 = 0x00000002; +pub const USB_DMA_CFG_EN: u32 = 0x00000001; +//***************************************************************************** +// +// The following are values that can be passed to USBModeConfig() as the +// ui3Mode parameter. +// +//***************************************************************************** +pub const USB_MODE_HOST_VBUS: u32 = 0x00000004; +pub const USB_MODE_HOST: u32 = 0x00000002; +pub const USB_MODE_DEV_VBUS: u32 = 0x00000005; +pub const USB_MODE_DEV: u32 = 0x00000003; +pub const USB_MODE_OTG: u32 = 0x00000000; +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +//***************************************************************************** +// +// The type of interrupt that can be generated by the watchdog. +// +//***************************************************************************** +pub const WATCHDOG_INT_TYPE_INT: u32 = 0x00000000; +pub const WATCHDOG_INT_TYPE_NMI: u32 = 0x00000004; +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** + +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of the device. +// +// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package. +// +//***************************************************************************** +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +pub const FLASH_BASE: u32 = 0x00000000; // FLASH memory +pub const SRAM_BASE: u32 = 0x20000000; // SRAM memory +pub const WATCHDOG0_BASE: u32 = 0x40000000; // Watchdog0 +pub const WATCHDOG1_BASE: u32 = 0x40001000; // Watchdog1 +pub const GPIO_PORTA_BASE: u32 = 0x40004000; // GPIO Port A +pub const GPIO_PORTB_BASE: u32 = 0x40005000; // GPIO Port B +pub const GPIO_PORTC_BASE: u32 = 0x40006000; // GPIO Port C +pub const GPIO_PORTD_BASE: u32 = 0x40007000; // GPIO Port D +pub const SSI0_BASE: u32 = 0x40008000; // SSI0 +pub const SSI1_BASE: u32 = 0x40009000; // SSI1 +pub const SSI2_BASE: u32 = 0x4000A000; // SSI2 +pub const SSI3_BASE: u32 = 0x4000B000; // SSI3 +pub const UART0_BASE: u32 = 0x4000C000; // UART0 +pub const UART1_BASE: u32 = 0x4000D000; // UART1 +pub const UART2_BASE: u32 = 0x4000E000; // UART2 +pub const UART3_BASE: u32 = 0x4000F000; // UART3 +pub const UART4_BASE: u32 = 0x40010000; // UART4 +pub const UART5_BASE: u32 = 0x40011000; // UART5 +pub const UART6_BASE: u32 = 0x40012000; // UART6 +pub const UART7_BASE: u32 = 0x40013000; // UART7 +pub const I2C0_BASE: u32 = 0x40020000; // I2C0 +pub const I2C1_BASE: u32 = 0x40021000; // I2C1 +pub const I2C2_BASE: u32 = 0x40022000; // I2C2 +pub const I2C3_BASE: u32 = 0x40023000; // I2C3 +pub const GPIO_PORTE_BASE: u32 = 0x40024000; // GPIO Port E +pub const GPIO_PORTF_BASE: u32 = 0x40025000; // GPIO Port F +pub const GPIO_PORTG_BASE: u32 = 0x40026000; // GPIO Port G +pub const GPIO_PORTH_BASE: u32 = 0x40027000; // GPIO Port H +pub const PWM0_BASE: u32 = 0x40028000; // Pulse Width Modulator (PWM) +pub const PWM1_BASE: u32 = 0x40029000; // Pulse Width Modulator (PWM) +pub const QEI0_BASE: u32 = 0x4002C000; // QEI0 +pub const QEI1_BASE: u32 = 0x4002D000; // QEI1 +pub const TIMER0_BASE: u32 = 0x40030000; // Timer0 +pub const TIMER1_BASE: u32 = 0x40031000; // Timer1 +pub const TIMER2_BASE: u32 = 0x40032000; // Timer2 +pub const TIMER3_BASE: u32 = 0x40033000; // Timer3 +pub const TIMER4_BASE: u32 = 0x40034000; // Timer4 +pub const TIMER5_BASE: u32 = 0x40035000; // Timer5 +pub const WTIMER0_BASE: u32 = 0x40036000; // Wide Timer0 +pub const WTIMER1_BASE: u32 = 0x40037000; // Wide Timer1 +pub const ADC0_BASE: u32 = 0x40038000; // ADC0 +pub const ADC1_BASE: u32 = 0x40039000; // ADC1 +pub const COMP_BASE: u32 = 0x4003C000; // Analog comparators +pub const GPIO_PORTJ_BASE: u32 = 0x4003D000; // GPIO Port J +pub const CAN0_BASE: u32 = 0x40040000; // CAN0 +pub const CAN1_BASE: u32 = 0x40041000; // CAN1 +pub const WTIMER2_BASE: u32 = 0x4004C000; // Wide Timer2 +pub const WTIMER3_BASE: u32 = 0x4004D000; // Wide Timer3 +pub const WTIMER4_BASE: u32 = 0x4004E000; // Wide Timer4 +pub const WTIMER5_BASE: u32 = 0x4004F000; // Wide Timer5 +pub const USB0_BASE: u32 = 0x40050000; // USB 0 Controller +pub const GPIO_PORTA_AHB_BASE: u32 = 0x40058000; // GPIO Port A (high speed) +pub const GPIO_PORTB_AHB_BASE: u32 = 0x40059000; // GPIO Port B (high speed) +pub const GPIO_PORTC_AHB_BASE: u32 = 0x4005A000; // GPIO Port C (high speed) +pub const GPIO_PORTD_AHB_BASE: u32 = 0x4005B000; // GPIO Port D (high speed) +pub const GPIO_PORTE_AHB_BASE: u32 = 0x4005C000; // GPIO Port E (high speed) +pub const GPIO_PORTF_AHB_BASE: u32 = 0x4005D000; // GPIO Port F (high speed) +pub const GPIO_PORTG_AHB_BASE: u32 = 0x4005E000; // GPIO Port G (high speed) +pub const GPIO_PORTH_AHB_BASE: u32 = 0x4005F000; // GPIO Port H (high speed) +pub const GPIO_PORTJ_AHB_BASE: u32 = 0x40060000; // GPIO Port J (high speed) +pub const GPIO_PORTK_BASE: u32 = 0x40061000; // GPIO Port K +pub const GPIO_PORTL_BASE: u32 = 0x40062000; // GPIO Port L +pub const GPIO_PORTM_BASE: u32 = 0x40063000; // GPIO Port M +pub const GPIO_PORTN_BASE: u32 = 0x40064000; // GPIO Port N +pub const GPIO_PORTP_BASE: u32 = 0x40065000; // GPIO Port P +pub const GPIO_PORTQ_BASE: u32 = 0x40066000; // GPIO Port Q +pub const GPIO_PORTR_BASE: u32 = 0x40067000; // General-Purpose Input/Outputs + // (GPIOs) +pub const GPIO_PORTS_BASE: u32 = 0x40068000; // General-Purpose Input/Outputs + // (GPIOs) +pub const GPIO_PORTT_BASE: u32 = 0x40069000; // General-Purpose Input/Outputs + // (GPIOs) +pub const EEPROM_BASE: u32 = 0x400AF000; // EEPROM memory +pub const ONEWIRE0_BASE: u32 = 0x400B6000; // 1-Wire Master Module +pub const I2C8_BASE: u32 = 0x400B8000; // I2C8 +pub const I2C9_BASE: u32 = 0x400B9000; // I2C9 +pub const I2C4_BASE: u32 = 0x400C0000; // I2C4 +pub const I2C5_BASE: u32 = 0x400C1000; // I2C5 +pub const I2C6_BASE: u32 = 0x400C2000; // I2C6 +pub const I2C7_BASE: u32 = 0x400C3000; // I2C7 +pub const EPI0_BASE: u32 = 0x400D0000; // EPI0 +pub const TIMER6_BASE: u32 = 0x400E0000; // General-Purpose Timers +pub const TIMER7_BASE: u32 = 0x400E1000; // General-Purpose Timers +pub const EMAC0_BASE: u32 = 0x400EC000; // Ethernet Controller +pub const SYSEXC_BASE: u32 = 0x400F9000; // System Exception Module +pub const HIB_BASE: u32 = 0x400FC000; // Hibernation Module +pub const FLASH_CTRL_BASE: u32 = 0x400FD000; // FLASH Controller +pub const SYSCTL_BASE: u32 = 0x400FE000; // System Control +pub const UDMA_BASE: u32 = 0x400FF000; // uDMA Controller +pub const CCM0_BASE: u32 = 0x44030000; // Cyclical Redundancy Check (CRC) +pub const SHAMD5_BASE: u32 = 0x44034000; // SHA/MD5 Accelerator +pub const AES_BASE: u32 = 0x44036000; // Advance Encryption + // Hardware-Accelerated Module +pub const DES_BASE: u32 = 0x44038000; // Data Encryption Standard + // Accelerator (DES) +pub const LCD0_BASE: u32 = 0x44050000; // LCD Controller +pub const ITM_BASE: u32 = 0xE0000000; // Instrumentation Trace Macrocell +pub const DWT_BASE: u32 = 0xE0001000; // Data Watchpoint and Trace +pub const FPB_BASE: u32 = 0xE0002000; // FLASH Patch and Breakpoint +pub const NVIC_BASE: u32 = 0xE000E000; // Nested Vectored Interrupt Ctrl +pub const TPIU_BASE: u32 = 0xE0040000; // Trace Port Interface Unit diff --git a/src/uart.rs b/src/uart.rs new file mode 100644 index 0000000..8693ae1 --- /dev/null +++ b/src/uart.rs @@ -0,0 +1,236 @@ + + +pub fn UARTParityModeSetWrap(ui32Base: u32, ui32Parity: u32) { + unsafe { UARTParityModeSet(ui32Base, ui32Parity); } +} + +pub fn UARTParityModeGetWrap(ui32Base: u32) -> u32 { + unsafe { UARTParityModeGet(ui32Base) } +} + +pub fn UARTFIFOLevelSetWrap(ui32Base: u32, ui32TxLevel: u32, ui32RxLevel: u32) { + unsafe { UARTFIFOLevelSet(ui32Base, ui32TxLevel, ui32RxLevel); } +} + +pub fn UARTFIFOLevelGetWrap(ui32Base: u32, pui32TxLevel: *const u32, pui32RxLevel: *const u32) { + unsafe { UARTFIFOLevelGet(ui32Base, pui32TxLevel, pui32RxLevel); } +} + +pub fn UARTConfigSetExpClkWrap(ui32Base: u32, ui32UARTClk: u32, ui32Baud: u32, ui32Config: u32) { + unsafe { UARTConfigSetExpClk(ui32Base, ui32UARTClk, ui32Baud, ui32Config); } +} + +pub fn UARTConfigGetExpClkWrap(ui32Base: u32, ui32UARTClk: u32, pui32Baud: *const u32, pui32Config: *const u32) { + unsafe { UARTConfigGetExpClk(ui32Base, ui32UARTClk, pui32Baud, pui32Config); } +} + +pub fn UARTEnableWrap(ui32Base: u32) { + unsafe { UARTEnable(ui32Base); } +} + +pub fn UARTDisableWrap(ui32Base: u32) { + unsafe { UARTDisable(ui32Base); } +} + +pub fn UARTFIFOEnableWrap(ui32Base: u32) { + unsafe { UARTFIFOEnable(ui32Base); } +} + +pub fn UARTFIFODisableWrap(ui32Base: u32) { + unsafe { UARTFIFODisable(ui32Base); } +} + +pub fn UARTEnableSIRWrap(ui32Base: u32, bLowPower: bool) { + unsafe { UARTEnableSIR(ui32Base, bLowPower); } +} + +pub fn UARTDisableSIRWrap(ui32Base: u32) { + unsafe { UARTDisableSIR(ui32Base); } +} + +pub fn UARTCharsAvailWrap(ui32Base: u32) -> bool { + unsafe { UARTCharsAvail(ui32Base) } +} + +pub fn UARTSpaceAvailWrap(ui32Base: u32) -> bool { + unsafe { UARTSpaceAvail(ui32Base) } +} + +pub fn UARTCharGetNonBlockingWrap(ui32Base: u32) -> i32 { + unsafe { UARTCharGetNonBlocking(ui32Base) } +} + +pub fn UARTCharGetWrap(ui32Base: u32) -> i32 { + unsafe { UARTCharGet(ui32Base) } +} + +pub fn UARTCharPutNonBlockingWrap(ui32Base: u32) -> bool { + unsafe { UARTCharPutNonBlocking(ui32Base) } +} + +pub fn UARTCharPutWrap(ui32Base: u32) { + unsafe { UARTCharPut(ui32Base); } +} + +pub fn UARTBreakCtlWrap(ui32Base: u32, bBreakState: bool) { + unsafe { UARTBreakCtl(ui32Base, bBreakState); } +} + +pub fn UARTBusyWrap(ui32Base: u32) -> bool { + unsafe { UARTBusy(ui32Base) } +} + +pub fn UARTIntUnregisterWrap(ui32Base: u32) { + unsafe { UARTIntUnregister(ui32Base); } +} + +pub fn UARTIntEnableWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { UARTIntEnable(ui32Base, ui32IntFlags); } +} + +pub fn UARTIntDisableWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { UARTIntDisable(ui32Base, ui32IntFlags); } +} + +pub fn UARTIntStatusWrap(ui32Base: u32, bMasked: bool) -> u32 { + unsafe { UARTIntStatus(ui32Base, bMasked) } +} + +pub fn UARTIntClearWrap(ui32Base: u32, ui32IntFlags: u32) { + unsafe { UARTIntClear(ui32Base, ui32IntFlags); } +} + +pub fn UARTDMAEnableWrap(ui32Base: u32, ui32DMAFlags: u32) { + unsafe { UARTDMAEnable(ui32Base, ui32DMAFlags); } +} + +pub fn UARTDMADisableWrap(ui32Base: u32, ui32DMAFlags: u32) { + unsafe { UARTDMADisable(ui32Base, ui32DMAFlags); } +} + +pub fn UARTRxErrorGetWrap(ui32Base: u32) -> u32 { + unsafe { UARTRxErrorGet(ui32Base) } +} + +pub fn UARTRxErrorClearWrap(ui32Base: u32) { + unsafe { UARTRxErrorClear(ui32Base); } +} + +pub fn UARTSmartCardEnableWrap(ui32Base: u32) { + unsafe { UARTSmartCardEnable(ui32Base); } +} + +pub fn UARTSmartCardDisableWrap(ui32Base: u32) { + unsafe { UARTSmartCardDisable(ui32Base); } +} + +pub fn UARTModemControlSetWrap(ui32Base: u32, ui32Control: u32) { + unsafe { UARTModemControlSet(ui32Base, ui32Control); } +} + +pub fn UARTModemControlClearWrap(ui32Base: u32, ui32Control: u32) { + unsafe { UARTModemControlClear(ui32Base, ui32Control); } +} + +pub fn UARTModemControlGetWrap(ui32Base: u32) -> u32 { + unsafe { UARTModemControlGet(ui32Base) } +} + +pub fn UARTModemStatusGetWrap(ui32Base: u32) -> u32 { + unsafe { UARTModemStatusGet(ui32Base) } +} + +pub fn UARTFlowControlSetWrap(ui32Base: u32, ui32Mode: u32) { + unsafe { UARTFlowControlSet(ui32Base, ui32Mode); } +} + +pub fn UARTFlowControlGetWrap(ui32Base: u32) -> u32 { + unsafe { UARTFlowControlGet(ui32Base) } +} + +pub fn UARTTxIntModeSetWrap(ui32Base: u32, ui32Mode: u32) { + unsafe { UARTTxIntModeSet(ui32Base, ui32Mode); } +} + +pub fn UARTTxIntModeGetWrap(ui32Base: u32) -> u32 { + unsafe { UARTTxIntModeGet(ui32Base) } +} + +pub fn UARTClockSourceSetWrap(ui32Base: u32, ui32Source: u32) { + unsafe { UARTClockSourceSet(ui32Base, ui32Source); } +} + +pub fn UARTClockSourceGetWrap(ui32Base: u32) -> u32 { + unsafe { UARTClockSourceGet(ui32Base) } +} + +pub fn UART9BitEnableWrap(ui32Base: u32) { + unsafe { UART9BitEnable(ui32Base); } +} + +pub fn UART9BitDisableWrap(ui32Base: u32) { + unsafe { UART9BitDisable(ui32Base); } +} + +pub fn UART9BitAddrSetWrap(ui32Base: u32, ui8Addr: u8, ui8Mask: u8) { + unsafe { UART9BitAddrSet(ui32Base, ui8Addr, ui8Mask); } +} + +pub fn UART9BitAddrSendWrap(ui32Base: u32, ui8Addr: u8) { + unsafe { UART9BitAddrSend(ui32Base, ui8Addr); } +} + +pub fn UARTLoopbackEnableWrap(ui32Base: u32) { + unsafe { UARTLoopbackEnable(ui32Base); } +} + +#[link(name="uart", kind="static")] +extern "C" { + pub fn UARTParityModeSet(ui32Base: u32, ui32Parity: u32); + pub fn UARTParityModeGet(ui32Base: u32) -> u32; + pub fn UARTFIFOLevelSet(ui32Base: u32, ui32TxLevel: u32, ui32RxLevel: u32); + pub fn UARTFIFOLevelGet(ui32Base: u32, pui32TxLevel: *const u32, pui32RxLevel: *const u32); + pub fn UARTConfigSetExpClk(ui32Base: u32, ui32UARTClk: u32, ui32Baud: u32, ui32Config: u32); + pub fn UARTConfigGetExpClk(ui32Base: u32, ui32UARTClk: u32, pui32Baud: *const u32, pui32Config: *const u32); + pub fn UARTEnable(ui32Base: u32); + pub fn UARTDisable(ui32Base: u32); + pub fn UARTFIFOEnable(ui32Base: u32); + pub fn UARTFIFODisable(ui32Base: u32); + pub fn UARTEnableSIR(ui32Base: u32, bLowPower: bool); + pub fn UARTDisableSIR(ui32Base: u32); + pub fn UARTCharsAvail(ui32Base: u32) -> bool; + pub fn UARTSpaceAvail(ui32Base: u32) -> bool; + pub fn UARTCharGetNonBlocking(ui32Base: u32) -> i32; + pub fn UARTCharGet(ui32Base: u32) -> i32; + pub fn UARTCharPutNonBlocking(ui32Base: u32) -> bool; + pub fn UARTCharPut(ui32Base: u32); + pub fn UARTBreakCtl(ui32Base: u32, bBreakState: bool); + pub fn UARTBusy(ui32Base: u32) -> bool; + pub fn UARTIntRegister(ui32Base: u32, pfnHandler: Option ); + pub fn UARTIntUnregister(ui32Base: u32); + pub fn UARTIntEnable(ui32Base: u32, ui32IntFlags: u32); + pub fn UARTIntDisable(ui32Base: u32, ui32IntFlags: u32); + pub fn UARTIntStatus(ui32Base: u32, bMasked: bool) -> u32; + pub fn UARTIntClear(ui32Base: u32, ui32IntFlags: u32); + pub fn UARTDMAEnable(ui32Base: u32, ui32DMAFlags: u32); + pub fn UARTDMADisable(ui32Base: u32, ui32DMAFlags: u32); + pub fn UARTRxErrorGet(ui32Base: u32) -> u32; + pub fn UARTRxErrorClear(ui32Base: u32); + pub fn UARTSmartCardEnable(ui32Base: u32); + pub fn UARTSmartCardDisable(ui32Base: u32); + pub fn UARTModemControlSet(ui32Base: u32, ui32Control: u32); + pub fn UARTModemControlClear(ui32Base: u32, ui32Control: u32); + pub fn UARTModemControlGet(ui32Base: u32) -> u32; + pub fn UARTModemStatusGet(ui32Base: u32) -> u32; + pub fn UARTFlowControlSet(ui32Base: u32, ui32Mode: u32); + pub fn UARTFlowControlGet(ui32Base: u32) -> u32; + pub fn UARTTxIntModeSet(ui32Base: u32, ui32Mode: u32); + pub fn UARTTxIntModeGet(ui32Base: u32) -> u32; + pub fn UARTClockSourceSet(ui32Base: u32, ui32Source: u32); + pub fn UARTClockSourceGet(ui32Base: u32) -> u32; + pub fn UART9BitEnable(ui32Base: u32); + pub fn UART9BitDisable(ui32Base: u32); + pub fn UART9BitAddrSet(ui32Base: u32, ui8Addr: u8, ui8Mask: u8); + pub fn UART9BitAddrSend(ui32Base: u32, ui8Addr: u8); + pub fn UARTLoopbackEnable(ui32Base: u32); +} \ No newline at end of file diff --git a/sw_crc.o b/sw_crc.o new file mode 100644 index 0000000..54e3fa2 Binary files /dev/null and b/sw_crc.o differ diff --git a/sysexc.o b/sysexc.o new file mode 100644 index 0000000..3f039c1 Binary files /dev/null and b/sysexc.o differ diff --git a/target/.rustc_info.json b/target/.rustc_info.json new file mode 100644 index 0000000..6791cf4 --- /dev/null +++ b/target/.rustc_info.json @@ -0,0 +1 @@ +{"rustc_fingerprint":1827681471097140717,"outputs":{"8021068424851416819":{"success":true,"status":"","code":0,"stdout":"___\nlib___.rlib\nlib___.a\nC:\\Users\\wang\\.rustup\\toolchains\\stable-x86_64-pc-windows-msvc\noff\n___\ndebug_assertions\npanic=\"abort\"\nproc_macro\ntarget_abi=\"eabihf\"\ntarget_arch=\"arm\"\ntarget_endian=\"little\"\ntarget_env=\"\"\ntarget_has_atomic=\"16\"\ntarget_has_atomic=\"32\"\ntarget_has_atomic=\"8\"\ntarget_has_atomic=\"ptr\"\ntarget_os=\"none\"\ntarget_pointer_width=\"32\"\ntarget_vendor=\"unknown\"\n","stderr":"warning: dropping unsupported crate type `dylib` for target `thumbv7em-none-eabihf`\n\nwarning: dropping unsupported crate type `cdylib` for target `thumbv7em-none-eabihf`\n\nwarning: dropping unsupported crate type `proc-macro` for target `thumbv7em-none-eabihf`\n\nwarning: 3 warnings emitted\n\n"},"4614504638168534921":{"success":true,"status":"","code":0,"stdout":"rustc 1.82.0 (f6e511eec 2024-10-15)\nbinary: rustc\ncommit-hash: f6e511eec7342f59a25f7c0534f1dbea00d01b14\ncommit-date: 2024-10-15\nhost: x86_64-pc-windows-msvc\nrelease: 1.82.0\nLLVM version: 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b/target/thumbv7em-none-eabihf/debug/.fingerprint/tm4c123x-57403112b8347914/lib-tm4c123x.json new file mode 100644 index 0000000..121a711 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/.fingerprint/tm4c123x-57403112b8347914/lib-tm4c123x.json @@ -0,0 +1 @@ +{"rustc":8148778215749587923,"features":"[\"cortex-m-rt\", \"rt\"]","declared_features":"[\"cortex-m-rt\", \"rt\"]","target":10190475943270779398,"profile":16690480377348987070,"path":16939468879760525838,"deps":[[1577901321233636205,"build_script_build",false,14949271084917635761],[10950290660039784454,"cortex_m_rt",false,8190367436378421126],[11107328738283231737,"vcell",false,5654437927207893746],[11354050516895600027,"cortex_m",false,10562768756269357730]],"local":[{"CheckDepInfo":{"dep_info":"thumbv7em-none-eabihf\\debug\\.fingerprint\\tm4c123x-57403112b8347914\\dep-lib-tm4c123x"}}],"rustflags":["-C","link-arg=-Tlink.x"],"metadata":10127068865695775732,"config":2202906307356721367,"compile_kind":18320266955371171910} \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/dep-lib-vcell b/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/dep-lib-vcell new file mode 100644 index 0000000..1b1cb4d Binary files /dev/null and b/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/dep-lib-vcell differ diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/invoked.timestamp b/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/invoked.timestamp new file mode 100644 index 0000000..e00328d --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/lib-vcell b/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/lib-vcell new file mode 100644 index 0000000..4c71053 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/lib-vcell @@ -0,0 +1 @@ +f2fab8175699784e \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/lib-vcell.json b/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/lib-vcell.json new file mode 100644 index 0000000..d701196 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/.fingerprint/vcell-94e6bec999ec8fdb/lib-vcell.json @@ -0,0 +1 @@ +{"rustc":8148778215749587923,"features":"[]","declared_features":"[\"const-fn\"]","target":11918635725550840930,"profile":16690480377348987070,"path":10639754530455522992,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"thumbv7em-none-eabihf\\debug\\.fingerprint\\vcell-94e6bec999ec8fdb\\dep-lib-vcell"}}],"rustflags":["-C","link-arg=-Tlink.x"],"metadata":13577594567583942782,"config":2202906307356721367,"compile_kind":18320266955371171910} \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/dep-lib-void b/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/dep-lib-void new file mode 100644 index 0000000..1b1cb4d Binary files /dev/null and b/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/dep-lib-void differ diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/invoked.timestamp b/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/invoked.timestamp new file mode 100644 index 0000000..e00328d --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/lib-void b/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/lib-void new file mode 100644 index 0000000..34165de --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/lib-void @@ -0,0 +1 @@ +68d788ed057d677f \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/lib-void.json b/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/lib-void.json new file mode 100644 index 0000000..a4af968 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/.fingerprint/void-58b350b94d75ef64/lib-void.json @@ -0,0 +1 @@ +{"rustc":8148778215749587923,"features":"[]","declared_features":"[\"default\", \"std\"]","target":6911971464560117640,"profile":16690480377348987070,"path":10087767471640737657,"deps":[],"local":[{"CheckDepInfo":{"dep_info":"thumbv7em-none-eabihf\\debug\\.fingerprint\\void-58b350b94d75ef64\\dep-lib-void"}}],"rustflags":["-C","link-arg=-Tlink.x"],"metadata":12916841795283096440,"config":2202906307356721367,"compile_kind":18320266955371171910} \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/dep-lib-volatile_register b/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/dep-lib-volatile_register new file mode 100644 index 0000000..1b1cb4d Binary files /dev/null and b/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/dep-lib-volatile_register differ diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/invoked.timestamp b/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/invoked.timestamp new file mode 100644 index 0000000..e00328d --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/lib-volatile_register b/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/lib-volatile_register new file mode 100644 index 0000000..3e01631 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/lib-volatile_register @@ -0,0 +1 @@ +a0ff4ea4603796de \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/lib-volatile_register.json b/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/lib-volatile_register.json new file mode 100644 index 0000000..1e66d50 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/.fingerprint/volatile-register-dd70ea60f0a0083b/lib-volatile_register.json @@ -0,0 +1 @@ +{"rustc":8148778215749587923,"features":"[]","declared_features":"[]","target":11121542377313385127,"profile":16690480377348987070,"path":13244677295519632556,"deps":[[11107328738283231737,"vcell",false,5654437927207893746]],"local":[{"CheckDepInfo":{"dep_info":"thumbv7em-none-eabihf\\debug\\.fingerprint\\volatile-register-dd70ea60f0a0083b\\dep-lib-volatile_register"}}],"rustflags":["-C","link-arg=-Tlink.x"],"metadata":10117672783988140343,"config":2202906307356721367,"compile_kind":18320266955371171910} \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/build/bare-metal-c786d4cc844f86a8/invoked.timestamp b/target/thumbv7em-none-eabihf/debug/build/bare-metal-c786d4cc844f86a8/invoked.timestamp new file mode 100644 index 0000000..e00328d --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/bare-metal-c786d4cc844f86a8/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/build/bare-metal-c786d4cc844f86a8/output b/target/thumbv7em-none-eabihf/debug/build/bare-metal-c786d4cc844f86a8/output new file mode 100644 index 0000000..e69de29 diff --git a/target/thumbv7em-none-eabihf/debug/build/bare-metal-c786d4cc844f86a8/root-output b/target/thumbv7em-none-eabihf/debug/build/bare-metal-c786d4cc844f86a8/root-output new file mode 100644 index 0000000..f3ba6c5 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/bare-metal-c786d4cc844f86a8/root-output @@ -0,0 +1 @@ +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\build\bare-metal-c786d4cc844f86a8\out \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/build/bare-metal-c786d4cc844f86a8/stderr b/target/thumbv7em-none-eabihf/debug/build/bare-metal-c786d4cc844f86a8/stderr new file mode 100644 index 0000000..e69de29 diff --git a/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/invoked.timestamp b/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/invoked.timestamp new file mode 100644 index 0000000..e00328d --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/out/libcortex-m.a b/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/out/libcortex-m.a new file mode 100644 index 0000000..cf91a7a Binary files /dev/null and b/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/out/libcortex-m.a differ diff --git a/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/output b/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/output new file mode 100644 index 0000000..f4a26f5 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/output @@ -0,0 +1,6 @@ +cargo:rustc-link-lib=static=cortex-m +cargo:rustc-link-search=C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\build\cortex-m-2fbdccdc1dbb56b8\out +cargo:rustc-cfg=cortex_m +cargo:rustc-cfg=armv7m +cargo:rustc-cfg=armv7em +cargo:rustc-cfg=has_fpu diff --git a/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/root-output b/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/root-output new file mode 100644 index 0000000..603beeb --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/root-output @@ -0,0 +1 @@ +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\build\cortex-m-2fbdccdc1dbb56b8\out \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/stderr b/target/thumbv7em-none-eabihf/debug/build/cortex-m-2fbdccdc1dbb56b8/stderr new file mode 100644 index 0000000..e69de29 diff --git a/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/invoked.timestamp b/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/invoked.timestamp new file mode 100644 index 0000000..e00328d --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/out/link.x b/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/out/link.x new file mode 100644 index 0000000..78d7117 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/out/link.x @@ -0,0 +1,289 @@ +/* # Developer notes + +- Symbols that start with a double underscore (__) are considered "private" + +- Symbols that start with a single underscore (_) are considered "semi-public"; they can be + overridden in a user linker script, but should not be referred from user code (e.g. `extern "C" { + static mut __sbss }`). + +- `EXTERN` forces the linker to keep a symbol in the final binary. We use this to make sure a + symbol is not dropped if it appears in or near the front of the linker arguments and "it's not + needed" by any of the preceding objects (linker arguments) + +- `PROVIDE` is used to provide default values that can be overridden by a user linker script + +- On alignment: it's important for correctness that the VMA boundaries of both .bss and .data *and* + the LMA of .data are all 4-byte aligned. These alignments are assumed by the RAM initialization + routine. There's also a second benefit: 4-byte aligned boundaries means that you won't see + "Address (..) is out of bounds" in the disassembly produced by `objdump`. +*/ + +/* Provides information about the memory layout of the device */ +/* This will be provided by the user (see `memory.x`) or by a Board Support Crate */ +INCLUDE memory.x + +/* # Entry point = reset vector */ +EXTERN(__RESET_VECTOR); +EXTERN(Reset); +ENTRY(Reset); + +/* # Exception vectors */ +/* This is effectively weak aliasing at the linker level */ +/* The user can override any of these aliases by defining the corresponding symbol themselves (cf. + the `exception!` macro) */ +EXTERN(__EXCEPTIONS); /* depends on all the these PROVIDED symbols */ + +EXTERN(DefaultHandler); + +PROVIDE(NonMaskableInt = DefaultHandler); +EXTERN(HardFaultTrampoline); +PROVIDE(MemoryManagement = DefaultHandler); +PROVIDE(BusFault = DefaultHandler); +PROVIDE(UsageFault = DefaultHandler); +PROVIDE(SecureFault = DefaultHandler); +PROVIDE(SVCall = DefaultHandler); +PROVIDE(DebugMonitor = DefaultHandler); +PROVIDE(PendSV = DefaultHandler); +PROVIDE(SysTick = DefaultHandler); + +PROVIDE(DefaultHandler = DefaultHandler_); +PROVIDE(HardFault = HardFault_); + +/* # Interrupt vectors */ +EXTERN(__INTERRUPTS); /* `static` variable similar to `__EXCEPTIONS` */ + +/* # Pre-initialization function */ +/* If the user overrides this using the `pre_init!` macro or by creating a `__pre_init` function, + then the function this points to will be called before the RAM is initialized. */ +PROVIDE(__pre_init = DefaultPreInit); + +/* # Sections */ +SECTIONS +{ + PROVIDE(_ram_start = ORIGIN(RAM)); + PROVIDE(_ram_end = ORIGIN(RAM) + LENGTH(RAM)); + PROVIDE(_stack_start = _ram_end); + + /* ## Sections in FLASH */ + /* ### Vector table */ + .vector_table ORIGIN(FLASH) : + { + __vector_table = .; + + /* Initial Stack Pointer (SP) value. + * We mask the bottom three bits to force 8-byte alignment. + * Despite having an assert for this later, it's possible that a separate + * linker script could override _stack_start after the assert is checked. + */ + LONG(_stack_start & 0xFFFFFFF8); + + /* Reset vector */ + KEEP(*(.vector_table.reset_vector)); /* this is the `__RESET_VECTOR` symbol */ + + /* Exceptions */ + __exceptions = .; /* start of exceptions */ + KEEP(*(.vector_table.exceptions)); /* this is the `__EXCEPTIONS` symbol */ + __eexceptions = .; /* end of exceptions */ + + /* Device specific interrupts */ + KEEP(*(.vector_table.interrupts)); /* this is the `__INTERRUPTS` symbol */ + } > FLASH + + PROVIDE(_stext = ADDR(.vector_table) + SIZEOF(.vector_table)); + + /* ### .text */ + .text _stext : + { + __stext = .; + *(.Reset); + + *(.text .text.*); + + /* The HardFaultTrampoline uses the `b` instruction to enter `HardFault`, + so must be placed close to it. */ + *(.HardFaultTrampoline); + *(.HardFault.*); + + . = ALIGN(4); /* Pad .text to the alignment to workaround overlapping load section bug in old lld */ + __etext = .; + } > FLASH + + /* ### .rodata */ + .rodata : ALIGN(4) + { + . = ALIGN(4); + __srodata = .; + *(.rodata .rodata.*); + + /* 4-byte align the end (VMA) of this section. + This is required by LLD to ensure the LMA of the following .data + section will have the correct alignment. */ + . = ALIGN(4); + __erodata = .; + } > FLASH + + /* ## Sections in RAM */ + /* ### .data */ + .data : ALIGN(4) + { + . = ALIGN(4); + __sdata = .; + *(.data .data.*); + . = ALIGN(4); /* 4-byte align the end (VMA) of this section */ + } > RAM AT>FLASH + /* Allow sections from user `memory.x` injected using `INSERT AFTER .data` to + * use the .data loading mechanism by pushing __edata. Note: do not change + * output region or load region in those user sections! */ + . = ALIGN(4); + __edata = .; + + /* LMA of .data */ + __sidata = LOADADDR(.data); + + /* ### .gnu.sgstubs + This section contains the TrustZone-M veneers put there by the Arm GNU linker. */ + /* Security Attribution Unit blocks must be 32 bytes aligned. */ + /* Note that this pads the FLASH usage to 32 byte alignment. */ + .gnu.sgstubs : ALIGN(32) + { + . = ALIGN(32); + __veneer_base = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + } > FLASH + /* Place `__veneer_limit` outside the `.gnu.sgstubs` section because veneers are + * always inserted last in the section, which would otherwise be _after_ the `__veneer_limit` symbol. + */ + . = ALIGN(32); + __veneer_limit = .; + + /* ### .bss */ + .bss (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __sbss = .; + *(.bss .bss.*); + *(COMMON); /* Uninitialized C statics */ + . = ALIGN(4); /* 4-byte align the end (VMA) of this section */ + } > RAM + /* Allow sections from user `memory.x` injected using `INSERT AFTER .bss` to + * use the .bss zeroing mechanism by pushing __ebss. Note: do not change + * output region or load region in those user sections! */ + . = ALIGN(4); + __ebss = .; + + /* ### .uninit */ + .uninit (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __suninit = .; + *(.uninit .uninit.*); + . = ALIGN(4); + __euninit = .; + } > RAM + + /* Place the heap right after `.uninit` in RAM */ + PROVIDE(__sheap = __euninit); + + /* Place stack end at the end of allocated RAM */ + PROVIDE(_stack_end = __euninit); + + /* ## .got */ + /* Dynamic relocations are unsupported. This section is only used to detect relocatable code in + the input files and raise an error if relocatable code is found */ + .got (NOLOAD) : + { + KEEP(*(.got .got.*)); + } + + /* ## Discarded sections */ + /DISCARD/ : + { + /* Unused exception related info that only wastes space */ + *(.ARM.exidx); + *(.ARM.exidx.*); + *(.ARM.extab.*); + } +} + +/* Do not exceed this mark in the error messages below | */ +/* # Alignment checks */ +ASSERT(ORIGIN(FLASH) % 4 == 0, " +ERROR(cortex-m-rt): the start of the FLASH region must be 4-byte aligned"); + +ASSERT(ORIGIN(RAM) % 4 == 0, " +ERROR(cortex-m-rt): the start of the RAM region must be 4-byte aligned"); + +ASSERT(__sdata % 4 == 0 && __edata % 4 == 0, " +BUG(cortex-m-rt): .data is not 4-byte aligned"); + +ASSERT(__sidata % 4 == 0, " +BUG(cortex-m-rt): the LMA of .data is not 4-byte aligned"); + +ASSERT(__sbss % 4 == 0 && __ebss % 4 == 0, " +BUG(cortex-m-rt): .bss is not 4-byte aligned"); + +ASSERT(__sheap % 4 == 0, " +BUG(cortex-m-rt): start of .heap is not 4-byte aligned"); + +ASSERT(_stack_start % 8 == 0, " +ERROR(cortex-m-rt): stack start address is not 8-byte aligned. +If you have set _stack_start, check it's set to an address which is a multiple of 8 bytes. +If you haven't, stack starts at the end of RAM by default. Check that both RAM +origin and length are set to multiples of 8 in the `memory.x` file."); + +ASSERT(_stack_end % 4 == 0, " +ERROR(cortex-m-rt): end of stack is not 4-byte aligned"); + +ASSERT(_stack_start >= _stack_end, " +ERROR(cortex-m-rt): stack end address is not below stack start."); + +/* # Position checks */ + +/* ## .vector_table + * + * If the *start* of exception vectors is not 8 bytes past the start of the + * vector table, then we somehow did not place the reset vector, which should + * live 4 bytes past the start of the vector table. + */ +ASSERT(__exceptions == ADDR(.vector_table) + 0x8, " +BUG(cortex-m-rt): the reset vector is missing"); + +ASSERT(__eexceptions == ADDR(.vector_table) + 0x40, " +BUG(cortex-m-rt): the exception vectors are missing"); + +ASSERT(SIZEOF(.vector_table) > 0x40, " +ERROR(cortex-m-rt): The interrupt vectors are missing. +Possible solutions, from most likely to less likely: +- Link to a svd2rust generated device crate +- Check that you actually use the device/hal/bsp crate in your code +- Disable the 'device' feature of cortex-m-rt to build a generic application (a dependency +may be enabling it) +- Supply the interrupt handlers yourself. Check the documentation for details."); + +/* ## .text */ +ASSERT(ADDR(.vector_table) + SIZEOF(.vector_table) <= _stext, " +ERROR(cortex-m-rt): The .text section can't be placed inside the .vector_table section +Set _stext to an address greater than the end of .vector_table (See output of `nm`)"); + +ASSERT(_stext > ORIGIN(FLASH) && _stext < ORIGIN(FLASH) + LENGTH(FLASH), " +ERROR(cortex-m-rt): The .text section must be placed inside the FLASH memory. +Set _stext to an address within the FLASH region."); + +/* # Other checks */ +ASSERT(SIZEOF(.got) == 0, " +ERROR(cortex-m-rt): .got section detected in the input object files +Dynamic relocations are not supported. If you are linking to C code compiled using +the 'cc' crate then modify your build script to compile the C code _without_ +the -fPIC flag. See the documentation of the `cc::Build.pic` method for details."); +/* Do not exceed this mark in the error messages above | */ + +/* Provides weak aliases (cf. PROVIDED) for device specific interrupt handlers */ +/* This will usually be provided by a device crate generated using svd2rust (see `device.x`) */ +INCLUDE device.x + +ASSERT(SIZEOF(.vector_table) <= 0x400, " +There can't be more than 240 interrupt handlers. This may be a bug in +your device crate, or you may have registered more than 240 interrupt +handlers."); + diff --git a/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/output b/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/output new file mode 100644 index 0000000..e7e3257 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/output @@ -0,0 +1,11 @@ +cargo:rustc-check-cfg=cfg(armv6m) +cargo:rustc-check-cfg=cfg(armv7m) +cargo:rustc-check-cfg=cfg(armv8m) +cargo:rustc-check-cfg=cfg(cortex_m) +cargo:rustc-check-cfg=cfg(has_fpu) +cargo:rustc-cfg=cortex_m +cargo:rustc-cfg=armv7m +cargo:rustc-cfg=has_fpu +cargo:rustc-link-search=C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\build\cortex-m-rt-3d12c4a594f9b76b\out +cargo:rerun-if-changed=build.rs +cargo:rerun-if-changed=link.x.in diff --git a/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/root-output b/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/root-output new file mode 100644 index 0000000..ced1125 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/root-output @@ -0,0 +1 @@ +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\build\cortex-m-rt-3d12c4a594f9b76b\out \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/stderr b/target/thumbv7em-none-eabihf/debug/build/cortex-m-rt-3d12c4a594f9b76b/stderr new file mode 100644 index 0000000..e69de29 diff --git a/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/invoked.timestamp b/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/invoked.timestamp new file mode 100644 index 0000000..e00328d --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/out/memory.x b/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/out/memory.x new file mode 100644 index 0000000..6f1910a --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/out/memory.x @@ -0,0 +1,16 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* Sections */ +SECTIONS +{ + /* Stack section (placed at the top of RAM) */ + .stack : ALIGN(4){ + _stack_top = ORIGIN(RAM) + LENGTH(RAM); /* Top of the stack */ + . = _stack_top - 0x400; /* Allocate 1 KB for stack */ + _stack_bottom = .; /* Bottom of the stack */ + } > RAM +} diff --git a/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/output b/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/output new file mode 100644 index 0000000..c36a0be --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/output @@ -0,0 +1,13 @@ +cargo:rustc-link-search=C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\build\tivatest-fd57c372eee4e9af\out +cargo:rerun-if-changed=build.rs +cargo:rerun-if-changed=memory.x +cargo:rustc-link=gpio +cargo:rustc-link=uart +cargo:rustc-link=sysctl +cargo:rustc-link=systick +cargo:rustc-link=timer +cargo:rustc-link=i2c +cargo:rustc-link=interrupt +cargo:rustc-link=adc +cargo:rustc-link=ssi +cargo:rustc-link-search=C:\Users\wang\Downloads\TivaCCriticalRegion diff --git a/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/root-output b/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/root-output new file mode 100644 index 0000000..443026d --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/root-output @@ -0,0 +1 @@ +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\build\tivatest-fd57c372eee4e9af\out \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/stderr b/target/thumbv7em-none-eabihf/debug/build/tivatest-fd57c372eee4e9af/stderr new file mode 100644 index 0000000..e69de29 diff --git a/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/invoked.timestamp b/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/invoked.timestamp new file mode 100644 index 0000000..e00328d --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/invoked.timestamp @@ -0,0 +1 @@ +This file has an mtime of when this was started. \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/out/device.x b/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/out/device.x new file mode 100644 index 0000000..98c3a97 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/out/device.x @@ -0,0 +1,79 @@ +PROVIDE(GPIOA = DefaultHandler); +PROVIDE(GPIOB = DefaultHandler); +PROVIDE(GPIOC = DefaultHandler); +PROVIDE(GPIOD = DefaultHandler); +PROVIDE(GPIOE = DefaultHandler); +PROVIDE(UART0 = DefaultHandler); +PROVIDE(UART1 = DefaultHandler); +PROVIDE(SSI0 = DefaultHandler); +PROVIDE(I2C0 = DefaultHandler); +PROVIDE(PWM0_FAULT = DefaultHandler); +PROVIDE(PWM0_0 = DefaultHandler); +PROVIDE(PWM0_1 = DefaultHandler); +PROVIDE(PWM0_2 = DefaultHandler); +PROVIDE(QEI0 = DefaultHandler); +PROVIDE(ADC0SS0 = DefaultHandler); +PROVIDE(ADC0SS1 = DefaultHandler); +PROVIDE(ADC0SS2 = DefaultHandler); +PROVIDE(ADC0SS3 = DefaultHandler); +PROVIDE(WATCHDOG = DefaultHandler); +PROVIDE(TIMER0A = DefaultHandler); +PROVIDE(TIMER0B = DefaultHandler); +PROVIDE(TIMER1A = DefaultHandler); +PROVIDE(TIMER1B = DefaultHandler); +PROVIDE(TIMER2A = DefaultHandler); +PROVIDE(TIMER2B = DefaultHandler); +PROVIDE(COMP0 = DefaultHandler); +PROVIDE(COMP1 = DefaultHandler); +PROVIDE(SYSCTL = DefaultHandler); +PROVIDE(FLASH = DefaultHandler); +PROVIDE(GPIOF = DefaultHandler); +PROVIDE(UART2 = DefaultHandler); +PROVIDE(SSI1 = DefaultHandler); +PROVIDE(TIMER3A = DefaultHandler); +PROVIDE(TIMER3B = DefaultHandler); +PROVIDE(I2C1 = DefaultHandler); +PROVIDE(QEI1 = DefaultHandler); +PROVIDE(CAN0 = DefaultHandler); +PROVIDE(CAN1 = DefaultHandler); +PROVIDE(HIBERNATE = DefaultHandler); +PROVIDE(USB0 = DefaultHandler); +PROVIDE(PWM0_3 = DefaultHandler); +PROVIDE(UDMA = DefaultHandler); +PROVIDE(UDMAERR = DefaultHandler); +PROVIDE(ADC1SS0 = DefaultHandler); +PROVIDE(ADC1SS1 = DefaultHandler); +PROVIDE(ADC1SS2 = DefaultHandler); +PROVIDE(ADC1SS3 = DefaultHandler); +PROVIDE(SSI2 = DefaultHandler); +PROVIDE(SSI3 = DefaultHandler); +PROVIDE(UART3 = DefaultHandler); +PROVIDE(UART4 = DefaultHandler); +PROVIDE(UART5 = DefaultHandler); +PROVIDE(UART6 = DefaultHandler); +PROVIDE(UART7 = DefaultHandler); +PROVIDE(I2C2 = DefaultHandler); +PROVIDE(I2C3 = DefaultHandler); +PROVIDE(TIMER4A = DefaultHandler); +PROVIDE(TIMER4B = DefaultHandler); +PROVIDE(TIMER5A = DefaultHandler); +PROVIDE(TIMER5B = DefaultHandler); +PROVIDE(WTIMER0A = DefaultHandler); +PROVIDE(WTIMER0B = DefaultHandler); +PROVIDE(WTIMER1A = DefaultHandler); +PROVIDE(WTIMER1B = DefaultHandler); +PROVIDE(WTIMER2A = DefaultHandler); +PROVIDE(WTIMER2B = DefaultHandler); +PROVIDE(WTIMER3A = DefaultHandler); +PROVIDE(WTIMER3B = DefaultHandler); +PROVIDE(WTIMER4A = DefaultHandler); +PROVIDE(WTIMER4B = DefaultHandler); +PROVIDE(WTIMER5A = DefaultHandler); +PROVIDE(WTIMER5B = DefaultHandler); +PROVIDE(SYSEXC = DefaultHandler); +PROVIDE(PWM1_0 = DefaultHandler); +PROVIDE(PWM1_1 = DefaultHandler); +PROVIDE(PWM1_2 = DefaultHandler); +PROVIDE(PWM1_3 = DefaultHandler); +PROVIDE(PWM1_FAULT = DefaultHandler); + diff --git a/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/output b/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/output new file mode 100644 index 0000000..79b2ffd --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/output @@ -0,0 +1,3 @@ +cargo:rustc-link-search=C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\build\tm4c123x-18500a0766a93d50\out +cargo:rerun-if-changed=device.x +cargo:rerun-if-changed=build.rs diff --git a/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/root-output b/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/root-output new file mode 100644 index 0000000..db228c5 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/root-output @@ -0,0 +1 @@ +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\build\tm4c123x-18500a0766a93d50\out \ No newline at end of file diff --git a/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/stderr b/target/thumbv7em-none-eabihf/debug/build/tm4c123x-18500a0766a93d50/stderr new file mode 100644 index 0000000..e69de29 diff --git a/target/thumbv7em-none-eabihf/debug/deps/bare_metal-fb126c6a2797d884.d b/target/thumbv7em-none-eabihf/debug/deps/bare_metal-fb126c6a2797d884.d new file mode 100644 index 0000000..bb779d8 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/deps/bare_metal-fb126c6a2797d884.d @@ -0,0 +1,7 @@ +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libbare_metal-fb126c6a2797d884.rmeta: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\bare-metal-0.2.5\src\lib.rs + +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libbare_metal-fb126c6a2797d884.rlib: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\bare-metal-0.2.5\src\lib.rs + +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\bare_metal-fb126c6a2797d884.d: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\bare-metal-0.2.5\src\lib.rs + +C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\bare-metal-0.2.5\src\lib.rs: diff --git a/target/thumbv7em-none-eabihf/debug/deps/bitfield-df2d0655c3754a99.d b/target/thumbv7em-none-eabihf/debug/deps/bitfield-df2d0655c3754a99.d new file mode 100644 index 0000000..ced97d9 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/deps/bitfield-df2d0655c3754a99.d @@ -0,0 +1,7 @@ +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libbitfield-df2d0655c3754a99.rmeta: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\bitfield-0.13.2\src\lib.rs + +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libbitfield-df2d0655c3754a99.rlib: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\bitfield-0.13.2\src\lib.rs + +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\bitfield-df2d0655c3754a99.d: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\bitfield-0.13.2\src\lib.rs + +C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\bitfield-0.13.2\src\lib.rs: diff --git a/target/thumbv7em-none-eabihf/debug/deps/cortex_m-83c93be35d4a3fb2.d b/target/thumbv7em-none-eabihf/debug/deps/cortex_m-83c93be35d4a3fb2.d new file mode 100644 index 0000000..e63368b --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/deps/cortex_m-83c93be35d4a3fb2.d @@ -0,0 +1,38 @@ +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libcortex_m-83c93be35d4a3fb2.rmeta: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\lib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\call_asm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\macros.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\asm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\critical_section.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\delay.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\interrupt.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\itm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\mod.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\cbp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\cpuid.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\dcb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\dwt.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\fpb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\fpu.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\icb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\itm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\mpu.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\nvic.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\scb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\syst.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\peripheral\tpiu.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\prelude.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\register\mod.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\register\basepri.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\register\basepri_max.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\register\control.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\register\faultmask.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\register\fpscr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\register\msp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\register\primask.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\register\psp.rs + +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libcortex_m-83c93be35d4a3fb2.rlib: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\lib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\call_asm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\macros.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\asm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\critical_section.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\cortex-m-0.7.7\src\delay.rs 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b/target/thumbv7em-none-eabihf/debug/deps/nb-e0f7d2763d7cce1c.d new file mode 100644 index 0000000..85515f2 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/deps/nb-e0f7d2763d7cce1c.d @@ -0,0 +1,7 @@ +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libnb-e0f7d2763d7cce1c.rmeta: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\nb-0.1.3\src\lib.rs + +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libnb-e0f7d2763d7cce1c.rlib: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\nb-0.1.3\src\lib.rs + +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\nb-e0f7d2763d7cce1c.d: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\nb-0.1.3\src\lib.rs + +C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\nb-0.1.3\src\lib.rs: diff --git a/target/thumbv7em-none-eabihf/debug/deps/panic_halt-39fb3ba835a8d777.d b/target/thumbv7em-none-eabihf/debug/deps/panic_halt-39fb3ba835a8d777.d new file mode 100644 index 0000000..0b1b258 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/deps/panic_halt-39fb3ba835a8d777.d @@ -0,0 +1,7 @@ +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libpanic_halt-39fb3ba835a8d777.rmeta: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\panic-halt-0.2.0\src\lib.rs + +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libpanic_halt-39fb3ba835a8d777.rlib: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\panic-halt-0.2.0\src\lib.rs + +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\panic_halt-39fb3ba835a8d777.d: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\panic-halt-0.2.0\src\lib.rs + +C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\panic-halt-0.2.0\src\lib.rs: diff --git a/target/thumbv7em-none-eabihf/debug/deps/tivatest-3e8a4d3a4d203afa b/target/thumbv7em-none-eabihf/debug/deps/tivatest-3e8a4d3a4d203afa new file mode 100644 index 0000000..b01ee49 Binary files /dev/null and b/target/thumbv7em-none-eabihf/debug/deps/tivatest-3e8a4d3a4d203afa differ diff --git a/target/thumbv7em-none-eabihf/debug/deps/tivatest-3e8a4d3a4d203afa.d b/target/thumbv7em-none-eabihf/debug/deps/tivatest-3e8a4d3a4d203afa.d new file mode 100644 index 0000000..65b72a1 --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/deps/tivatest-3e8a4d3a4d203afa.d @@ -0,0 +1,10 @@ +C:\Users\wang\Downloads\TivaCMutexCNT\target\thumbv7em-none-eabihf\debug\deps\tivatest-3e8a4d3a4d203afa: src/main.rs src\sysctl.rs src\tm123.rs src\timer.rs src\int.rs src\gpio.rs + +C:\Users\wang\Downloads\TivaCMutexCNT\target\thumbv7em-none-eabihf\debug\deps\tivatest-3e8a4d3a4d203afa.d: src/main.rs src\sysctl.rs src\tm123.rs src\timer.rs src\int.rs src\gpio.rs + +src/main.rs: +src\sysctl.rs: +src\tm123.rs: +src\timer.rs: +src\int.rs: +src\gpio.rs: diff --git a/target/thumbv7em-none-eabihf/debug/deps/tm4c123x-57403112b8347914.d b/target/thumbv7em-none-eabihf/debug/deps/tm4c123x-57403112b8347914.d new file mode 100644 index 0000000..538caaa --- /dev/null +++ b/target/thumbv7em-none-eabihf/debug/deps/tm4c123x-57403112b8347914.d @@ -0,0 +1,769 @@ +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libtm4c123x-57403112b8347914.rmeta: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\lib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\generic.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0\load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0\value.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\pc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\sync.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\enable.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\invert.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\fault.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\isc.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_0_minfltper.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_isc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_count.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_cmpa.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_cmpb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_gena.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_genb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_dbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_dbrise.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_dbfall.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltsrc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltsrc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_minfltper.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_isc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_count.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_cmpa.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_cmpb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_gena.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_genb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_dbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_dbrise.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_dbfall.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltsrc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltsrc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_minfltper.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_isc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_count.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_cmpa.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_cmpb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_gena.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_genb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_dbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_dbrise.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_dbfall.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltsrc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltsrc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_minfltper.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_0_fltsen.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_0_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_0_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltsen.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\stat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\pos.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\maxpos.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\time.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\count.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\speed.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\isc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\cfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tamr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbmr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\sync.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\imr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\icr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tailr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbilr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tamatchr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbmatchr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tapr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbpr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tapmr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbpmr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tar.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dcctl6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dcctl7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\pc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\cc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acmis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acinten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acrefctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acstat0.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\tst.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\brpe.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1crq.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1cmsk.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1msk1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1msk2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1arb1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1arb2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1mctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1da1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1da2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1db1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1db2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2crq.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2cmsk.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2msk1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2msk2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2arb1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2arb2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2mctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2da1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2da2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2db1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2db2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\txrq1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\txrq2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\nwda1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\nwda2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\msg1int.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\msg2int.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\msg1val.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\msg2val.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\faddr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\power.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txie.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxie.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\is.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\ie.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\frame.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\epidx.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\test.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\devctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfifosz.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfifosz.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfifoadd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfifoadd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\contim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vplen.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fseof.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\lseof.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\csrl0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\csrh0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\count0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\type0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\naklmt.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxdpktbufdis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txdpktbufdis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\epc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\epcris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\epcim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\epcisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\drris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\drim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\drisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\gpcs.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdcris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdcim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdcisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\idvris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\idvim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\idvisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\dmasel.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eesize.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eeblock.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eeoffset.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eerdwr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eerdwrinc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eedone.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eesupp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eeunlock.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eeprot.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eepass0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eepass1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eepass2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eeint.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eehide.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eedbgme.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysexc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysexc\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysexc\im.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysexc\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysexc\ic.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\rtcc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\rtcm0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\rtcld.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\im.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\ic.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\rtct.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\rtcss.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\data.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fcris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fcim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fcmisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fwbval.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fwbn.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fsize.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\ssize.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\romswmap.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\rmctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\bootcfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\did0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\did1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc8.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pborctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srcr0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srcr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srcr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\imc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\misc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\resc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\gpiohbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\moscctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dslpclkcfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sysprop.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\piosccal.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pioscstat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pllfreq0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pllfreq1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pllstat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\slppwrcfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dslppwrcfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc9.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\nvmstat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ldospctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ldodpctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pptimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pphib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppuart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppi2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppcan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppadc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppacmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pppwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppeeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srhib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sruart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sri2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srcan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sradc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sracmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srpwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sreeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgctimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgchib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcuart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgci2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgccan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcadc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcacmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcpwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgceeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgctimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgchib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcuart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgci2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgccan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcadc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcacmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcpwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgceeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgctimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgchib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcuart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgci2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgccan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcadc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcacmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcpwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgceeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prhib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pruart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pri2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prcan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pradc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pracmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prpwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\preeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\stat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\cfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\ctlbase.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\altbase.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\waitstat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\swreq.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\useburstset.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\useburstclr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\reqmaskset.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\reqmaskclr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\enaset.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\enaclr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\altset.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\altclr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\prioset.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\prioclr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\errclr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\chasgn.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\chis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\chmap0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\chmap1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\chmap2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\chmap3.rs + +C:\Users\wang\Downloads\TivaCCriticalRegion\target\thumbv7em-none-eabihf\debug\deps\libtm4c123x-57403112b8347914.rlib: C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\lib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\generic.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0\load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0\value.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0\icr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0\test.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\watchdog0\lock.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\data.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\dir.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\is.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\ibe.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\iev.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\im.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\icr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\afsel.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\dr2r.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\dr4r.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\dr8r.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\odr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\pur.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\pdr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\slr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\den.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\lock.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\cr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\amsel.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\pctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\adcctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\gpio_porta\dmactl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0\cr0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0\cr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0\dr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0\sr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0\cpsr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0\im.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0\icr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0\dmactl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\ssi0\cc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\dr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\rsr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\ecr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\fr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\ilpr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\ibrd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\fbrd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\lcrh.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\ifls.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\im.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\icr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\dmactl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\_9bitaddr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\_9bitamask.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\uart0\cc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\msa.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\mcs.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\mdr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\mtpr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\mimr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\mris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\mmis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\micr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\mcr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\mclkocnt.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\mbmon.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\mcr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\soar.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\scsr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\sdr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\simr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\sris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\smis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\sicr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\soar2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\sackctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\i2c0\pc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\sync.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\enable.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\invert.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\fault.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\isc.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_0_minfltper.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_isc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_count.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_cmpa.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_cmpb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_gena.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_genb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_dbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_dbrise.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_dbfall.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltsrc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltsrc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_minfltper.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_isc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_count.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_cmpa.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_cmpb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_gena.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_genb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_dbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_dbrise.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_dbfall.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltsrc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltsrc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_minfltper.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_isc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_count.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_cmpa.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_cmpb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_gena.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_genb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_dbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_dbrise.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_dbfall.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltsrc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltsrc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_minfltper.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_0_fltsen.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_0_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_0_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltsen.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\stat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\pos.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\maxpos.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\time.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\count.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\speed.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\isc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\cfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tamr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbmr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\sync.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\imr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\icr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tailr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbilr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tamatchr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbmatchr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tapr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbpr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tapmr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbpmr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tar.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tav.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbv.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\rtcpd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\taps.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbps.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tapv.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbpv.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\pp.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dcctl6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dcctl7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\pc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\cc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acmis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acinten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acrefctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acctl0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acctl1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\sts.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\err.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\bit_.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\int.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\tst.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\brpe.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1crq.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1cmsk.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1msk1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1msk2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1arb1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1arb2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1mctl.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2arb2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2mctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2da1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2da2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2db1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2db2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\txrq1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\txrq2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\nwda1.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\devctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfifosz.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfifosz.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfifoadd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfifoadd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\contim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vplen.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fseof.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\lseof.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\csrl0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\csrh0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\count0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\type0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\naklmt.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxdpktbufdis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txdpktbufdis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\epc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\epcris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\epcim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\epcisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\drris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\drim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\drisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\gpcs.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdcris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdcim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdcisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\idvris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\idvim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\idvisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\dmasel.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eesize.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eeblock.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eeoffset.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eerdwr.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eehide.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\eedbgme.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\eeprom\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysexc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysexc\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysexc\im.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysexc\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysexc\ic.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\rtcc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\rtcm0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\rtcld.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\im.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\ic.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\rtct.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\rtcss.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\hib\data.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fcris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fcim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fcmisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fwbval.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fwbn.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fsize.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\ssize.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\romswmap.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\rmctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\bootcfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\did0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\did1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc6.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\resc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\gpiohbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\moscctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dslpclkcfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sysprop.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\piosccal.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pioscstat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pllfreq0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pllfreq1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pllstat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\slppwrcfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dslppwrcfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc9.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\nvmstat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ldospctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ldodpctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pptimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pphib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppuart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppi2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppcan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppadc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppacmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pppwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppeeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ppwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srhib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sruart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sri2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srcan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sradc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sracmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srpwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\sreeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\srwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgctimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgchib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcuart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgci2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgccan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcadc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcacmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcpwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgceeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgcwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgctimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgchib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcuart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgci2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgccan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcadc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcacmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcpwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgceeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgcwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgctimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgchib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcuart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgci2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgccan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcadc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcacmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcpwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgceeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dcgcwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prwd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prgpio.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prdma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prhib.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pruart.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prssi.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pri2c.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prusb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prcan.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pradc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pracmp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prpwm.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prqei.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\preeprom.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\prwtimer.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\stat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\cfg.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\enaclr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\altset.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\altclr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\prioset.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\prioclr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\errclr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\chasgn.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\chis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\udma\chmap0.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_gena.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_genb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_dbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_dbrise.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_dbfall.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltsrc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltsrc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_minfltper.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_isc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_count.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_cmpa.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_cmpb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_gena.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_genb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_dbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_dbrise.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_dbfall.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltsrc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltsrc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_minfltper.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_isc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_count.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_cmpa.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_cmpb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_gena.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_genb.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_dbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_dbrise.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_dbfall.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltsrc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltsrc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_minfltper.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_0_fltsen.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_0_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_0_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltsen.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_1_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_2_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\_3_fltstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\pwm0\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\stat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\pos.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\maxpos.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\load.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\time.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\count.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\speed.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\inten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\qei0\isc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\cfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tamr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbmr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\sync.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\imr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\icr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tailr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbilr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tamatchr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbmatchr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tapr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbpr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tapmr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbpmr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tar.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tav.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbv.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\rtcpd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\taps.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbps.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tapv.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\tbpv.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\timer0\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\cfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\tamr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\tbmr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\sync.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\imr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\ris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\mis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\icr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\tailr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\tbilr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\tamatchr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\tbmatchr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\tapr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\tbpr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\tapmr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\wtimer0\tbpmr.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\dccmp7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\pc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\adc0\cc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acmis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acinten.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acrefctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acstat0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acctl0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acstat1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\acctl1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\comp\pp.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\ctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\sts.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\err.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\bit_.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\int.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\tst.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\brpe.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1crq.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1cmsk.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1msk1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1msk2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1arb1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1arb2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1mctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1da1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1da2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1db1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if1db2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2crq.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2cmsk.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2msk1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2msk2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2arb1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2arb2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2mctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2da1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2da2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2db1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\if2db2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\txrq1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\txrq2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\nwda1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\nwda2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\msg1int.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\msg2int.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\msg1val.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\can0\msg2val.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\faddr.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\power.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxis.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txie.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxie.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\is.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\ie.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\frame.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\epidx.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\test.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fifo7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\devctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfifosz.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfifosz.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfifoadd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfifoadd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\contim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vplen.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\fseof.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\lseof.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txfuncaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txhubport7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxfuncaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubaddr7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxhubport7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\csrl0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\csrh0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\count0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\type0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\naklmt.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval6.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txmaxp7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrl7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txcsrh7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxmaxp7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrl7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcsrh7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxcount7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txtype7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\txinterval7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxtype7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rxinterval7.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\rqpktcount3.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\epcisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\drris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\drim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\drisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\gpcs.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdcris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdcim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\vdcisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\usb0\idvris.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fma.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmd.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fcris.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fcim.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fcmisc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fwbval.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fwbn.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fsize.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\ssize.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\romswmap.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\rmctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\bootcfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\userreg3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmpre3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\flash_ctrl\fmppe3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\did0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\did1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc3.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc4.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc5.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc6.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\resc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcc.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\gpiohbctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\moscctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgc0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgc1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\rcgc2.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\scgc0.rs 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C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pllfreq0.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pllfreq1.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\pllstat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\slppwrcfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dslppwrcfg.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\dc9.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\nvmstat.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ldospctl.rs C:\Users\wang\.cargo\registry\src\index.crates.io-6f17d22bba15001f\tm4c123x-0.9.2\src\sysctl\ldodpctl.rs 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