Crane 2026 LPV Controller — RTIC Timer Jitter Measurement

This repository contains the Rust/RTIC firmware for the Crane 2026 Low Profile Vessel (LPV) controller on the STM32F303VC. In addition to CAN, iBUS, and PWM control, the firmware measures the timing jitter of a high-priority periodic hardware-timer interrupt.

Firmware Features

RTIC 2 real-time task scheduling
TIM6 high-priority interrupt every 20 ms
Cortex-M4 DWT cycle-counter timing
1005 timer-period measurements stored before logging begins
RTT CSV output after the measurement timer stops
FlySky iBUS input on USART1 at 115200 baud
bxCAN communication
TIM4 PWM outputs on PB6 and PB7

Hardware Connections

Function	Pin	Description
CAN_RX	PD0	bxCAN receive
CAN_TX	PD1	bxCAN transmit
PWM_OUT1	PB6	TIM4 channel 1
PWM_OUT2	PB7	TIM4 channel 2
USART1_TX	PA9	USART1 transmit
USART1_RX	PA10	FlySky iBUS receive

RTIC Tasks and Interrupts

Task	Priority	Trigger	Purpose
`timer_jitter_irq`	5	TIM6 update interrupt	Captures the DWT count and records each 20 ms interrupt delta.
`set_both`	4	Software task	Updates both PWM outputs.
`usart1_irq`	3	USART1 RX interrupt	Reads incoming iBUS bytes into the queue.
`handle_ibus`	3	Software task	Applies decoded iBUS channel data.
`on_can_rx0`	2	CAN FIFO0 interrupt	Processes incoming CAN frames.
`process_rx`	1	Software task	Parses queued iBUS bytes.
`dump_timer_jitter`	1	Software task	Writes the completed timer-jitter capture through RTT.

Timer Jitter Measurement

TIM6 is configured as a periodic hardware timer with a 20 ms period. Its RTIC interrupt task runs at priority 5, above the other application tasks.

The Cortex-M4 DWT cycle counter runs at the 48 MHz CPU clock:

Expected delta = 48,000,000 cycles/s × 0.020 s
               = 960,000 cycles

At the beginning of each TIM6 ISR, the firmware reads the DWT cycle counter and calculates:

delta_cycles  = current_cycle - previous_cycle
jitter_cycles = delta_cycles - 960,000

The subtraction uses wrapping cycle-counter arithmetic. Positive jitter means the interrupt was observed late relative to the previous interrupt; negative jitter means the measured interval was shorter than the nominal interval.

The first timer interrupt establishes the timestamp baseline. The firmware then records 1005 valid deltas, so the complete capture requires 1006 timer interrupts and takes approximately 20.12 seconds.

After the 1005th delta is recorded, the firmware:

Disables the TIM6 update interrupt.
Stops TIM6 so no additional jitter samples are collected.
Spawns the lower-priority dump_timer_jitter task.
Prints the stored data through RTT.

No RTT output occurs while the timing samples are being collected.

RTT Output Format

The output is CSV-formatted:

sample,delta_cycles,jitter_cycles
0,960002,2
1,959999,-1
2,960000,0

Samples are numbered from 0 through 1004.

Build and Record the Jitter Log

Install the Rust target and probe-rs tools if they are not already installed:

rustup target add thumbv7em-none-eabihf
cargo install probe-rs-tools

Connect the STM32F303VC board and open another terminal in VS Code. From the repository root, build the firmware:

cargo build

Then flash and run it with probe-rs while redirecting the RTT output to a CSV file:

probe-rs run --chip STM32F303VCTx target/thumbv7em-none-eabihf/debug/stm32f3-lpv-rtic > jitter_log.csv

Keep the command running for at least 21 seconds so the 1005-point capture can finish and the dump task can write the complete log. Stop probe-rs with Ctrl+C after the CSV output has appeared.

The resulting file is:

jitter_log.csv

Repository Structure

Crane2026_lpv_rtic_jitter/
├── .cargo/config.toml    # Embedded target and runner configuration
├── src/main.rs           # RTIC application and timer-jitter capture
├── Cargo.toml            # Rust package and dependency configuration
├── memory.x              # STM32 memory layout
└── README.md              # Project documentation

Notes

The expected delta assumes the DWT counter runs at the configured 48 MHz system clock.
The measurement reports interrupt-to-interrupt interval variation in CPU cycles; it does not measure USART1 byte-arrival jitter.
TIM6 priority 5 allows it to preempt the application tasks at priorities 1–4.
RTT logging starts only after TIM6 has stopped, preventing the CSV output from disturbing the captured timing data.

References

wang32/Crane2026_lpv_rtic_tim6int_jitter

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