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Guoping Wang
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Mar 29, 2025
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# default runner starts a GDB sesssion, which requires OpenOCD to be | ||
# running, e.g., | ||
## openocd -s C:\OpenOCD\openocd\scripts -f board/ti_ek-tm4c123gxl.cfg | ||
# depending on your local GDB, pick one of the following | ||
[target.thumbv7em-none-eabihf] | ||
runner = "arm-none-eabi-gdb -q -x openocd.gdb" | ||
rustflags = [ | ||
"-C", "link-arg=-Tlink.x", | ||
] | ||
[build] | ||
target = "thumbv7em-none-eabihf" |
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[package] | ||
name = "tivatest" | ||
version = "0.1.0" | ||
edition = "2021" | ||
build="build.rs" | ||
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[dependencies] | ||
cortex-m = "0.7" | ||
cortex-m-rt = {version="0.7",features=["device"]} | ||
tm4c123x = {version="0.9.2", features=["rt"]} | ||
embedded-hal = "0.2" | ||
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[dependencies.panic-halt] | ||
version = "0.2" |
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use std::env; | ||
use std::fs::File; | ||
use std::io::Write; | ||
use std::path::PathBuf; | ||
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fn main() { | ||
// Put the linker script somewhere the linker can find it | ||
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); | ||
File::create(out.join("memory.x")) | ||
.unwrap() | ||
.write_all(include_bytes!("memory.x")) | ||
.unwrap(); | ||
println!("cargo:rustc-link-search={}", out.display()); | ||
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println!("cargo:rerun-if-changed=build.rs"); | ||
println!("cargo:rerun-if-changed=memory.x"); | ||
// tell rustc to link with some driverlib library | ||
println!("cargo:rustc-link=gpio"); | ||
println!("cargo:rustc-link=uart"); | ||
println!("cargo:rustc-link=sysctl"); | ||
println!("cargo:rustc-link=systick"); | ||
println!("cargo:rustc-link=timer"); | ||
println!("cargo:rustc-link=i2c"); | ||
println!("cargo:rustc-link=interrupt"); | ||
println!("cargo:rustc-link=adc"); | ||
println!("cargo:rustc-link=ssi"); | ||
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// and it should search the Cargo.toml directory for that library | ||
println!("cargo:rustc-link-search={}", std::env::var("CARGO_MANIFEST_DIR").unwrap()); | ||
} | ||
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PROVIDE(GPIOA = DefaultHandler); | ||
PROVIDE(GPIOB = DefaultHandler); | ||
PROVIDE(GPIOC = DefaultHandler); | ||
PROVIDE(GPIOD = DefaultHandler); | ||
PROVIDE(GPIOE = DefaultHandler); | ||
PROVIDE(UART0 = DefaultHandler); | ||
PROVIDE(UART1 = DefaultHandler); | ||
PROVIDE(SSI0 = DefaultHandler); | ||
PROVIDE(I2C0 = DefaultHandler); | ||
PROVIDE(PWM0_FAULT = DefaultHandler); | ||
PROVIDE(PWM0_0 = DefaultHandler); | ||
PROVIDE(PWM0_1 = DefaultHandler); | ||
PROVIDE(PWM0_2 = DefaultHandler); | ||
PROVIDE(QEI0 = DefaultHandler); | ||
PROVIDE(ADC0SS0 = DefaultHandler); | ||
PROVIDE(ADC0SS1 = DefaultHandler); | ||
PROVIDE(ADC0SS2 = DefaultHandler); | ||
PROVIDE(ADC0SS3 = DefaultHandler); | ||
PROVIDE(WATCHDOG = DefaultHandler); | ||
PROVIDE(TIMER0A = DefaultHandler); | ||
PROVIDE(TIMER0B = DefaultHandler); | ||
PROVIDE(TIMER1A = DefaultHandler); | ||
PROVIDE(TIMER1B = DefaultHandler); | ||
PROVIDE(TIMER2A = DefaultHandler); | ||
PROVIDE(TIMER2B = DefaultHandler); | ||
PROVIDE(COMP0 = DefaultHandler); | ||
PROVIDE(COMP1 = DefaultHandler); | ||
PROVIDE(SYSCTL = DefaultHandler); | ||
PROVIDE(FLASH = DefaultHandler); | ||
PROVIDE(GPIOF = DefaultHandler); | ||
PROVIDE(UART2 = DefaultHandler); | ||
PROVIDE(SSI1 = DefaultHandler); | ||
PROVIDE(TIMER3A = DefaultHandler); | ||
PROVIDE(TIMER3B = DefaultHandler); | ||
PROVIDE(I2C1 = DefaultHandler); | ||
PROVIDE(QEI1 = DefaultHandler); | ||
PROVIDE(CAN0 = DefaultHandler); | ||
PROVIDE(CAN1 = DefaultHandler); | ||
PROVIDE(HIBERNATE = DefaultHandler); | ||
PROVIDE(USB0 = DefaultHandler); | ||
PROVIDE(PWM0_3 = DefaultHandler); | ||
PROVIDE(UDMA = DefaultHandler); | ||
PROVIDE(UDMAERR = DefaultHandler); | ||
PROVIDE(ADC1SS0 = DefaultHandler); | ||
PROVIDE(ADC1SS1 = DefaultHandler); | ||
PROVIDE(ADC1SS2 = DefaultHandler); | ||
PROVIDE(ADC1SS3 = DefaultHandler); | ||
PROVIDE(SSI2 = DefaultHandler); | ||
PROVIDE(SSI3 = DefaultHandler); | ||
PROVIDE(UART3 = DefaultHandler); | ||
PROVIDE(UART4 = DefaultHandler); | ||
PROVIDE(UART5 = DefaultHandler); | ||
PROVIDE(UART6 = DefaultHandler); | ||
PROVIDE(UART7 = DefaultHandler); | ||
PROVIDE(I2C2 = DefaultHandler); | ||
PROVIDE(I2C3 = DefaultHandler); | ||
PROVIDE(TIMER4A = DefaultHandler); | ||
PROVIDE(TIMER4B = DefaultHandler); | ||
PROVIDE(TIMER5A = DefaultHandler); | ||
PROVIDE(TIMER5B = DefaultHandler); | ||
PROVIDE(WTIMER0A = DefaultHandler); | ||
PROVIDE(WTIMER0B = DefaultHandler); | ||
PROVIDE(WTIMER1A = DefaultHandler); | ||
PROVIDE(WTIMER1B = DefaultHandler); | ||
PROVIDE(WTIMER2A = DefaultHandler); | ||
PROVIDE(WTIMER2B = DefaultHandler); | ||
PROVIDE(WTIMER3A = DefaultHandler); | ||
PROVIDE(WTIMER3B = DefaultHandler); | ||
PROVIDE(WTIMER4A = DefaultHandler); | ||
PROVIDE(WTIMER4B = DefaultHandler); | ||
PROVIDE(WTIMER5A = DefaultHandler); | ||
PROVIDE(WTIMER5B = DefaultHandler); | ||
PROVIDE(SYSEXC = DefaultHandler); | ||
PROVIDE(PWM1_0 = DefaultHandler); | ||
PROVIDE(PWM1_1 = DefaultHandler); | ||
PROVIDE(PWM1_2 = DefaultHandler); | ||
PROVIDE(PWM1_3 = DefaultHandler); | ||
PROVIDE(PWM1_FAULT = DefaultHandler); | ||
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MEMORY | ||
{ | ||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 | ||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 | ||
} | ||
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/* Sections */ | ||
SECTIONS | ||
{ | ||
/* Stack section (placed at the top of RAM) */ | ||
.stack : ALIGN(4){ | ||
_stack_top = ORIGIN(RAM) + LENGTH(RAM); /* Top of the stack */ | ||
. = _stack_top - 0x400; /* Allocate 1 KB for stack */ | ||
_stack_bottom = .; /* Bottom of the stack */ | ||
} > RAM | ||
} |
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target extended-remote :3333 | ||
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# print demangled symbols | ||
set print asm-demangle on | ||
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# Reset and halt the target | ||
monitor reset halt | ||
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# detect unhandled exceptions, hard faults and panics | ||
break DefaultHandler | ||
break UserHardFault | ||
break rust_begin_unwind | ||
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# *try* to stop at the user entry point (it might be gone due to inlining) | ||
break main | ||
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#monitor arm semihosting enable | ||
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# # send captured ITM to the file itm.fifo | ||
# # (the microcontroller SWO pin must be connected to the programmer SWO pin) | ||
# # 8000000 must match the core clock frequency | ||
# monitor tpiu config internal itm.txt uart off 8000000 | ||
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# # OR: make the microcontroller SWO pin output compatible with UART (8N1) | ||
# # 8000000 must match the core clock frequency | ||
# # 2000000 is the frequency of the SWO pin | ||
# monitor tpiu config external uart off 8000000 2000000 | ||
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# # enable ITM port 0 | ||
# monitor itm port 0 on | ||
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load | ||
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# start the process but immediately halt the processor | ||
#stepi |
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